Update PCI bus driver to support non-standard PCI to PCI bridge I/O window alignment, such as 2K/1K/512 byte. Feature PCD PcdPciBridgeIoAlignmentProbe is introduced to turn on/off this feature.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9598 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -469,6 +469,36 @@ GatherPpbInfo (
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}
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}
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//
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// if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes
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// PCI bridge supporting non-stardard I/O window alignment less than 4K.
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//
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PciIoDevice->BridgeIoAlignment = 0xFFF;
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if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe)) {
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//
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// Check any bits of bit 3-1 of I/O Base Register are writable.
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// if so, it is assumed non-stardard I/O window alignment is supported by this bridge.
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// Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
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//
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Value = Temp ^ (BIT3 | BIT2 | BIT1);
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
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PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
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PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
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Value = (Value ^ Temp) & (BIT3 | BIT2 | BIT1);
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switch (Value) {
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case BIT3:
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PciIoDevice->BridgeIoAlignment = 0x7FF;
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break;
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case BIT3 | BIT2:
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PciIoDevice->BridgeIoAlignment = 0x3FF;
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break;
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case BIT3 | BIT2 | BIT1:
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PciIoDevice->BridgeIoAlignment = 0x1FF;
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break;
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}
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}
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Status = BarExisted (
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PciIoDevice,
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0x24,
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