From 1f3b1eb3082206e4efc4091982a208022b86c7ca Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 5 Mar 2020 13:49:32 +0100 Subject: [PATCH] ArmPkg/ArmMmuLib ARM: drop memory type check for page tables We already expect normal memory to be mapped writeback cacheable if EDK2 itself is to make use of it, so doing an early sanity check on the memory type of the allocation that the page tables happened to land in isn't very useful. So let's drop it. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index a6f44dbd5f..15e836e75e 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -328,7 +328,6 @@ ArmConfigureMmu ( ) { VOID *TranslationTable; - ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute; UINT32 TTBRAttributes; TranslationTable = AllocateAlignedPages ( @@ -353,28 +352,13 @@ ArmConfigureMmu ( InvalidateDataCacheRange (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); - // By default, mark the translation table as belonging to a uncached region - TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; while (MemoryTable->Length != 0) { - // Find the memory attribute for the Translation Table - if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) { - TranslationTableAttribute = MemoryTable->Attributes; - } - FillTranslationTable (TranslationTable, MemoryTable); MemoryTable++; } - // Translate the Memory Attributes into Translation Table Register Attributes - if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) { - TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC; - } else { - // Page tables must reside in memory mapped as write-back cacheable - ASSERT (0); - return RETURN_UNSUPPORTED; - } - + TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC + : TTBR_WRITE_BACK_ALLOC; if (TTBRAttributes & TTBR_SHAREABLE) { if (PreferNonshareableMemory ()) { TTBRAttributes ^= TTBR_SHAREABLE;