diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
index e22900d0cc..9f8f1bb8bb 100644
--- a/UefiCpuPkg/Include/Register/LocalApic.h
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -62,12 +62,13 @@
 
 typedef union {
   struct {
-    UINT64  Reserved0:8;   ///< Reserved.
-    UINT64  Bsp:1;         ///< Processor is BSP.
-    UINT64  Reserved1:1;   ///< Reserved.
-    UINT64  Extd:1;        ///< Enable x2APIC mode.
-    UINT64  En:1;          ///< xAPIC global enable/disable.
-    UINT64  ApicBase:52;   ///< APIC Base physical address. The actual field width depends on physical address width.
+    UINT32  Reserved0:8;     ///< Reserved.
+    UINT32  Bsp:1;           ///< Processor is BSP.
+    UINT32  Reserved1:1;     ///< Reserved.
+    UINT32  Extd:1;          ///< Enable x2APIC mode.
+    UINT32  En:1;            ///< xAPIC global enable/disable.
+    UINT32  ApicBaseLow:20;  ///< APIC Base physical address. The actual field width depends on physical address width.
+    UINT32  ApicBaseHigh:32;
   } Bits;
   UINT64    Uint64;
 } MSR_IA32_APIC_BASE;
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 1cba34cd59..9f08f5d188 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -151,7 +151,7 @@ SendIpi (
     // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an 
     // interrupt in x2APIC mode.
     //
-    MsrValue = (((UINT64)ApicId) << 32) | IcrLow;
+    MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
     AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
   }
 }