UefiCpuPkg: Remove X86 ASM and S files
NASM has replaced ASM and S files. 1. Remove ASM from all modules expect for the ones in ResetVector directory. The ones in ResetVector directory are included by Vtf0.nasmb. They are also nasm style. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Liming Gao
@@ -1,7 +1,7 @@
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## @file
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# CPU Exception Handler library instance for DXE modules.
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#
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# Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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@@ -28,7 +28,6 @@
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#
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[Sources.Ia32]
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Ia32/ExceptionHandlerAsm.asm
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Ia32/ExceptionHandlerAsm.nasm
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Ia32/ExceptionTssEntryAsm.nasm
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Ia32/ExceptionHandlerAsm.S
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@@ -36,7 +35,6 @@
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Ia32/ArchInterruptDefs.h
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[Sources.X64]
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X64/ExceptionHandlerAsm.asm
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X64/ExceptionHandlerAsm.nasm
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X64/ExceptionHandlerAsm.S
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X64/ArchExceptionHandler.c
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@@ -1,467 +0,0 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; ExceptionHandlerAsm.Asm
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;
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; Abstract:
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;
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; IA32 CPU Exception Handler
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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.686
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.model flat,C
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;
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; CommonExceptionHandler()
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;
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CommonExceptionHandler PROTO C
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.data
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EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
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EXTRN mDoFarReturnFlag:DWORD ; Do far return flag
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.code
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ALIGN 8
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;
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; exception handler stub table
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;
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AsmIdtVectorBegin:
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REPEAT 32
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db 6ah ; push #VectorNum
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db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
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push eax
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mov eax, CommonInterruptEntry
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jmp eax
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ENDM
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AsmIdtVectorEnd:
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HookAfterStubBegin:
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db 6ah ; push
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VectorNum:
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db 0 ; 0 will be fixed
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push eax
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mov eax, HookAfterStubHeaderEnd
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jmp eax
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HookAfterStubHeaderEnd:
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pop eax
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sub esp, 8 ; reserve room for filling exception data later
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push [esp + 8]
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xchg ecx, [esp] ; get vector number
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bt mErrorCodeFlag, ecx
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jnc @F
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push [esp] ; addition push if exception data needed
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@@:
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xchg ecx, [esp] ; restore ecx
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push eax
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;----------------------------------------------------------------------------;
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; CommonInterruptEntry ;
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;----------------------------------------------------------------------------;
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; The follow algorithm is used for the common interrupt routine.
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; Entry from each interrupt with a push eax and eax=interrupt number
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + Vector Number +
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; +---------------------+
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; + EBP +
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; +---------------------+ <-- EBP
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CommonInterruptEntry PROC PUBLIC
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cli
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pop eax
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;
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; All interrupt handlers are invoked through interrupt gates, so
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; IF flag automatically cleared at the entry point
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;
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;
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; Get vector number from top of stack
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;
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xchg ecx, [esp]
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and ecx, 0FFh ; Vector number should be less than 256
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cmp ecx, 32 ; Intel reserved vector for exceptions?
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jae NoErrorCode
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bt mErrorCodeFlag, ecx
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jc HasErrorCode
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NoErrorCode:
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;
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + ECX +
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; +---------------------+ <-- ESP
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;
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; Registers:
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; ECX - Vector Number
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;
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;
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; Put Vector Number on stack
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;
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push ecx
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;
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; Put 0 (dummy) error code on stack, and restore ECX
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;
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xor ecx, ecx ; ECX = 0
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xchg ecx, [esp+4]
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jmp ErrorCodeAndVectorOnStack
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HasErrorCode:
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;
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + ECX +
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; +---------------------+ <-- ESP
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;
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; Registers:
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; ECX - Vector Number
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;
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;
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; Put Vector Number on stack and restore ECX
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;
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xchg ecx, [esp]
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ErrorCodeAndVectorOnStack:
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push ebp
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mov ebp, esp
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;
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + Vector Number +
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; +---------------------+
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; + EBP +
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; +---------------------+ <-- EBP
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;
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;
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; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
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; is 16-byte aligned
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;
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and esp, 0fffffff0h
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sub esp, 12
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sub esp, 8
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push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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push eax
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push ecx
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push edx
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push ebx
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lea ecx, [ebp + 6 * 4]
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push ecx ; ESP
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push dword ptr [ebp] ; EBP
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push esi
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push edi
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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mov eax, ss
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push eax
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movzx eax, word ptr [ebp + 4 * 4]
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push eax
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mov eax, ds
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push eax
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mov eax, es
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push eax
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mov eax, fs
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push eax
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mov eax, gs
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push eax
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;; UINT32 Eip;
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mov eax, [ebp + 3 * 4]
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push eax
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;; UINT32 Gdtr[2], Idtr[2];
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sub esp, 8
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sidt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0FFFFh
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mov [esp+4], eax
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sub esp, 8
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sgdt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0FFFFh
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mov [esp+4], eax
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;; UINT32 Ldtr, Tr;
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xor eax, eax
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str ax
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push eax
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sldt ax
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push eax
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;; UINT32 EFlags;
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mov eax, [ebp + 5 * 4]
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push eax
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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mov eax, 1
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push ebx ; temporarily save value of ebx on stack
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cpuid ; use CPUID to determine if FXSAVE/FXRESTOR and DE
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; are supported
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pop ebx ; retore value of ebx that was overwritten by CPUID
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mov eax, cr4
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push eax ; push cr4 firstly
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
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jz @F
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or eax, BIT9 ; Set CR4.OSFXSR
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@@:
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test edx, BIT2 ; Test for Debugging Extensions support
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jz @F
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or eax, BIT3 ; Set CR4.DE
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@@:
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mov cr4, eax
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mov eax, cr3
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push eax
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mov eax, cr2
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push eax
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xor eax, eax
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push eax
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mov eax, cr0
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push eax
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov eax, dr7
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push eax
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mov eax, dr6
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push eax
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mov eax, dr3
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push eax
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mov eax, dr2
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push eax
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mov eax, dr1
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push eax
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mov eax, dr0
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push eax
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;; FX_SAVE_STATE_IA32 FxSaveState;
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sub esp, 512
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mov edi, esp
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
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; edx still contains result from CPUID above
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jz @F
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db 0fh, 0aeh, 07h ;fxsave [edi]
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@@:
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;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
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cld
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;; UINT32 ExceptionData;
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push dword ptr [ebp + 2 * 4]
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;; Prepare parameter and call
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mov edx, esp
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push edx
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mov edx, dword ptr [ebp + 1 * 4]
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push edx
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;
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; Call External Exception Handler
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;
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mov eax, CommonExceptionHandler
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call eax
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add esp, 8
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cli
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;; UINT32 ExceptionData;
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add esp, 4
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;; FX_SAVE_STATE_IA32 FxSaveState;
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mov esi, esp
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mov eax, 1
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cpuid ; use CPUID to determine if FXSAVE/FXRESTOR
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; are supported
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
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jz @F
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db 0fh, 0aeh, 0eh ; fxrstor [esi]
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@@:
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add esp, 512
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; Skip restoration of DRx registers to support in-circuit emualators
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;; or debuggers set breakpoint in interrupt/exception context
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add esp, 4 * 6
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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pop eax
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mov cr0, eax
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add esp, 4 ; not for Cr1
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pop eax
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mov cr2, eax
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pop eax
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mov cr3, eax
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pop eax
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mov cr4, eax
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;; UINT32 EFlags;
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pop dword ptr [ebp + 5 * 4]
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;; UINT32 Ldtr, Tr;
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;; UINT32 Gdtr[2], Idtr[2];
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;; Best not let anyone mess with these particular registers...
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add esp, 24
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;; UINT32 Eip;
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pop dword ptr [ebp + 3 * 4]
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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;; NOTE - modified segment registers could hang the debugger... We
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;; could attempt to insulate ourselves against this possibility,
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;; but that poses risks as well.
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;;
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pop gs
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pop fs
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pop es
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pop ds
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pop dword ptr [ebp + 4 * 4]
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pop ss
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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pop edi
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pop esi
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add esp, 4 ; not for ebp
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add esp, 4 ; not for esp
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pop ebx
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pop edx
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pop ecx
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pop eax
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pop dword ptr [ebp - 8]
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pop dword ptr [ebp - 4]
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mov esp, ebp
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pop ebp
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add esp, 8
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cmp dword ptr [esp - 16], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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jz DoReturn
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cmp dword ptr [esp - 20], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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jz ErrorCode
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jmp dword ptr [esp - 16]
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ErrorCode:
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sub esp, 4
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jmp dword ptr [esp - 12]
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DoReturn:
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cmp mDoFarReturnFlag, 0 ; Check if need to do far return instead of IRET
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jz DoIret
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push [esp + 8] ; save EFLAGS
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add esp, 16
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push [esp - 8] ; save CS in new location
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push [esp - 8] ; save EIP in new location
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push [esp - 8] ; save EFLAGS in new location
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popfd ; restore EFLAGS
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retf ; far return
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DoIret:
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iretd
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CommonInterruptEntry ENDP
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;---------------------------------------;
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; _AsmGetTemplateAddressMap ;
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;----------------------------------------------------------------------------;
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;
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; Protocol prototype
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; AsmGetTemplateAddressMap (
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; EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
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; );
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;
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; Routine Description:
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;
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; Return address map of interrupt handler template so that C code can generate
|
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; interrupt table.
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;
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; Arguments:
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;
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;
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; Returns:
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;
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; Nothing
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;
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;
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; Input: [ebp][0] = Original ebp
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; [ebp][4] = Return address
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;
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; Output: Nothing
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;
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; Destroys: Nothing
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;-----------------------------------------------------------------------------;
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AsmGetTemplateAddressMap proc near public
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push ebp ; C prolog
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mov ebp, esp
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pushad
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mov ebx, dword ptr [ebp + 08h]
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mov dword ptr [ebx], AsmIdtVectorBegin
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mov dword ptr [ebx + 4h], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
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mov dword ptr [ebx + 8h], HookAfterStubBegin
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popad
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pop ebp
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ret
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AsmGetTemplateAddressMap ENDP
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;-------------------------------------------------------------------------------------
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; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
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;-------------------------------------------------------------------------------------
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AsmVectorNumFixup proc near public
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mov eax, dword ptr [esp + 8]
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mov ecx, [esp + 4]
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mov [ecx + (VectorNum - HookAfterStubBegin)], al
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ret
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AsmVectorNumFixup ENDP
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END
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@@ -1,7 +1,7 @@
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## @file
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||||
# CPU Exception Handler library instance for PEI module.
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#
|
||||
# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
@@ -28,7 +28,6 @@
|
||||
#
|
||||
|
||||
[Sources.Ia32]
|
||||
Ia32/ExceptionHandlerAsm.asm
|
||||
Ia32/ExceptionHandlerAsm.nasm
|
||||
Ia32/ExceptionTssEntryAsm.nasm
|
||||
Ia32/ExceptionHandlerAsm.S
|
||||
@@ -36,7 +35,6 @@
|
||||
Ia32/ArchInterruptDefs.h
|
||||
|
||||
[Sources.X64]
|
||||
X64/ExceptionHandlerAsm.asm
|
||||
X64/ExceptionHandlerAsm.nasm
|
||||
X64/ExceptionHandlerAsm.S
|
||||
X64/ArchExceptionHandler.c
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
## @file
|
||||
# CPU Exception Handler library instance for SEC/PEI modules.
|
||||
#
|
||||
# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
@@ -28,7 +28,6 @@
|
||||
#
|
||||
|
||||
[Sources.Ia32]
|
||||
Ia32/ExceptionHandlerAsm.asm
|
||||
Ia32/ExceptionHandlerAsm.nasm
|
||||
Ia32/ExceptionTssEntryAsm.nasm
|
||||
Ia32/ExceptionHandlerAsm.S
|
||||
@@ -36,7 +35,6 @@
|
||||
Ia32/ArchInterruptDefs.h
|
||||
|
||||
[Sources.X64]
|
||||
X64/ExceptionHandlerAsm.asm
|
||||
X64/ExceptionHandlerAsm.nasm
|
||||
X64/ExceptionHandlerAsm.S
|
||||
X64/ArchExceptionHandler.c
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
## @file
|
||||
# CPU Exception Handler library instance for SMM modules.
|
||||
#
|
||||
# Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
@@ -28,7 +28,6 @@
|
||||
#
|
||||
|
||||
[Sources.Ia32]
|
||||
Ia32/ExceptionHandlerAsm.asm
|
||||
Ia32/ExceptionHandlerAsm.nasm
|
||||
Ia32/ExceptionTssEntryAsm.nasm
|
||||
Ia32/ExceptionHandlerAsm.S
|
||||
@@ -36,7 +35,6 @@
|
||||
Ia32/ArchInterruptDefs.h
|
||||
|
||||
[Sources.X64]
|
||||
X64/ExceptionHandlerAsm.asm
|
||||
X64/ExceptionHandlerAsm.nasm
|
||||
X64/ExceptionHandlerAsm.S
|
||||
X64/ArchExceptionHandler.c
|
||||
|
||||
@@ -1,389 +0,0 @@
|
||||
;------------------------------------------------------------------------------ ;
|
||||
; Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
; This program and the accompanying materials
|
||||
; are licensed and made available under the terms and conditions of the BSD License
|
||||
; which accompanies this distribution. The full text of the license may be found at
|
||||
; http://opensource.org/licenses/bsd-license.php.
|
||||
;
|
||||
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
;
|
||||
; Module Name:
|
||||
;
|
||||
; ExceptionHandlerAsm.Asm
|
||||
;
|
||||
; Abstract:
|
||||
;
|
||||
; x64 CPU Exception Handler
|
||||
;
|
||||
; Notes:
|
||||
;
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
;
|
||||
; CommonExceptionHandler()
|
||||
;
|
||||
externdef CommonExceptionHandler:near
|
||||
|
||||
EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
|
||||
EXTRN mDoFarReturnFlag:QWORD ; Do far return flag
|
||||
|
||||
data SEGMENT
|
||||
|
||||
.code
|
||||
|
||||
ALIGN 8
|
||||
|
||||
AsmIdtVectorBegin:
|
||||
REPEAT 32
|
||||
db 6ah ; push #VectorNum
|
||||
db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
|
||||
push rax
|
||||
mov rax, CommonInterruptEntry
|
||||
jmp rax
|
||||
ENDM
|
||||
AsmIdtVectorEnd:
|
||||
|
||||
HookAfterStubHeaderBegin:
|
||||
db 6ah ; push
|
||||
@VectorNum:
|
||||
db 0 ; 0 will be fixed
|
||||
push rax
|
||||
mov rax, HookAfterStubHeaderEnd
|
||||
jmp rax
|
||||
HookAfterStubHeaderEnd:
|
||||
mov rax, rsp
|
||||
and sp, 0fff0h ; make sure 16-byte aligned for exception context
|
||||
sub rsp, 18h ; reserve room for filling exception data later
|
||||
push rcx
|
||||
mov rcx, [rax + 8]
|
||||
bt mErrorCodeFlag, ecx
|
||||
jnc @F
|
||||
push [rsp] ; push additional rcx to make stack alignment
|
||||
@@:
|
||||
xchg rcx, [rsp] ; restore rcx, save Exception Number in stack
|
||||
push [rax] ; push rax into stack to keep code consistence
|
||||
|
||||
;---------------------------------------;
|
||||
; CommonInterruptEntry ;
|
||||
;---------------------------------------;
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
; Entry from each interrupt with a push eax and eax=interrupt number
|
||||
; Stack frame would be as follows as specified in IA32 manuals:
|
||||
;
|
||||
; +---------------------+ <-- 16-byte aligned ensured by processor
|
||||
; + Old SS +
|
||||
; +---------------------+
|
||||
; + Old RSP +
|
||||
; +---------------------+
|
||||
; + RFlags +
|
||||
; +---------------------+
|
||||
; + CS +
|
||||
; +---------------------+
|
||||
; + RIP +
|
||||
; +---------------------+
|
||||
; + Error Code +
|
||||
; +---------------------+
|
||||
; + Vector Number +
|
||||
; +---------------------+
|
||||
; + RBP +
|
||||
; +---------------------+ <-- RBP, 16-byte aligned
|
||||
; The follow algorithm is used for the common interrupt routine.
|
||||
CommonInterruptEntry PROC PUBLIC
|
||||
cli
|
||||
pop rax
|
||||
;
|
||||
; All interrupt handlers are invoked through interrupt gates, so
|
||||
; IF flag automatically cleared at the entry point
|
||||
;
|
||||
xchg rcx, [rsp] ; Save rcx into stack and save vector number into rcx
|
||||
and rcx, 0FFh
|
||||
cmp ecx, 32 ; Intel reserved vector for exceptions?
|
||||
jae NoErrorCode
|
||||
bt mErrorCodeFlag, ecx
|
||||
jc @F
|
||||
|
||||
NoErrorCode:
|
||||
|
||||
;
|
||||
; Push a dummy error code on the stack
|
||||
; to maintain coherent stack map
|
||||
;
|
||||
push [rsp]
|
||||
mov qword ptr [rsp + 8], 0
|
||||
@@:
|
||||
push rbp
|
||||
mov rbp, rsp
|
||||
push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
|
||||
push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
|
||||
|
||||
;
|
||||
; Stack:
|
||||
; +---------------------+ <-- 16-byte aligned ensured by processor
|
||||
; + Old SS +
|
||||
; +---------------------+
|
||||
; + Old RSP +
|
||||
; +---------------------+
|
||||
; + RFlags +
|
||||
; +---------------------+
|
||||
; + CS +
|
||||
; +---------------------+
|
||||
; + RIP +
|
||||
; +---------------------+
|
||||
; + Error Code +
|
||||
; +---------------------+
|
||||
; + RCX / Vector Number +
|
||||
; +---------------------+
|
||||
; + RBP +
|
||||
; +---------------------+ <-- RBP, 16-byte aligned
|
||||
;
|
||||
|
||||
|
||||
;
|
||||
; Since here the stack pointer is 16-byte aligned, so
|
||||
; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
|
||||
; is 16-byte aligned
|
||||
;
|
||||
|
||||
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
push r15
|
||||
push r14
|
||||
push r13
|
||||
push r12
|
||||
push r11
|
||||
push r10
|
||||
push r9
|
||||
push r8
|
||||
push rax
|
||||
push qword ptr [rbp + 8] ; RCX
|
||||
push rdx
|
||||
push rbx
|
||||
push qword ptr [rbp + 48] ; RSP
|
||||
push qword ptr [rbp] ; RBP
|
||||
push rsi
|
||||
push rdi
|
||||
|
||||
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
|
||||
movzx rax, word ptr [rbp + 56]
|
||||
push rax ; for ss
|
||||
movzx rax, word ptr [rbp + 32]
|
||||
push rax ; for cs
|
||||
mov rax, ds
|
||||
push rax
|
||||
mov rax, es
|
||||
push rax
|
||||
mov rax, fs
|
||||
push rax
|
||||
mov rax, gs
|
||||
push rax
|
||||
|
||||
mov [rbp + 8], rcx ; save vector number
|
||||
|
||||
;; UINT64 Rip;
|
||||
push qword ptr [rbp + 24]
|
||||
|
||||
;; UINT64 Gdtr[2], Idtr[2];
|
||||
xor rax, rax
|
||||
push rax
|
||||
push rax
|
||||
sidt [rsp]
|
||||
xchg rax, [rsp + 2]
|
||||
xchg rax, [rsp]
|
||||
xchg rax, [rsp + 8]
|
||||
|
||||
xor rax, rax
|
||||
push rax
|
||||
push rax
|
||||
sgdt [rsp]
|
||||
xchg rax, [rsp + 2]
|
||||
xchg rax, [rsp]
|
||||
xchg rax, [rsp + 8]
|
||||
|
||||
;; UINT64 Ldtr, Tr;
|
||||
xor rax, rax
|
||||
str ax
|
||||
push rax
|
||||
sldt ax
|
||||
push rax
|
||||
|
||||
;; UINT64 RFlags;
|
||||
push qword ptr [rbp + 40]
|
||||
|
||||
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
mov rax, cr8
|
||||
push rax
|
||||
mov rax, cr4
|
||||
or rax, 208h
|
||||
mov cr4, rax
|
||||
push rax
|
||||
mov rax, cr3
|
||||
push rax
|
||||
mov rax, cr2
|
||||
push rax
|
||||
xor rax, rax
|
||||
push rax
|
||||
mov rax, cr0
|
||||
push rax
|
||||
|
||||
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
mov rax, dr7
|
||||
push rax
|
||||
mov rax, dr6
|
||||
push rax
|
||||
mov rax, dr3
|
||||
push rax
|
||||
mov rax, dr2
|
||||
push rax
|
||||
mov rax, dr1
|
||||
push rax
|
||||
mov rax, dr0
|
||||
push rax
|
||||
|
||||
;; FX_SAVE_STATE_X64 FxSaveState;
|
||||
sub rsp, 512
|
||||
mov rdi, rsp
|
||||
db 0fh, 0aeh, 07h ;fxsave [rdi]
|
||||
|
||||
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
|
||||
cld
|
||||
|
||||
;; UINT32 ExceptionData;
|
||||
push qword ptr [rbp + 16]
|
||||
|
||||
;; Prepare parameter and call
|
||||
mov rcx, [rbp + 8]
|
||||
mov rdx, rsp
|
||||
;
|
||||
; Per X64 calling convention, allocate maximum parameter stack space
|
||||
; and make sure RSP is 16-byte aligned
|
||||
;
|
||||
sub rsp, 4 * 8 + 8
|
||||
mov rax, CommonExceptionHandler
|
||||
call rax
|
||||
add rsp, 4 * 8 + 8
|
||||
|
||||
cli
|
||||
;; UINT64 ExceptionData;
|
||||
add rsp, 8
|
||||
|
||||
;; FX_SAVE_STATE_X64 FxSaveState;
|
||||
|
||||
mov rsi, rsp
|
||||
db 0fh, 0aeh, 0Eh ; fxrstor [rsi]
|
||||
add rsp, 512
|
||||
|
||||
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
;; Skip restoration of DRx registers to support in-circuit emualators
|
||||
;; or debuggers set breakpoint in interrupt/exception context
|
||||
add rsp, 8 * 6
|
||||
|
||||
;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
|
||||
pop rax
|
||||
mov cr0, rax
|
||||
add rsp, 8 ; not for Cr1
|
||||
pop rax
|
||||
mov cr2, rax
|
||||
pop rax
|
||||
mov cr3, rax
|
||||
pop rax
|
||||
mov cr4, rax
|
||||
pop rax
|
||||
mov cr8, rax
|
||||
|
||||
;; UINT64 RFlags;
|
||||
pop qword ptr [rbp + 40]
|
||||
|
||||
;; UINT64 Ldtr, Tr;
|
||||
;; UINT64 Gdtr[2], Idtr[2];
|
||||
;; Best not let anyone mess with these particular registers...
|
||||
add rsp, 48
|
||||
|
||||
;; UINT64 Rip;
|
||||
pop qword ptr [rbp + 24]
|
||||
|
||||
;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
pop rax
|
||||
; mov gs, rax ; not for gs
|
||||
pop rax
|
||||
; mov fs, rax ; not for fs
|
||||
; (X64 will not use fs and gs, so we do not restore it)
|
||||
pop rax
|
||||
mov es, rax
|
||||
pop rax
|
||||
mov ds, rax
|
||||
pop qword ptr [rbp + 32] ; for cs
|
||||
pop qword ptr [rbp + 56] ; for ss
|
||||
|
||||
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
||||
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
||||
pop rdi
|
||||
pop rsi
|
||||
add rsp, 8 ; not for rbp
|
||||
pop qword ptr [rbp + 48] ; for rsp
|
||||
pop rbx
|
||||
pop rdx
|
||||
pop rcx
|
||||
pop rax
|
||||
pop r8
|
||||
pop r9
|
||||
pop r10
|
||||
pop r11
|
||||
pop r12
|
||||
pop r13
|
||||
pop r14
|
||||
pop r15
|
||||
|
||||
mov rsp, rbp
|
||||
pop rbp
|
||||
add rsp, 16
|
||||
cmp qword ptr [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
|
||||
jz DoReturn
|
||||
cmp qword ptr [rsp - 40], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
|
||||
jz ErrorCode
|
||||
jmp qword ptr [rsp - 32]
|
||||
ErrorCode:
|
||||
sub rsp, 8
|
||||
jmp qword ptr [rsp - 24]
|
||||
|
||||
DoReturn:
|
||||
cmp mDoFarReturnFlag, 0 ; Check if need to do far return instead of IRET
|
||||
jz DoIret
|
||||
push rax
|
||||
mov rax, rsp ; save old RSP to rax
|
||||
mov rsp, [rsp + 20h]
|
||||
push [rax + 10h] ; save CS in new location
|
||||
push [rax + 8h] ; save EIP in new location
|
||||
push [rax + 18h] ; save EFLAGS in new location
|
||||
mov rax, [rax] ; restore rax
|
||||
popfq ; restore EFLAGS
|
||||
DB 48h ; prefix to composite "retq" with next "retf"
|
||||
retf ; far return
|
||||
DoIret:
|
||||
iretq
|
||||
|
||||
CommonInterruptEntry ENDP
|
||||
|
||||
;-------------------------------------------------------------------------------------
|
||||
; GetTemplateAddressMap (&AddressMap);
|
||||
;-------------------------------------------------------------------------------------
|
||||
; comments here for definition of address map
|
||||
AsmGetTemplateAddressMap PROC
|
||||
mov rax, offset AsmIdtVectorBegin
|
||||
mov qword ptr [rcx], rax
|
||||
mov qword ptr [rcx + 8h], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
|
||||
mov rax, offset HookAfterStubHeaderBegin
|
||||
mov qword ptr [rcx + 10h], rax
|
||||
ret
|
||||
AsmGetTemplateAddressMap ENDP
|
||||
|
||||
;-------------------------------------------------------------------------------------
|
||||
; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
|
||||
;-------------------------------------------------------------------------------------
|
||||
AsmVectorNumFixup PROC
|
||||
mov rax, rdx
|
||||
mov [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al
|
||||
ret
|
||||
AsmVectorNumFixup ENDP
|
||||
|
||||
END
|
||||
Reference in New Issue
Block a user