UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. The mask is applied when page tables entriees are created or modified. CC: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
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@@ -119,7 +119,7 @@ GetPageTableEntry (
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return NULL;
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}
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L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDRESS_MASK_64);
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L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
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} else {
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L3PageTable = (UINT64 *)GetPageTableBase ();
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}
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@@ -133,7 +133,7 @@ GetPageTableEntry (
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return &L3PageTable[Index3];
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}
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L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRESS_MASK_64);
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L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
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if (L2PageTable[Index2] == 0) {
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*PageAttribute = PageNone;
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return NULL;
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@@ -145,7 +145,7 @@ GetPageTableEntry (
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}
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// 4k
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L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRESS_MASK_64);
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L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
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if ((L1PageTable[Index1] == 0) && (Address != 0)) {
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*PageAttribute = PageNone;
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return NULL;
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@@ -304,9 +304,9 @@ SplitPage (
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}
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BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64;
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for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
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NewPageEntry[Index] = BaseAddress + SIZE_4KB * Index + ((*PageEntry) & PAGE_PROGATE_BITS);
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NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
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}
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(*PageEntry) = (UINT64)(UINTN)NewPageEntry + PAGE_ATTRIBUTE_BITS;
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(*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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return RETURN_SUCCESS;
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} else {
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return RETURN_UNSUPPORTED;
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@@ -325,9 +325,9 @@ SplitPage (
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}
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BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64;
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for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
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NewPageEntry[Index] = BaseAddress + SIZE_2MB * Index + IA32_PG_PS + ((*PageEntry) & PAGE_PROGATE_BITS);
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NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
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}
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(*PageEntry) = (UINT64)(UINTN)NewPageEntry + PAGE_ATTRIBUTE_BITS;
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(*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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return RETURN_SUCCESS;
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} else {
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return RETURN_UNSUPPORTED;
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