ArmPkg: Added Aarch64 support
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
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ArmPkg/Library/CompilerIntrinsicsLib/AArch64/memcpy.S
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125
ArmPkg/Library/CompilerIntrinsicsLib/AArch64/memcpy.S
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/*
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* Copyright (c) 2011 - 2013, ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.text
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.align 2
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ASM_GLOBAL ASM_PFX(memcpy)
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// Taken from Newlib BSD implementation.
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ASM_PFX(memcpy):
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// Copy dst to x6, so we can preserve return value.
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mov x6, x0
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// NOTE: although size_t is unsigned, this code uses signed
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// comparisons on x2 so relies on nb never having its top bit
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// set. In practice this is not going to be a real problem.
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// Require at least 64 bytes to be worth aligning.
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cmp x2, #64
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blt qwordcopy
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// Compute offset to align destination to 16 bytes.
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neg x3, x0
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and x3, x3, 15
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cbz x3, blockcopy // offset == 0 is likely
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// We know there is at least 64 bytes to be done, so we
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// do a 16 byte misaligned copy at first and then later do
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// all 16-byte aligned copies. Some bytes will be copied
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// twice, but there's no harm in that since memcpy does not
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// guarantee correctness on overlap.
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sub x2, x2, x3 // nb -= offset
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ldp x4, x5, [x1]
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add x1, x1, x3
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stp x4, x5, [x6]
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add x6, x6, x3
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// The destination pointer is now qword (16 byte) aligned.
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// (The src pointer might be.)
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blockcopy:
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// Copy 64 bytes at a time.
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subs x2, x2, #64
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blt 3f
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2: subs x2, x2, #64
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ldp x4, x5, [x1,#0]
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ldp x8, x9, [x1,#16]
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ldp x10,x11,[x1,#32]
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ldp x12,x13,[x1,#48]
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add x1, x1, #64
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stp x4, x5, [x6,#0]
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stp x8, x9, [x6,#16]
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stp x10,x11,[x6,#32]
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stp x12,x13,[x6,#48]
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add x6, x6, #64
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bge 2b
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// Unwind pre-decrement
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3: add x2, x2, #64
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qwordcopy:
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// Copy 0-48 bytes, 16 bytes at a time.
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subs x2, x2, #16
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blt tailcopy
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2: ldp x4, x5, [x1],#16
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subs x2, x2, #16
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stp x4, x5, [x6],#16
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bge 2b
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// No need to unwind the pre-decrement, it would not change
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// the low 4 bits of the count. But how likely is it for the
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// byte count to be multiple of 16? Is it worth the overhead
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// of testing for x2 == -16?
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tailcopy:
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// Copy trailing 0-15 bytes.
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tbz x2, #3, 1f
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ldr x4, [x1],#8 // copy 8 bytes
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str x4, [x6],#8
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1:
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tbz x2, #2, 1f
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ldr w4, [x1],#4 // copy 4 bytes
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str w4, [x6],#4
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1:
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tbz x2, #1, 1f
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ldrh w4, [x1],#2 // copy 2 bytes
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strh w4, [x6],#2
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1:
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tbz x2, #0, return
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ldrb w4, [x1] // copy 1 byte
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strb w4, [x6]
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return:
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// This is the only return point of memcpy.
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ret
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