ArmPkg: Moved ARMv7 specific files to a 'Arm' subdirectory
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14180 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
184
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
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184
ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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INCLUDE AsmMacroIoLib.inc
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#ifdef ARM_CPU_ARMv6
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// No memory barriers for ARMv6
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#define isb
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#define dsb
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#endif
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EXPORT Cp15IdCode
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EXPORT Cp15CacheInfo
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EXPORT ArmGetInterruptState
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EXPORT ArmGetFiqState
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EXPORT ArmGetTTBR0BaseAddress
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EXPORT ArmSetTTBR0
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EXPORT ArmSetDomainAccessControl
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EXPORT CPSRMaskInsert
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EXPORT CPSRRead
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EXPORT ArmReadCpacr
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EXPORT ArmWriteCpacr
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EXPORT ArmWriteAuxCr
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EXPORT ArmReadAuxCr
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EXPORT ArmInvalidateTlb
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EXPORT ArmUpdateTranslationTableEntry
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EXPORT ArmReadNsacr
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EXPORT ArmWriteNsacr
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EXPORT ArmReadScr
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EXPORT ArmWriteScr
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EXPORT ArmReadMVBar
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EXPORT ArmWriteMVBar
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EXPORT ArmCallWFE
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EXPORT ArmCallSEV
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EXPORT ArmReadSctlr
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AREA ArmLibSupport, CODE, READONLY
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Cp15IdCode
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mrc p15,0,R0,c0,c0,0
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bx LR
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Cp15CacheInfo
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mrc p15,0,R0,c0,c0,1
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bx LR
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ArmGetInterruptState
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mrs R0,CPSR
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tst R0,#0x80 // Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmGetFiqState
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mrs R0,CPSR
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tst R0,#0x40 // Check if FIQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmSetDomainAccessControl
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mcr p15,0,r0,c3,c0,0
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bx lr
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CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert
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stmfd sp!, {r4-r12, lr} // save all the banked registers
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mov r3, sp // copy the stack pointer into a non-banked register
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mrs r2, cpsr // read the cpsr
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bic r2, r2, r0 // clear mask in the cpsr
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and r1, r1, r0 // clear bits outside the mask in the input
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orr r2, r2, r1 // set field
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msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)
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isb
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mov sp, r3 // restore stack pointer
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ldmfd sp!, {r4-r12, lr} // restore registers
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bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
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CPSRRead
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mrs r0, cpsr
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bx lr
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ArmReadCpacr
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mrc p15, 0, r0, c1, c0, 2
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bx lr
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ArmWriteCpacr
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mcr p15, 0, r0, c1, c0, 2
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isb
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bx lr
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ArmWriteAuxCr
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mcr p15, 0, r0, c1, c0, 1
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bx lr
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ArmReadAuxCr
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mrc p15, 0, r0, c1, c0, 1
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bx lr
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ArmSetTTBR0
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mcr p15,0,r0,c2,c0,0
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isb
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bx lr
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ArmGetTTBR0BaseAddress
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mrc p15,0,r0,c2,c0,0
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LoadConstantToReg(0xFFFFC000, r1)
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and r0, r0, r1
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isb
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bx lr
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//
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//VOID
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//ArmUpdateTranslationTableEntry (
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// IN VOID *TranslationTableEntry // R0
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// IN VOID *MVA // R1
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// );
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ArmUpdateTranslationTableEntry
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mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
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dsb
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mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
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mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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ArmInvalidateTlb
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
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dsb
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isb
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bx lr
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ArmReadNsacr
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mrc p15, 0, r0, c1, c1, 2
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bx lr
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ArmWriteNsacr
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mcr p15, 0, r0, c1, c1, 2
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bx lr
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ArmReadScr
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mrc p15, 0, r0, c1, c1, 0
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bx lr
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ArmWriteScr
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mcr p15, 0, r0, c1, c1, 0
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bx lr
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ArmReadMVBar
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mrc p15, 0, r0, c12, c0, 1
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bx lr
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ArmWriteMVBar
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mcr p15, 0, r0, c12, c0, 1
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bx lr
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ArmCallWFE
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wfe
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blx lr
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ArmCallSEV
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sev
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blx lr
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ArmReadSctlr
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mrc p15, 0, R0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)
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bx lr
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END
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