ArmPlatformPkg: Rename gEmbeddedTokenSpaceGuid.PcdEmbeddedFd* into gArmTokenSpaceGuid.PcdNormalFd*
This renaming is for matching the namespace with the secure firmware gArmTokenSpaceGuid.PcdSecureFdBaseAddress/Size. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11475 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -195,7 +195,7 @@ CEntryPoint (
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// If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
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if (FeaturePcdGet(PcdStandalone) == FALSE) {
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if (CoreId == 0) {
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UINTN* StartAddress = (UINTN*)PcdGet32(PcdEmbeddedFdBaseAddress);
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UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFdBaseAddress);
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// Patch the DRAM to make an infinite loop at the start address
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*StartAddress = 0xEAFFFFFE; // opcode for while(1)
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@@ -204,7 +204,7 @@ CEntryPoint (
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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// To enter into Non Secure state, we need to make a return from exception
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return_from_exception(PcdGet32(PcdEmbeddedFdBaseAddress));
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return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
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} else {
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// When the primary core is stopped by the hardware debugger to copy the firmware
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// into DRAM. The secondary cores are still running. As soon as the first bytes of
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@@ -218,7 +218,7 @@ CEntryPoint (
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}
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} else {
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// To enter into Non Secure state, we need to make a return from exception
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return_from_exception(PcdGet32(PcdEmbeddedFdBaseAddress));
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return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
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}
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//-------------------- Non Secure Mode ---------------------
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@@ -232,7 +232,7 @@ VOID NonSecureWaitForFirmware() {
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VOID (*secondary_start)(VOID);
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// The secondary cores will execute the fimrware once wake from WFI.
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secondary_start = (VOID (*)())PcdGet32(PcdEmbeddedFdBaseAddress);
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secondary_start = (VOID (*)())PcdGet32(PcdNormalFdBaseAddress);
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ArmCallWFI();
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