MdeModulePkg/Xhci: make all timeout values be consistent with comments.

In the original code, there exists some mismatches between the real
waiting time and the corresponding timeout comments. For example, the
XHC_GENERIC_TIMEOUT comment says it's 10ms timeout value, but the real
code in fact waits 10s.

So the code is refined to be consistent in code logic and comments.

Note XHC_POLL_DELAY macro also be removed and the polling interval in
XhcWaitOpRegBit() is changed from 1ms to 1us to keep same code style
with other code. It has no real functionality impact.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18235 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Feng Tian
2015-08-19 03:41:38 +00:00
committed by erictian
parent 1d7258fa53
commit 26cd2d6d2d
6 changed files with 29 additions and 35 deletions

View File

@@ -1,7 +1,7 @@
/** @file
Private Header file for Usb Host Controller PEIM
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
@@ -48,21 +48,20 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
//
// XHC reset timeout experience values.
// The unit is microsecond, setting it as 1s.
// The unit is millisecond, setting it as 1s.
//
#define XHC_RESET_TIMEOUT (1 * XHC_1_SECOND)
//
// XHC delay experience value for polling operation.
// The unit is microsecond, set it as 1ms.
//
#define XHC_POLL_DELAY (1 * XHC_1_MILLISECOND)
#define XHC_RESET_TIMEOUT (1000)
//
// Wait for root port state stable.
//
#define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
#define XHC_GENERIC_TIMEOUT (10 * XHC_1_MILLISECOND)
//
// XHC generic timeout experience values.
// The unit is millisecond, setting it as 10s.
//
#define XHC_GENERIC_TIMEOUT (10 * 1000)
#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))