Add ASSERT check for AsmFlushCacheRange().
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8465 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -1,7 +1,7 @@
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/** @file
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Declaration of internal functions in BaseLib.
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Copyright (c) 2006 - 2008, Intel Corporation<BR>
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Copyright (c) 2006 - 2009, Intel Corporation<BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -1616,6 +1616,38 @@ AsmSwitchStackAndBackingStore (
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IN VOID *NewStack,
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IN VOID *NewBsp
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);
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/**
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Internal worker function to invalidate a range of instruction cache lines
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in the cache coherency domain of the calling CPU.
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Internal worker function to invalidate the instruction cache lines specified
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by Address and Length. If Address is not aligned on a cache line boundary,
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then entire instruction cache line containing Address is invalidated. If
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Address + Length is not aligned on a cache line boundary, then the entire
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instruction cache line containing Address + Length -1 is invalidated. This
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function may choose to invalidate the entire instruction cache if that is more
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efficient than invalidating the specified range. If Length is 0, the no instruction
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cache lines are invalidated. Address is returned.
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This function is only available on IPF.
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@param Address The base address of the instruction cache lines to
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invalidate. If the CPU is in a physical addressing mode, then
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Address is a physical address. If the CPU is in a virtual
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addressing mode, then Address is a virtual address.
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@param Length The number of bytes to invalidate from the instruction cache.
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@return Address
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**/
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VOID *
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EFIAPI
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InternalFlushCacheRange (
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IN VOID *Address,
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IN UINTN Length
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);
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#else
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#endif
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