Add ASSERT check for AsmFlushCacheRange().

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8465 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
xli24
2009-06-04 14:29:12 +00:00
parent 63fffe4e72
commit 287f4f47b4
5 changed files with 103 additions and 27 deletions

View File

@@ -1,7 +1,7 @@
/** @file
Declaration of internal functions in BaseLib.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Copyright (c) 2006 - 2009, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1616,6 +1616,38 @@ AsmSwitchStackAndBackingStore (
IN VOID *NewStack,
IN VOID *NewBsp
);
/**
Internal worker function to invalidate a range of instruction cache lines
in the cache coherency domain of the calling CPU.
Internal worker function to invalidate the instruction cache lines specified
by Address and Length. If Address is not aligned on a cache line boundary,
then entire instruction cache line containing Address is invalidated. If
Address + Length is not aligned on a cache line boundary, then the entire
instruction cache line containing Address + Length -1 is invalidated. This
function may choose to invalidate the entire instruction cache if that is more
efficient than invalidating the specified range. If Length is 0, the no instruction
cache lines are invalidated. Address is returned.
This function is only available on IPF.
@param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address
**/
VOID *
EFIAPI
InternalFlushCacheRange (
IN VOID *Address,
IN UINTN Length
);
#else
#endif