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ArmPlatformPkg/ArmVExpress-CTA15-A7: Added support for CoreTile Express A15x2_A7x3

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This is the big.LITTLE test chip for ARM Versatile Express Motherboard.

Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13775 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2012-09-28 11:09:36 +00:00
parent 17839a45b8
commit 295c2eb804
11 changed files with 1539 additions and 0 deletions
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56
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf Normal file
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#/* @file
#
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CTA15A7ArmVExpressLib
FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmPlatformLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
IoLib
ArmLib
MemoryAllocationLib
SerialPortLib
[Sources.common]
CTA15-A7.c
CTA15-A7Mem.c
CTA15-A7Helper.asm | RVCT
CTA15-A7Helper.S | GCC
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
gArmPlatformTokenSpaceGuid.PcdStandalone
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdCoreCount
gArmTokenSpaceGuid.PcdTrustzoneSupport
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

193
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c Normal file
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/** @file
*
* Copyright (c) 2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Library/IoLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <ArmPlatform.h>
ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {
{
// Cluster 0, Core 0
0x0, 0x0,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
(UINT64)0
},
{
// Cluster 0, Core 1
0x0, 0x1,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
(UINT64)0
},
#ifndef ARM_BIGLITTLE_TC2
{
// Cluster 0, Core 2
0x0, 0x2,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
(UINT64)0
},
{
// Cluster 0, Core 3
0x0, 0x3,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
(UINT64)0
},
#endif
{
// Cluster 1, Core 0
0x1, 0x0,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
(UINT64)0
},
{
// Cluster 1, Core 1
0x1, 0x1,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
(UINT64)0
},
{
// Cluster 1, Core 2
0x1, 0x2,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
(UINT64)0
}
#ifndef ARM_BIGLITTLE_TC2
,{
// Cluster 1, Core 3
0x1, 0x3,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
(UINT64)0
}
#endif
};
/**
Return the current Boot Mode
This function returns the boot reason on the platform
@return Return the current Boot Mode of the platform
**/
EFI_BOOT_MODE
ArmPlatformGetBootMode (
VOID
)
{
return BOOT_WITH_FULL_CONFIGURATION;
}
/**
Initialize controllers that must setup in the normal world
This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
in the PEI phase.
**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
)
{
if (!IS_PRIMARY_CORE(MpId)) {
return RETURN_SUCCESS;
}
// Nothing to do here
return RETURN_SUCCESS;
}
/**
Initialize the system (or sometimes called permanent) memory
This memory is generally represented by the DRAM.
**/
VOID
ArmPlatformInitializeSystemMemory (
VOID
)
{
}
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
)
{
// Only support one cluster
*CoreCount = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);
*ArmCoreTable = mVersatileExpressCTA15A7InfoTable;
return EFI_SUCCESS;
}
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&mArmMpCoreInfoPpiGuid,
&mMpCoreInfoPpi
}
};
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
*PpiListSize = sizeof(gPlatformPpiTable);
*PpiList = gPlatformPpiTable;
}

30
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S Normal file
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//
// Copyright (c) 2012, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//
#include <Library/ArmLib.h>
.text
.align 3
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
//UINTN
//ArmPlatformGetCorePosition (
// IN UINTN MpId
// );
ASM_PFX(ArmPlatformGetCorePosition):
and r1, r0, #ARM_CORE_MASK
and r0, r0, #ARM_CLUSTER_MASK
add r0, r1, r0, LSR #7
bx lr

34
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.asm Normal file
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//
// Copyright (c) 2012, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//
#include <Library/ArmLib.h>
INCLUDE AsmMacroIoLib.inc
EXPORT ArmPlatformGetCorePosition
PRESERVE8
AREA CTA15A7Helper, CODE, READONLY
//UINTN
//ArmPlatformGetCorePosition (
// IN UINTN MpId
// );
ArmPlatformGetCorePosition FUNCTION
and r1, r0, #ARM_CORE_MASK
and r0, r0, #ARM_CLUSTER_MASK
add r0, r1, r0, LSR #7
bx lr
ENDFUNC
END

194
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c Normal file
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/** @file
*
* Copyright (c) 2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <ArmPlatform.h>
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
/**
Return the Virtual Memory Map of your platform
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. This array must be ended by a zero-filled
entry
**/
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
UINTN Index = 0;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
ASSERT (VirtualMemoryMap != NULL);
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
if (VirtualMemoryTable == NULL) {
return;
}
if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
CacheAttributes = DDR_ATTRIBUTES_CACHED;
} else {
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
}
// Detect if it is a 1GB or 2GB Test Chip
// [16:19]: 0=1GB TC2, 1=2GB TC2
if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED,
PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
0x40000000
);
}
#ifdef ARM_BIGLITTLE_TC2
// Secure NOR0 Flash
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Secure RAM
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
#endif
// SMB CS0 - NOR0 Flash
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Environment Variables region
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// SMB CS1 or CS4 - NOR1 Flash
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE;
VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Environment Variables region
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// SMB CS3 or CS1 - PSRAM
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// Motherboard peripherals
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
#ifdef ARM_BIGLITTLE_TC2
// Non-secure ROM
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
#endif
// OnChip peripherals
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// SCC Region
VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE;
VirtualMemoryTable[Index].Length = SIZE_64KB;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
#ifdef ARM_BIGLITTLE_TC2
// TC2 OnChip non-secure SRAM
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
#endif
#ifndef ARM_BIGLITTLE_TC2
// Workaround for SRAM bug in RTSM
if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {
VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;
VirtualMemoryTable[Index].VirtualBase = 0x80000000;
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
#endif
// DDR
VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
VirtualMemoryTable[Index].Length = 0;
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
*VirtualMemoryMap = VirtualMemoryTable;
}
/**
Return the EFI Memory Map provided by extension memory on your platform
This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
Descriptor HOBs used by DXE core.
@param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
EFI Memory region. This array must be ended by a zero-filled entry
**/
EFI_STATUS
ArmPlatformGetAdditionalSystemMemory (
OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
)
{
return EFI_UNSUPPORTED;
}

289
ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c Normal file
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/**
Copyright (c) 2012, ARM Ltd. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/ArmPlatformSysConfigLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/LcdPlatformLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/Cpu.h>
#include <Protocol/EdidDiscovered.h>
#include <Protocol/EdidActive.h>
#include <ArmPlatform.h>
typedef struct {
UINT32 Mode;
UINT32 HorizontalResolution;
UINT32 VerticalResolution;
LCD_BPP Bpp;
UINT32 OscFreq;
// These are used by HDLCD
UINT32 HSync;
UINT32 HBackPorch;
UINT32 HFrontPorch;
UINT32 VSync;
UINT32 VBackPorch;
UINT32 VFrontPorch;
} LCD_RESOLUTION;
LCD_RESOLUTION mResolutions[] = {
{ // Mode 0 : VGA : 640 x 480 x 24 bpp
VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,
VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
},
{ // Mode 1 : SVGA : 800 x 600 x 24 bpp
SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,
SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
},
{ // Mode 2 : XGA : 1024 x 768 x 24 bpp
XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,
XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
},
{ // Mode 3 : SXGA : 1280 x 1024 x 24 bpp
SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),
SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,
SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH
},
{ // Mode 4 : UXGA : 1600 x 1200 x 24 bpp
UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),
UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,
UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH
},
{ // Mode 5 : HD : 1920 x 1080 x 24 bpp
HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),
HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,
HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH
}
};
EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {
0,
NULL
};
EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {
0,
NULL
};
EFI_STATUS
LcdPlatformInitializeDisplay (
IN EFI_HANDLE Handle
)
{
EFI_STATUS Status;
// Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard
Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);
if (EFI_ERROR(Status)) {
return Status;
}
// Install the EDID Protocols
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,
&gEfiEdidActiveProtocolGuid, &mEdidActive,
NULL
);
return Status;
}
EFI_STATUS
LcdPlatformGetVram (
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
OUT UINTN* VramSize
)
{
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_ALLOCATE_TYPE AllocationType;
// Set the vram size
*VramSize = LCD_VRAM_SIZE;
*VramBaseAddress = (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE;
// Allocate the VRAM from the DRAM so that nobody else uses it.
if (*VramBaseAddress == 0) {
AllocationType = AllocateAnyPages;
} else {
AllocationType = AllocateAddress;
}
Status = gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);
if (EFI_ERROR(Status)) {
return Status;
}
// Ensure the Cpu architectural protocol is already installed
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
// Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable.
Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);
ASSERT_EFI_ERROR(Status);
if (EFI_ERROR(Status)) {
gBS->FreePool (VramBaseAddress);
return Status;
}
return EFI_SUCCESS;
}
UINT32
LcdPlatformGetMaxMode (
VOID
)
{
//
// The following line will report correctly the total number of graphics modes
// that could be supported by the graphics driver:
//
return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION));
}
EFI_STATUS
LcdPlatformSetMode (
IN UINT32 ModeNumber
)
{
EFI_STATUS Status;
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
return EFI_INVALID_PARAMETER;
}
// Set the video mode oscillator
do {
Status = ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq);
} while (Status == EFI_TIMEOUT);
if (EFI_ERROR(Status)) {
ASSERT_EFI_ERROR (Status);
return Status;
}
// Set the DVI into the new mode
do {
Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);
} while (Status == EFI_TIMEOUT);
if (EFI_ERROR(Status)) {
ASSERT_EFI_ERROR (Status);
return Status;
}
// Set the multiplexer
Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);
if (EFI_ERROR(Status)) {
ASSERT_EFI_ERROR (Status);
return Status;
}
return Status;
}
EFI_STATUS
LcdPlatformQueryMode (
IN UINT32 ModeNumber,
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
)
{
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
return EFI_INVALID_PARAMETER;
}
Info->Version = 0;
Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;
Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;
Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;
switch (mResolutions[ModeNumber].Bpp) {
case LCD_BITS_PER_PIXEL_24:
Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;
Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;
Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;
Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;
break;
case LCD_BITS_PER_PIXEL_16_555:
case LCD_BITS_PER_PIXEL_16_565:
case LCD_BITS_PER_PIXEL_12_444:
case LCD_BITS_PER_PIXEL_8:
case LCD_BITS_PER_PIXEL_4:
case LCD_BITS_PER_PIXEL_2:
case LCD_BITS_PER_PIXEL_1:
default:
// These are not supported
ASSERT(FALSE);
break;
}
return EFI_SUCCESS;
}
EFI_STATUS
LcdPlatformGetTimings (
IN UINT32 ModeNumber,
OUT UINT32* HRes,
OUT UINT32* HSync,
OUT UINT32* HBackPorch,
OUT UINT32* HFrontPorch,
OUT UINT32* VRes,
OUT UINT32* VSync,
OUT UINT32* VBackPorch,
OUT UINT32* VFrontPorch
)
{
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
return EFI_INVALID_PARAMETER;
}
*HRes = mResolutions[ModeNumber].HorizontalResolution;
*HSync = mResolutions[ModeNumber].HSync;
*HBackPorch = mResolutions[ModeNumber].HBackPorch;
*HFrontPorch = mResolutions[ModeNumber].HFrontPorch;
*VRes = mResolutions[ModeNumber].VerticalResolution;
*VSync = mResolutions[ModeNumber].VSync;
*VBackPorch = mResolutions[ModeNumber].VBackPorch;
*VFrontPorch = mResolutions[ModeNumber].VFrontPorch;
return EFI_SUCCESS;
}
EFI_STATUS
LcdPlatformGetBpp (
IN UINT32 ModeNumber,
OUT LCD_BPP * Bpp
)
{
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
return EFI_INVALID_PARAMETER;
}
*Bpp = mResolutions[ModeNumber].Bpp;
return EFI_SUCCESS;
}

44
ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf Normal file
View File

@@ -0,0 +1,44 @@
#/** @file
#
# Component description file for HdLcdArmLib module
#
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = HdLcdArmVExpress
FILE_GUID = 535a720e-06c0-4bb9-b563-452216abbed4
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = LcdPlatformLib
[Sources.common]
HdLcdArmVExpress.c
[Packages]
MdePkg/MdePkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
[LibraryClasses]
BaseLib
ArmPlatformSysConfigLib
[Protocols]
gEfiEdidDiscoveredProtocolGuid # Produced
gEfiEdidActiveProtocolGuid # Produced
[Pcd]
gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode
gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId