ArmPlatformPkg/ArmVExpress-CTA15-A7: Added support for CoreTile Express A15x2_A7x3
This is the big.LITTLE test chip for ARM Versatile Express Motherboard. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13775 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -0,0 +1,56 @@
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#/* @file
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#
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = CTA15A7ArmVExpressLib
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FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmPlatformLib
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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IoLib
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ArmLib
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MemoryAllocationLib
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SerialPortLib
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[Sources.common]
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CTA15-A7.c
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CTA15-A7Mem.c
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CTA15-A7Helper.asm | RVCT
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CTA15-A7Helper.S | GCC
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[FeaturePcd]
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gEmbeddedTokenSpaceGuid.PcdCacheEnable
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
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gArmPlatformTokenSpaceGuid.PcdStandalone
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[FixedPcd]
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gArmPlatformTokenSpaceGuid.PcdCoreCount
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gArmTokenSpaceGuid.PcdTrustzoneSupport
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gArmTokenSpaceGuid.PcdSystemMemoryBase
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gArmTokenSpaceGuid.PcdSystemMemorySize
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gArmTokenSpaceGuid.PcdFvBaseAddress
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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@@ -0,0 +1,193 @@
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/** @file
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*
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* Copyright (c) 2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/IoLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Ppi/ArmMpCoreInfo.h>
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#include <ArmPlatform.h>
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ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {
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{
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// Cluster 0, Core 0
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0x0, 0x0,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
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(UINT64)0
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},
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{
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// Cluster 0, Core 1
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0x0, 0x1,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
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(UINT64)0
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},
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#ifndef ARM_BIGLITTLE_TC2
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{
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// Cluster 0, Core 2
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0x0, 0x2,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
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(UINT64)0
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},
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{
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// Cluster 0, Core 3
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0x0, 0x3,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
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(UINT64)0
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},
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#endif
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{
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// Cluster 1, Core 0
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0x1, 0x0,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
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(UINT64)0
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},
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{
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// Cluster 1, Core 1
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0x1, 0x1,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
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(UINT64)0
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},
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{
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// Cluster 1, Core 2
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0x1, 0x2,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
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(UINT64)0
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}
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#ifndef ARM_BIGLITTLE_TC2
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,{
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// Cluster 1, Core 3
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0x1, 0x3,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
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(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
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(UINT64)0
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}
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#endif
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};
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/**
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Return the current Boot Mode
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This function returns the boot reason on the platform
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@return Return the current Boot Mode of the platform
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**/
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EFI_BOOT_MODE
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ArmPlatformGetBootMode (
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VOID
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)
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{
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return BOOT_WITH_FULL_CONFIGURATION;
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}
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/**
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Initialize controllers that must setup in the normal world
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This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
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in the PEI phase.
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**/
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RETURN_STATUS
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ArmPlatformInitialize (
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IN UINTN MpId
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)
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{
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if (!IS_PRIMARY_CORE(MpId)) {
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return RETURN_SUCCESS;
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}
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// Nothing to do here
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return RETURN_SUCCESS;
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}
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/**
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Initialize the system (or sometimes called permanent) memory
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This memory is generally represented by the DRAM.
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**/
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VOID
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ArmPlatformInitializeSystemMemory (
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VOID
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)
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{
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}
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EFI_STATUS
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PrePeiCoreGetMpCoreInfo (
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OUT UINTN *CoreCount,
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OUT ARM_CORE_INFO **ArmCoreTable
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)
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{
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// Only support one cluster
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*CoreCount = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);
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*ArmCoreTable = mVersatileExpressCTA15A7InfoTable;
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return EFI_SUCCESS;
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}
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// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
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EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
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ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
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EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI,
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&mArmMpCoreInfoPpiGuid,
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&mMpCoreInfoPpi
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}
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};
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VOID
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ArmPlatformGetPlatformPpiList (
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OUT UINTN *PpiListSize,
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OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
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)
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{
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*PpiListSize = sizeof(gPlatformPpiTable);
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*PpiList = gPlatformPpiTable;
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}
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@@ -0,0 +1,30 @@
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//
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// Copyright (c) 2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <Library/ArmLib.h>
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.text
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.align 3
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GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
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//UINTN
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//ArmPlatformGetCorePosition (
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// IN UINTN MpId
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// );
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ASM_PFX(ArmPlatformGetCorePosition):
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and r1, r0, #ARM_CORE_MASK
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and r0, r0, #ARM_CLUSTER_MASK
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add r0, r1, r0, LSR #7
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bx lr
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@@ -0,0 +1,34 @@
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//
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// Copyright (c) 2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <Library/ArmLib.h>
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmPlatformGetCorePosition
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PRESERVE8
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AREA CTA15A7Helper, CODE, READONLY
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//UINTN
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//ArmPlatformGetCorePosition (
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// IN UINTN MpId
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// );
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ArmPlatformGetCorePosition FUNCTION
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and r1, r0, #ARM_CORE_MASK
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and r0, r0, #ARM_CLUSTER_MASK
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add r0, r1, r0, LSR #7
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bx lr
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ENDFUNC
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END
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@@ -0,0 +1,194 @@
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/** @file
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*
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* Copyright (c) 2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
|
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* which accompanies this distribution. The full text of the license may be found at
|
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <ArmPlatform.h>
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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/**
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Return the Virtual Memory Map of your platform
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This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
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Virtual Memory mapping. This array must be ended by a zero-filled
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entry
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**/
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VOID
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ArmPlatformGetVirtualMemoryMap (
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IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
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)
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{
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ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
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UINTN Index = 0;
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ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
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ASSERT (VirtualMemoryMap != NULL);
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VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
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if (VirtualMemoryTable == NULL) {
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return;
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}
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if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
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CacheAttributes = DDR_ATTRIBUTES_CACHED;
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} else {
|
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CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
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}
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// Detect if it is a 1GB or 2GB Test Chip
|
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// [16:19]: 0=1GB TC2, 1=2GB TC2
|
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if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
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DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
|
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
|
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EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
|
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
|
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EFI_RESOURCE_ATTRIBUTE_TESTED,
|
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PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
|
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0x40000000
|
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);
|
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}
|
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#ifdef ARM_BIGLITTLE_TC2
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// Secure NOR0 Flash
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VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Secure RAM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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#endif
|
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|
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// SMB CS0 - NOR0 Flash
|
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VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
|
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
|
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VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Environment Variables region
|
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
|
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
|
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VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
|
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
// SMB CS1 or CS4 - NOR1 Flash
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE;
|
||||
VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
// Environment Variables region
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
|
||||
VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
// SMB CS3 or CS1 - PSRAM
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
|
||||
// Motherboard peripherals
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
// Non-secure ROM
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
#endif
|
||||
|
||||
// OnChip peripherals
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
// SCC Region
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE;
|
||||
VirtualMemoryTable[Index].Length = SIZE_64KB;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
// TC2 OnChip non-secure SRAM
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
#endif
|
||||
|
||||
#ifndef ARM_BIGLITTLE_TC2
|
||||
// Workaround for SRAM bug in RTSM
|
||||
if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {
|
||||
VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;
|
||||
VirtualMemoryTable[Index].VirtualBase = 0x80000000;
|
||||
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
}
|
||||
#endif
|
||||
|
||||
// DDR
|
||||
VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase);
|
||||
VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase);
|
||||
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
|
||||
// End of Table
|
||||
VirtualMemoryTable[++Index].PhysicalBase = 0;
|
||||
VirtualMemoryTable[Index].VirtualBase = 0;
|
||||
VirtualMemoryTable[Index].Length = 0;
|
||||
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
|
||||
|
||||
ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
|
||||
|
||||
*VirtualMemoryMap = VirtualMemoryTable;
|
||||
}
|
||||
|
||||
/**
|
||||
Return the EFI Memory Map provided by extension memory on your platform
|
||||
|
||||
This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
|
||||
Descriptor HOBs used by DXE core.
|
||||
|
||||
@param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
|
||||
EFI Memory region. This array must be ended by a zero-filled entry
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
ArmPlatformGetAdditionalSystemMemory (
|
||||
OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
Reference in New Issue
Block a user