ArmPlatformPkg/ArmVExpress-CTA15-A7: Added support for CoreTile Express A15x2_A7x3
This is the big.LITTLE test chip for ARM Versatile Express Motherboard. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13775 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
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/** @file
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*
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* Copyright (c) 2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <ArmPlatform.h>
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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/**
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Return the Virtual Memory Map of your platform
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This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
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Virtual Memory mapping. This array must be ended by a zero-filled
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entry
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**/
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VOID
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ArmPlatformGetVirtualMemoryMap (
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IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
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)
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{
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ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
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UINTN Index = 0;
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ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
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ASSERT (VirtualMemoryMap != NULL);
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VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
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if (VirtualMemoryTable == NULL) {
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return;
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}
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if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
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CacheAttributes = DDR_ATTRIBUTES_CACHED;
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} else {
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CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
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}
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// Detect if it is a 1GB or 2GB Test Chip
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// [16:19]: 0=1GB TC2, 1=2GB TC2
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if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
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DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
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0x40000000
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);
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}
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#ifdef ARM_BIGLITTLE_TC2
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// Secure NOR0 Flash
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VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Secure RAM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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#endif
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// SMB CS0 - NOR0 Flash
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VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
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VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Environment Variables region
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
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VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SMB CS1 or CS4 - NOR1 Flash
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE;
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VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Environment Variables region
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
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VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SMB CS3 or CS1 - PSRAM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// Motherboard peripherals
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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#ifdef ARM_BIGLITTLE_TC2
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// Non-secure ROM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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#endif
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// OnChip peripherals
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// SCC Region
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VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE;
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VirtualMemoryTable[Index].Length = SIZE_64KB;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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#ifdef ARM_BIGLITTLE_TC2
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// TC2 OnChip non-secure SRAM
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VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
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VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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#endif
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#ifndef ARM_BIGLITTLE_TC2
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// Workaround for SRAM bug in RTSM
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if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {
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VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;
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VirtualMemoryTable[Index].VirtualBase = 0x80000000;
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VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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}
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#endif
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// DDR
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase);
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VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase);
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VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// End of Table
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VirtualMemoryTable[++Index].PhysicalBase = 0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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VirtualMemoryTable[Index].Length = 0;
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VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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*VirtualMemoryMap = VirtualMemoryTable;
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}
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/**
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Return the EFI Memory Map provided by extension memory on your platform
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This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
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Descriptor HOBs used by DXE core.
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@param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
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EFI Memory region. This array must be ended by a zero-filled entry
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**/
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EFI_STATUS
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ArmPlatformGetAdditionalSystemMemory (
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OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
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)
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{
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return EFI_UNSUPPORTED;
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}
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