UefiCpuPkg: Replace Opcode with the corresponding instructions.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
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@@ -1,5 +1,5 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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@@ -32,12 +32,13 @@ SECTION .text
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ALIGN 8
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AsmIdtVectorBegin:
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%assign Vector 0
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%rep 32
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db 0x6a ; push #VectorNum
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db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
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push byte %[Vector]
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push rax
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mov rax, ASM_PFX(CommonInterruptEntry)
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jmp rax
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%assign Vector Vector+1
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%endrep
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AsmIdtVectorEnd:
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@@ -257,7 +258,7 @@ DrFinish:
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;; FX_SAVE_STATE_X64 FxSaveState;
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sub rsp, 512
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mov rdi, rsp
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db 0xf, 0xae, 0x7 ;fxsave [rdi]
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fxsave [rdi]
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;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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cld
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@@ -284,7 +285,7 @@ DrFinish:
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;; FX_SAVE_STATE_X64 FxSaveState;
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mov rsi, rsp
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db 0xf, 0xae, 0xE ; fxrstor [rsi]
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fxrstor [rsi]
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add rsp, 512
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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@@ -371,8 +372,7 @@ DoReturn:
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push qword [rax + 0x18] ; save EFLAGS in new location
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mov rax, [rax] ; restore rax
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popfq ; restore EFLAGS
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DB 0x48 ; prefix to composite "retq" with next "retf"
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retf ; far return
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retfq
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DoIret:
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iretq
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