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Fix issue with fixing tabs.

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11297 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2011-02-02 23:19:30 +00:00
parent 5d23922674
commit 2ac288f919
73 changed files with 2559 additions and 2559 deletions
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80
ArmPkg/Include/Drivers/PL341Dmc.h
View File

@@ -17,32 +17,32 @@
struct pl341_dmc_config {
UINTN\s\sbase; // base address for the controller
UINTN\s\shas_qos; // has QoS registers
UINTN\s\smax_chip; // number of memory chips accessible
UINT32\s\srefresh_prd;
UINT32\s\scas_latency;
UINT32\s\swrite_latency;
UINT32\s\st_mrd;
UINT32\s\st_ras;
UINT32\s\st_rc;
UINT32\s\st_rcd;
UINT32\s\st_rfc;
UINT32\s\st_rp;
UINT32\s\st_rrd;
UINT32\s\st_wr;
UINT32\s\st_wtr;
UINT32\s\st_xp;
UINT32\s\st_xsr;
UINT32\s\st_esr;
UINT32\s\smemory_cfg;
UINT32\s\smemory_cfg2;
UINT32\s\smemory_cfg3;
UINT32\s\schip_cfg0;
UINT32\s\schip_cfg1;
UINT32\s\schip_cfg2;
UINT32\s\schip_cfg3;
UINT32\s\st_faw;
UINTN base; // base address for the controller
UINTN has_qos; // has QoS registers
UINTN max_chip; // number of memory chips accessible
UINT32 refresh_prd;
UINT32 cas_latency;
UINT32 write_latency;
UINT32 t_mrd;
UINT32 t_ras;
UINT32 t_rc;
UINT32 t_rcd;
UINT32 t_rfc;
UINT32 t_rp;
UINT32 t_rrd;
UINT32 t_wr;
UINT32 t_wtr;
UINT32 t_xp;
UINT32 t_xsr;
UINT32 t_esr;
UINT32 memory_cfg;
UINT32 memory_cfg2;
UINT32 memory_cfg3;
UINT32 chip_cfg0;
UINT32 chip_cfg1;
UINT32 chip_cfg2;
UINT32 chip_cfg3;
UINT32 t_faw;
};
/* Memory config bit fields */
@@ -60,21 +60,21 @@ struct pl341_dmc_config {
#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1\s\s\s\s(0x0 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2\s\s\s\s(0x1 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3\s\s\s\s(0x2 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4\s\s\s\s(0x3 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
#define DMC_MEMORY_CFG2_CLK_ASYNC\s\s\s\s(0x0 << 0)
#define DMC_MEMORY_CFG2_CLK_SYNC\s\s\s\s(0x1 << 0)
#define DMC_MEMORY_CFG2_DQM_INIT\s\s\s\s(0x1 << 2)
#define DMC_MEMORY_CFG2_CKE_INIT\s\s\s\s(0x1 << 3)
#define DMC_MEMORY_CFG2_BANK_BITS_2\s\s\s\s(0x0 << 4)
#define DMC_MEMORY_CFG2_BANK_BITS_3\s\s\s\s(0x3 << 4)
#define DMC_MEMORY_CFG2_MEM_WIDTH_16\s\s\s\s(0x0 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_32\s\s\s\s(0x1 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_64\s\s\s\s(0x2 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED\s\s(0x3 << 6)
#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)

2
ArmPkg/Include/Library/L2X0CacheLib.h
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@@ -29,7 +29,7 @@
#define L230_TAG_LATENCY 0x108
#define L230_DATA_LATENCY 0x10C
#define L2X0_INTCLEAR 0x220
#define L2X0_CACHE_SYNC\s\s\s\s\s\s0x730
#define L2X0_CACHE_SYNC 0x730
#define L2X0_INVWAY 0x77C
#define L2X0_CLEAN_WAY 0x7BC
#define L2X0_PFCTRL 0xF60

2
ArmPkg/Include/Protocol/VirtualUncachedPages.h
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@@ -57,4 +57,4 @@ struct _VIRTUAL_UNCACHED_PAGES_PROTOCOL {
extern EFI_GUID gVirtualUncachedPagesProtocolGuid;
#endif\s\s
#endif