Fix issue with fixing tabs.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11297 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
@@ -70,17 +70,17 @@ ArmDisableAsynchronousAbort
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ArmEnableIrq
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cpsie i
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isb
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\s\sbx LR
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bx LR
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ArmDisableIrq
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cpsid i
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isb
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\s\sbx LR
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bx LR
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ArmEnableFiq
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cpsie f
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isb
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\s\sbx LR
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bx LR
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ArmDisableFiq
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cpsid f
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@@ -99,17 +99,17 @@ ArmDisableInterrupts
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ArmGetInterruptState
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mrs R0,CPSR
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tst R0,#0x80\s\s ;Check if IRQ is enabled.
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tst R0,#0x80 ;Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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\s\sbx LR
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bx LR
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ArmGetFiqState
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\s\smrs R0,CPSR
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\s\stst R0,#0x40\s\s ;Check if FIQ is enabled.
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\s\smoveq R0,#1
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\s\smovne R0,#0
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\s\sbx LR
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mrs R0,CPSR
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tst R0,#0x40 ;Check if FIQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmInvalidateTlb
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mov r0,#0
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@@ -126,7 +126,7 @@ ArmSetTTBR0
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ArmGetTTBR0BaseAddress
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mrc p15,0,r0,c2,c0,0
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ldr\s\s r1, = 0xFFFFC000
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ldr r1, = 0xFFFFC000
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and r0, r0, r1
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isb
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bx lr
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@@ -31,7 +31,7 @@ ASM_PFX(ArmGetScuBaseAddress):
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# the Configuration BAR as a stack is not necessary setup. The SCU is at the
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# offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx\s\slr
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bx lr
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# IN None
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# OUT r1 = SCU enabled (boolean)
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@@ -31,7 +31,7 @@ ArmGetScuBaseAddress
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx\s\slr
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bx lr
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// IN None
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// OUT r1 = SCU enabled (boolean)
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@@ -80,21 +80,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
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ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
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mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\s\s\s\s
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mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
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dsb
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isb
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
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mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\s\s\s\s
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mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
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dsb
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isb
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bx lr
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ASM_PFX(ArmCleanDataCacheEntryBySetWay):
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mcr p15, 0, r0, c7, c10, 2 @ Clean this line\s\s\s\s
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mcr p15, 0, r0, c7, c10, 2 @ Clean this line
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dsb
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isb
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bx lr
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@@ -119,7 +119,7 @@ ASM_PFX(ArmDisableMmu):
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0 @Disable MMU
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\s\smcr \s\s\s\sp15,0,R0,c8,c7,0 @Invalidate TLB
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mcr p15,0,R0,c8,c7,0 @Invalidate TLB
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mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
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dsb
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isb
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@@ -309,7 +309,7 @@ ASM_PFX(ArmCallWFI):
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//Note: Return 0 in Uniprocessor implementation
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ASM_PFX(ArmReadCbar):
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mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register
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mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
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bx lr
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ASM_PFX(ArmInvalidateInstructionAndDataTlb):
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@@ -318,7 +318,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb):
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bx lr
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ASM_PFX(ArmReadMpidr):
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mrc p15, 0, r0, c0, c0, 5\s\s @ read MPIDR
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mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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@@ -82,21 +82,21 @@ ArmCleanInvalidateDataCacheEntryByMVA
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ArmInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\s\s\s\s
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\s\s\s\s
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
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dsb
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isb
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bx lr
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ArmCleanDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line\s\s\s\s
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line
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dsb
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isb
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bx lr
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@@ -125,7 +125,7 @@ ArmDisableMmu
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bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
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mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
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mcr \s\s p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
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mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
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mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
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dsb
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isb
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@@ -307,7 +307,7 @@ ArmCallWFI
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//Note: Return 0 in Uniprocessor implementation
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ArmReadCbar
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mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register
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mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
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bx lr
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ArmInvalidateInstructionAndDataTlb
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@@ -316,7 +316,7 @@ ArmInvalidateInstructionAndDataTlb
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bx lr
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ArmReadMpidr
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mrc p15, 0, r0, c0, c0, 5\s\s\s\s; read MPIDR
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mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
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bx lr
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END
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