sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix issue with fixing tabs.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11297 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2011-02-02 23:19:30 +00:00
parent 5d23922674
commit 2ac288f919
73 changed files with 2559 additions and 2559 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
ArmPkg/Drivers/CpuDxe/CpuDxe.h
View File

@ -111,8 +111,8 @@ CpuSetMemoryAttributes (
EFI_STATUS EFI_STATUS
InitializeExceptions ( InitializeExceptions (
\s\sIN EFI_CPU_ARCH_PROTOCOL *Cpu IN EFI_CPU_ARCH_PROTOCOL *Cpu
\s\s); );
EFI_STATUS EFI_STATUS
SyncCacheConfig ( SyncCacheConfig (

16
ArmPkg/Drivers/CpuDxe/Mmu.c
View File

@ -338,11 +338,11 @@ UpdatePageEntries (
// modify cacheability attributes // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) { if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
\s\s\s\s // map to strongly ordered // map to strongly ordered
\s\s\s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else { } else {
\s\s // map to normal non-cachable // map to normal non-cachable
\s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} }
break; break;
@ -486,11 +486,11 @@ UpdateSectionEntries (
// modify cacheability attributes // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) { if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
\s\s\s\s // map to strongly ordered // map to strongly ordered
\s\s\s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else { } else {
\s\s // map to normal non-cachable // map to normal non-cachable
\s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
} }
break; break;

234
ArmPkg/Drivers/PL34xDmc/PL341Dmc.c
View File

@ -64,7 +64,7 @@
#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18) #define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)
#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22) #define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)
#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16) #define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)
#define DMC_DIRECT_CMD_CHIP_ADDR(n)\s\s\s\s((n & 0x3) << 20) #define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)
// //
@ -163,25 +163,25 @@ VOID PL341DmcInit(struct pl341_dmc_config *config) {
// //
if (config->has_qos) { if (config->has_qos) {
\s\s// CLCD AXIID = 000 // CLCD AXIID = 000
\s\sDmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN); DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);
\s\s// Default disable QoS // Default disable QoS
\s\sDmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
\s\sDmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE); DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);
} }
// //
@ -231,104 +231,104 @@ VOID PL341DmcInit(struct pl341_dmc_config *config) {
// |====================================== // |======================================
DmcWriteReg(DMC_MEMORY_CFG3_REG, config->memory_cfg3); DmcWriteReg(DMC_MEMORY_CFG3_REG, config->memory_cfg3);
\s\s// |======================================================== // |========================================================
\s\s// |Set Test Chip PHY Registers via PL341 User Config Reg // |Set Test Chip PHY Registers via PL341 User Config Reg
\s\s// |Note that user_cfgX registers are Write Only // |Note that user_cfgX registers are Write Only
\s\s// | // |
\s\s// |DLL Freq set = 250MHz - 266MHz // |DLL Freq set = 250MHz - 266MHz
\s\s// |======================================================== // |========================================================
\s\sDmcWriteReg(DMC_USER_0_CFG_REG, 0x7C924924); DmcWriteReg(DMC_USER_0_CFG_REG, 0x7C924924);
\s\s// user_config2 // user_config2
\s\s// ------------ // ------------
\s\s// Set defaults before calibrating the DDR2 buffer impendence // Set defaults before calibrating the DDR2 buffer impendence
\s\s// -Disable ODT // -Disable ODT
\s\s// -Default drive strengths // -Default drive strengths
\s\sDmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198); DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);
\s\s// |======================================================= // |=======================================================
\s\s// |Auto calibrate the DDR2 buffers impendence // |Auto calibrate the DDR2 buffers impendence
\s\s// |======================================================= // |=======================================================
\s\sval32 = DmcReadReg(DMC_USER_STATUS_REG); val32 = DmcReadReg(DMC_USER_STATUS_REG);
\s\swhile (!(val32 & 0x100)) { while (!(val32 & 0x100)) {
\s\s val32 = DmcReadReg(DMC_USER_STATUS_REG); val32 = DmcReadReg(DMC_USER_STATUS_REG);
\s\s} }
\s\s// Set the output driven strength // Set the output driven strength
\s\sDmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 |
\s\s\s\s (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) |
\s\s\s\s (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) |
\s\s\s\s (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) |
\s\s\s\s (0x1 << TC_UIOHSTOP_SHIFT)); (0x1 << TC_UIOHSTOP_SHIFT));
\s\s// |====================================== // |======================================
\s\s// | Set PL341 Feature Control Register // | Set PL341 Feature Control Register
\s\s// |====================================== // |======================================
\s\s// | Disable early BRESP - use to optimise CLCD performance // | Disable early BRESP - use to optimise CLCD performance
\s\sDmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001); DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);
//================= //=================
// Config memories // Config memories
//================= //=================
for (chip = 0; chip <= config-> max_chip; chip++) { for (chip = 0; chip <= config-> max_chip; chip++) {
\s\s// send nop // send nop
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP); DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_NOP);
\s\s// pre-charge all // pre-charge all
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL); DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
\s\s// delay // delay
\s\sfor (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
\s\s val32 = DmcReadReg(DMC_STATUS_REG); val32 = DmcReadReg(DMC_STATUS_REG);
\s\s} }
\s\s// set (EMR2) extended mode register 2 // set (EMR2) extended mode register 2
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DmcWriteReg(DMC_DIRECT_CMD_REG,
\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_CHIP_ADDR(chip) |
\s\s\s\s DMC_DIRECT_CMD_BANKADDR(2) | DMC_DIRECT_CMD_BANKADDR(2) |
\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG); DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
\s\s// set (EMR3) extended mode register 3 // set (EMR3) extended mode register 3
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DmcWriteReg(DMC_DIRECT_CMD_REG,
\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_CHIP_ADDR(chip) |
\s\s\s\s DMC_DIRECT_CMD_BANKADDR(3) | DMC_DIRECT_CMD_BANKADDR(3) |
\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG); DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
\s\s// ================================= // =================================
\s\s// set (EMR) Extended Mode Register // set (EMR) Extended Mode Register
\s\s// ================================== // ==================================
\s\s// Put into OCD default state // Put into OCD default state
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DmcWriteReg(DMC_DIRECT_CMD_REG,
\s\s\s\s DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_CHIP_ADDR(chip) |
\s\s\s\s DMC_DIRECT_CMD_BANKADDR(1) | DMC_DIRECT_CMD_BANKADDR(1) |
\s\s\s\s DMC_DIRECT_CMD_MEMCMD_EXTMODEREG); DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);
\s\s// =========================================================== // ===========================================================
\s\s// set (MR) mode register - With DLL reset // set (MR) mode register - With DLL reset
\s\s// =========================================================== // ===========================================================
\s\s// Burst Length = 4 (010) // Burst Length = 4 (010)
\s\s// Burst Type = Seq (0) // Burst Type = Seq (0)
\s\s// Latency = 4 (100) // Latency = 4 (100)
\s\s// Test mode = Off (0) // Test mode = Off (0)
\s\s// DLL reset = Yes (1) // DLL reset = Yes (1)
\s\s// Wr Recovery = 4 (011) // Wr Recovery = 4 (011)
\s\s// PD = Normal (0) // PD = Normal (0)
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080742); DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080742);
\s\s// pre-charge all // pre-charge all
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL); DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);
\s\s// auto-refresh // auto-refresh
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH); DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
\s\s// auto-refresh // auto-refresh
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH); DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
\s\s// delay // delay
\s\sfor (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
\s\s val32 = DmcReadReg(DMC_STATUS_REG); val32 = DmcReadReg(DMC_STATUS_REG);
\s\s} }
\s\s// =========================================================== // ===========================================================
\s\s// set (MR) mode register - Without DLL reset // set (MR) mode register - Without DLL reset
\s\s// =========================================================== // ===========================================================
// auto-refresh // auto-refresh
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH); DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080642); DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00080642);
@ -338,26 +338,26 @@ VOID PL341DmcInit(struct pl341_dmc_config *config) {
val32 = DmcReadReg(DMC_STATUS_REG); val32 = DmcReadReg(DMC_STATUS_REG);
} }
\s\s// ====================================================== // ======================================================
\s\s// set (EMR) extended mode register - Enable OCD defaults // set (EMR) extended mode register - Enable OCD defaults
\s\s// ====================================================== // ======================================================
\s\sval32 = 0; //NOP val32 = 0; //NOP
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |
\s\s\s\s (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) |
\s\s\s\s DDR_EMR_RTT_75R | DDR_EMR_RTT_75R |
\s\s\s\s (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK)); (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));
\s\s// delay // delay
\s\sfor (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
\s\s val32 = DmcReadReg(DMC_STATUS_REG); val32 = DmcReadReg(DMC_STATUS_REG);
\s\s} }
\s\s// Set (EMR) extended mode register - OCD Exit // Set (EMR) extended mode register - OCD Exit
\s\sval32 = 0; //NOP val32 = 0; //NOP
\s\sDmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 | DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(chip) | 0x00090000 |
\s\s\s\s (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) |
\s\s\s\s DDR_EMR_RTT_75R | DDR_EMR_RTT_75R |
\s\s\s\s (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK)); (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK));
} }

24
ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
View File

@ -21,11 +21,11 @@ EFIAPI
PL390GicEnableInterruptInterface ( PL390GicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{\s\s {
\s\s/* /*
\s\s * Enable the CPU interface in Non-Secure world * Enable the CPU interface in Non-Secure world
\s\s * Note: The ICCICR register is banked when Security extensions are implemented\s\s * Note: The ICCICR register is banked when Security extensions are implemented
\s\s */ */
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
} }
@ -50,7 +50,7 @@ PL390GicSendSgiTo (
IN INTN CPUTargetList IN INTN CPUTargetList
) )
{ {
\s\sMmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16)); MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
} }
UINT32 UINT32
@ -65,9 +65,9 @@ PL390GicAcknowledgeSgiFrom (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
\s\sif (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) { if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
return 0; return 0;
@ -87,9 +87,9 @@ PL390GicAcknowledgeSgi2From (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
\s\sif((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) { if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
return 0; return 0;

42
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@ -34,11 +34,11 @@ PL390GicSetupNonSecure (
//Check if there are any pending interrupts //Check if there are any pending interrupts
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))
{ {
\s\s //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
\s\s UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
\s\s //Write to End of interrupt signal //Write to End of interrupt signal
\s\s MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
} }
// Ensure all GIC interrupts are Non-Secure // Ensure all GIC interrupts are Non-Secure
@ -56,19 +56,19 @@ PL390GicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */ MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
\s\s/* /*
\s\s * Enable CPU interface in Secure world * Enable CPU interface in Secure world
* Enable CPU inteface in Non-secure World * Enable CPU inteface in Non-secure World
\s\s * Signal Secure Interrupts to CPU using FIQ line * * Signal Secure Interrupts to CPU using FIQ line *
\s\s */ */
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR, MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
\s\s\s\sGIC_ICCICR_ENABLE_SECURE(1) | GIC_ICCICR_ENABLE_SECURE(1) |
\s\s\s\sGIC_ICCICR_ENABLE_NS(1) | GIC_ICCICR_ENABLE_NS(1) |
\s\s\s\sGIC_ICCICR_ACK_CTL(0) | GIC_ICCICR_ACK_CTL(0) |
\s\s\s\sGIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) | GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
\s\s\s\sGIC_ICCICR_USE_SBPR(0)); GIC_ICCICR_USE_SBPR(0));
} }
VOID VOID
@ -88,7 +88,7 @@ PL390GicSendSgiTo (
IN INTN CPUTargetList IN INTN CPUTargetList
) )
{ {
\s\sMmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16)); MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
} }
UINT32 UINT32
@ -103,9 +103,9 @@ PL390GicAcknowledgeSgiFrom (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
\s\sif (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) { if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
return 0; return 0;
@ -125,9 +125,9 @@ PL390GicAcknowledgeSgi2From (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
\s\sif((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) { if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
return 0; return 0;

80
ArmPkg/Include/Drivers/PL341Dmc.h
View File

@ -17,32 +17,32 @@
struct pl341_dmc_config { struct pl341_dmc_config {
UINTN\s\sbase; // base address for the controller UINTN base; // base address for the controller
UINTN\s\shas_qos; // has QoS registers UINTN has_qos; // has QoS registers
UINTN\s\smax_chip; // number of memory chips accessible UINTN max_chip; // number of memory chips accessible
UINT32\s\srefresh_prd; UINT32 refresh_prd;
UINT32\s\scas_latency; UINT32 cas_latency;
UINT32\s\swrite_latency; UINT32 write_latency;
UINT32\s\st_mrd; UINT32 t_mrd;
UINT32\s\st_ras; UINT32 t_ras;
UINT32\s\st_rc; UINT32 t_rc;
UINT32\s\st_rcd; UINT32 t_rcd;
UINT32\s\st_rfc; UINT32 t_rfc;
UINT32\s\st_rp; UINT32 t_rp;
UINT32\s\st_rrd; UINT32 t_rrd;
UINT32\s\st_wr; UINT32 t_wr;
UINT32\s\st_wtr; UINT32 t_wtr;
UINT32\s\st_xp; UINT32 t_xp;
UINT32\s\st_xsr; UINT32 t_xsr;
UINT32\s\st_esr; UINT32 t_esr;
UINT32\s\smemory_cfg; UINT32 memory_cfg;
UINT32\s\smemory_cfg2; UINT32 memory_cfg2;
UINT32\s\smemory_cfg3; UINT32 memory_cfg3;
UINT32\s\schip_cfg0; UINT32 chip_cfg0;
UINT32\s\schip_cfg1; UINT32 chip_cfg1;
UINT32\s\schip_cfg2; UINT32 chip_cfg2;
UINT32\s\schip_cfg3; UINT32 chip_cfg3;
UINT32\s\st_faw; UINT32 t_faw;
}; };
/* Memory config bit fields */ /* Memory config bit fields */
@ -60,21 +60,21 @@ struct pl341_dmc_config {
#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15) #define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)
#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15) #define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)
#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15) #define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1\s\s\s\s(0x0 << 21) #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2\s\s\s\s(0x1 << 21) #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3\s\s\s\s(0x2 << 21) #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4\s\s\s\s(0x3 << 21) #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)
#define DMC_MEMORY_CFG2_CLK_ASYNC\s\s\s\s(0x0 << 0) #define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)
#define DMC_MEMORY_CFG2_CLK_SYNC\s\s\s\s(0x1 << 0) #define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)
#define DMC_MEMORY_CFG2_DQM_INIT\s\s\s\s(0x1 << 2) #define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)
#define DMC_MEMORY_CFG2_CKE_INIT\s\s\s\s(0x1 << 3) #define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)
#define DMC_MEMORY_CFG2_BANK_BITS_2\s\s\s\s(0x0 << 4) #define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)
#define DMC_MEMORY_CFG2_BANK_BITS_3\s\s\s\s(0x3 << 4) #define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)
#define DMC_MEMORY_CFG2_MEM_WIDTH_16\s\s\s\s(0x0 << 6) #define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_32\s\s\s\s(0x1 << 6) #define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_64\s\s\s\s(0x2 << 6) #define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED\s\s(0x3 << 6) #define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)

2
ArmPkg/Include/Library/L2X0CacheLib.h
View File

@ -29,7 +29,7 @@
#define L230_TAG_LATENCY 0x108 #define L230_TAG_LATENCY 0x108
#define L230_DATA_LATENCY 0x10C #define L230_DATA_LATENCY 0x10C
#define L2X0_INTCLEAR 0x220 #define L2X0_INTCLEAR 0x220
#define L2X0_CACHE_SYNC\s\s\s\s\s\s0x730 #define L2X0_CACHE_SYNC 0x730
#define L2X0_INVWAY 0x77C #define L2X0_INVWAY 0x77C
#define L2X0_CLEAN_WAY 0x7BC #define L2X0_CLEAN_WAY 0x7BC
#define L2X0_PFCTRL 0xF60 #define L2X0_PFCTRL 0xF60

2
ArmPkg/Include/Protocol/VirtualUncachedPages.h
View File

@ -57,4 +57,4 @@ struct _VIRTUAL_UNCACHED_PAGES_PROTOCOL {
extern EFI_GUID gVirtualUncachedPagesProtocolGuid; extern EFI_GUID gVirtualUncachedPagesProtocolGuid;
#endif\s\s #endif

12
ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
View File

@ -58,18 +58,18 @@ ASM_PFX(ArmEnableInstructionCache):
orr r0,r0,r1 @Set I bit orr r0,r0,r1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR bx LR
\s\s
ASM_PFX(ArmDisableInstructionCache): ASM_PFX(ArmDisableInstructionCache):
ldr r1,=IC_ON ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data mrc p15,0,r0,c1,c0,0 @Read control register configuration data
bic r0,r0,r1 @Clear I bit. bic r0,r0,r1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR bx LR
\s\s
ASM_PFX(ArmInvalidateInstructionCache): ASM_PFX(ArmInvalidateInstructionCache):
mov r0,#0 mov r0,#0
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache. mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
\s\s @Also flushes the branch target cache. @Also flushes the branch target cache.
mov r0,#0 mov r0,#0
mcr p15,0,r0,c7,c10,4 @Data write buffer mcr p15,0,r0,c7,c10,4 @Data write buffer
bx LR bx LR
@ -99,7 +99,7 @@ ASM_PFX(ArmEnableDataCache):
orr R0,R0,R1 @Set C bit orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR bx LR
\s\s
ASM_PFX(ArmDisableDataCache): ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@ -111,7 +111,7 @@ ASM_PFX(ArmCleanDataCache):
mrc p15,0,r15,c7,c10,3 mrc p15,0,r15,c7,c10,3
bne ASM_PFX(ArmCleanDataCache) bne ASM_PFX(ArmCleanDataCache)
mov R0,#0 mov R0,#0
mcr p15,0,R0,c7,c10,4\s\s@Drain write buffer mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR bx LR
ASM_PFX(ArmInvalidateDataCache): ASM_PFX(ArmInvalidateDataCache):
@ -125,7 +125,7 @@ ASM_PFX(ArmCleanInvalidateDataCache):
mrc p15,0,r15,c7,c14,3 mrc p15,0,r15,c7,c14,3
bne ASM_PFX(ArmCleanInvalidateDataCache) bne ASM_PFX(ArmCleanInvalidateDataCache)
mov R0,#0 mov R0,#0
mcr p15,0,R0,c7,c10,4\s\s @Drain write buffer mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR bx LR
ASM_PFX(ArmEnableBranchPrediction): ASM_PFX(ArmEnableBranchPrediction):

4
ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
View File

@ -112,7 +112,7 @@ ArmCleanDataCache
MRC p15,0,r15,c7,c10,3 MRC p15,0,r15,c7,c10,3
BNE ArmCleanDataCache BNE ArmCleanDataCache
MOV R0,#0 MOV R0,#0
MCR p15,0,R0,c7,c10,4\s\s ;Drain write buffer MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR BX LR
ArmInvalidateDataCache ArmInvalidateDataCache
@ -126,7 +126,7 @@ ArmCleanInvalidateDataCache
MRC p15,0,r15,c7,c14,3 MRC p15,0,r15,c7,c14,3
BNE ArmCleanInvalidateDataCache BNE ArmCleanInvalidateDataCache
MOV R0,#0 MOV R0,#0
MCR p15,0,R0,c7,c10,4\s\s ;Drain write buffer MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR BX LR
ArmEnableBranchPrediction ArmEnableBranchPrediction

22
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
View File

@ -70,17 +70,17 @@ ArmDisableAsynchronousAbort
ArmEnableIrq ArmEnableIrq
cpsie i cpsie i
isb isb
\s\sbx LR bx LR
ArmDisableIrq ArmDisableIrq
cpsid i cpsid i
isb isb
\s\sbx LR bx LR
ArmEnableFiq ArmEnableFiq
cpsie f cpsie f
isb isb
\s\sbx LR bx LR
ArmDisableFiq ArmDisableFiq
cpsid f cpsid f
@ -99,17 +99,17 @@ ArmDisableInterrupts
ArmGetInterruptState ArmGetInterruptState
mrs R0,CPSR mrs R0,CPSR
tst R0,#0x80\s\s ;Check if IRQ is enabled. tst R0,#0x80 ;Check if IRQ is enabled.
moveq R0,#1 moveq R0,#1
movne R0,#0 movne R0,#0
\s\sbx LR bx LR
ArmGetFiqState ArmGetFiqState
\s\smrs R0,CPSR mrs R0,CPSR
\s\stst R0,#0x40\s\s ;Check if FIQ is enabled. tst R0,#0x40 ;Check if FIQ is enabled.
\s\smoveq R0,#1 moveq R0,#1
\s\smovne R0,#0 movne R0,#0
\s\sbx LR bx LR
ArmInvalidateTlb ArmInvalidateTlb
mov r0,#0 mov r0,#0
@ -126,7 +126,7 @@ ArmSetTTBR0
ArmGetTTBR0BaseAddress ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0 mrc p15,0,r0,c2,c0,0
ldr\s\s r1, = 0xFFFFC000 ldr r1, = 0xFFFFC000
and r0, r0, r1 and r0, r0, r1
isb isb
bx lr bx lr

2
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S
View File

@ -31,7 +31,7 @@ ASM_PFX(ArmGetScuBaseAddress):
# the Configuration BAR as a stack is not necessary setup. The SCU is at the # the Configuration BAR as a stack is not necessary setup. The SCU is at the
# offset 0x0000 from the Private Memory Region. # offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0 mrc p15, 4, r0, c15, c0, 0
bx\s\slr bx lr
# IN None # IN None
# OUT r1 = SCU enabled (boolean) # OUT r1 = SCU enabled (boolean)

2
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm
View File

@ -31,7 +31,7 @@ ArmGetScuBaseAddress
// the Configuration BAR as a stack is not necessary setup. The SCU is at the // the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region. // offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0 mrc p15, 4, r0, c15, c0, 0
bx\s\slr bx lr
// IN None // IN None
// OUT r1 = SCU enabled (boolean) // OUT r1 = SCU enabled (boolean)

12
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@ -80,21 +80,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\s\s\s\s mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
dsb dsb
isb isb
bx lr bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\s\s\s\s mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
dsb dsb
isb isb
bx lr bx lr
ASM_PFX(ArmCleanDataCacheEntryBySetWay): ASM_PFX(ArmCleanDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c10, 2 @ Clean this line\s\s\s\s mcr p15, 0, r0, c7, c10, 2 @ Clean this line
dsb dsb
isb isb
bx lr bx lr
@ -119,7 +119,7 @@ ASM_PFX(ArmDisableMmu):
bic R0,R0,#1 bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 @Disable MMU mcr p15,0,R0,c1,c0,0 @Disable MMU
\s\smcr \s\s\s\sp15,0,R0,c8,c7,0 @Invalidate TLB mcr p15,0,R0,c8,c7,0 @Invalidate TLB
mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
dsb dsb
isb isb
@ -309,7 +309,7 @@ ASM_PFX(ArmCallWFI):
//Note: Return 0 in Uniprocessor implementation //Note: Return 0 in Uniprocessor implementation
ASM_PFX(ArmReadCbar): ASM_PFX(ArmReadCbar):
mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
bx lr bx lr
ASM_PFX(ArmInvalidateInstructionAndDataTlb): ASM_PFX(ArmInvalidateInstructionAndDataTlb):
@ -318,7 +318,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb):
bx lr bx lr
ASM_PFX(ArmReadMpidr): ASM_PFX(ArmReadMpidr):
mrc p15, 0, r0, c0, c0, 5\s\s @ read MPIDR mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
bx lr bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED ASM_FUNCTION_REMOVE_IF_UNREFERENCED

12
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -82,21 +82,21 @@ ArmCleanInvalidateDataCacheEntryByMVA
ArmInvalidateDataCacheEntryBySetWay ArmInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\s\s\s\s mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
dsb dsb
isb isb
bx lr bx lr
ArmCleanInvalidateDataCacheEntryBySetWay ArmCleanInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\s\s\s\s mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
dsb dsb
isb isb
bx lr bx lr
ArmCleanDataCacheEntryBySetWay ArmCleanDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c10, 2 ; Clean this line\s\s\s\s mcr p15, 0, r0, c7, c10, 2 ; Clean this line
dsb dsb
isb isb
bx lr bx lr
@ -125,7 +125,7 @@ ArmDisableMmu
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
mcr \s\s p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
dsb dsb
isb isb
@ -307,7 +307,7 @@ ArmCallWFI
//Note: Return 0 in Uniprocessor implementation //Note: Return 0 in Uniprocessor implementation
ArmReadCbar ArmReadCbar
mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
bx lr bx lr
ArmInvalidateInstructionAndDataTlb ArmInvalidateInstructionAndDataTlb
@ -316,7 +316,7 @@ ArmInvalidateInstructionAndDataTlb
bx lr bx lr
ArmReadMpidr ArmReadMpidr
mrc p15, 0, r0, c0, c0, 5\s\s\s\s; read MPIDR mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
bx lr bx lr
END END

52
ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
View File

@ -42,48 +42,48 @@ ASM_PFX(Cp15CacheInfo):
bx LR bx LR
ASM_PFX(ArmEnableInterrupts): ASM_PFX(ArmEnableInterrupts):
\s\smrs R0,CPSR mrs R0,CPSR
\s\sbic R0,R0,#0x80\s\s\s\s@Enable IRQ interrupts bic R0,R0,#0x80 @Enable IRQ interrupts
\s\smsr CPSR_c,R0 msr CPSR_c,R0
\s\sbx LR bx LR
ASM_PFX(ArmDisableInterrupts): ASM_PFX(ArmDisableInterrupts):
\s\smrs R0,CPSR mrs R0,CPSR
\s\sorr R1,R0,#0x80\s\s\s\s@Disable IRQ interrupts orr R1,R0,#0x80 @Disable IRQ interrupts
\s\smsr CPSR_c,R1 msr CPSR_c,R1
tst R0,#0x80 tst R0,#0x80
moveq R0,#1 moveq R0,#1
movne R0,#0 movne R0,#0
\s\sbx LR bx LR
ASM_PFX(ArmGetInterruptState): ASM_PFX(ArmGetInterruptState):
\s\smrs R0,CPSR mrs R0,CPSR
\s\stst R0,#0x80\s\s @Check if IRQ is enabled. tst R0,#0x80 @Check if IRQ is enabled.
\s\smoveq R0,#1 moveq R0,#1
\s\smovne R0,#0 movne R0,#0
\s\sbx LR bx LR
ASM_PFX(ArmEnableFiq): ASM_PFX(ArmEnableFiq):
\s\smrs R0,CPSR mrs R0,CPSR
\s\sbic R0,R0,#0x40\s\s\s\s@Enable FIQ interrupts bic R0,R0,#0x40 @Enable FIQ interrupts
\s\smsr CPSR_c,R0 msr CPSR_c,R0
\s\sbx LR bx LR
ASM_PFX(ArmDisableFiq): ASM_PFX(ArmDisableFiq):
\s\smrs R0,CPSR mrs R0,CPSR
\s\sorr R1,R0,#0x40\s\s\s\s@Disable FIQ interrupts orr R1,R0,#0x40 @Disable FIQ interrupts
\s\smsr CPSR_c,R1 msr CPSR_c,R1
tst R0,#0x80 tst R0,#0x80
moveq R0,#1 moveq R0,#1
movne R0,#0 movne R0,#0
\s\sbx LR bx LR
ASM_PFX(ArmGetFiqState): ASM_PFX(ArmGetFiqState):
\s\smrs R0,CPSR mrs R0,CPSR
\s\stst R0,#0x80\s\s @Check if FIQ is enabled. tst R0,#0x80 @Check if FIQ is enabled.
\s\smoveq R0,#1 moveq R0,#1
\s\smovne R0,#0 movne R0,#0
\s\sbx LR bx LR
ASM_PFX(ArmInvalidateTlb): ASM_PFX(ArmInvalidateTlb):
mov r0,#0 mov r0,#0

52
ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
View File

@ -48,48 +48,48 @@ ArmIsMPCore
bx LR bx LR
ArmEnableInterrupts ArmEnableInterrupts
\s\smrs R0,CPSR mrs R0,CPSR
\s\sbic R0,R0,#0x80\s\s\s\s;Enable IRQ interrupts bic R0,R0,#0x80 ;Enable IRQ interrupts
\s\smsr CPSR_c,R0 msr CPSR_c,R0
\s\sbx LR bx LR
ArmDisableInterrupts ArmDisableInterrupts
\s\smrs R0,CPSR mrs R0,CPSR
\s\sorr R1,R0,#0x80\s\s\s\s;Disable IRQ interrupts orr R1,R0,#0x80 ;Disable IRQ interrupts
\s\smsr CPSR_c,R1 msr CPSR_c,R1
tst R0,#0x80 tst R0,#0x80
moveq R0,#1 moveq R0,#1
movne R0,#0 movne R0,#0
\s\sbx LR bx LR
ArmGetInterruptState ArmGetInterruptState
\s\smrs R0,CPSR mrs R0,CPSR
\s\stst R0,#0x80\s\s ;Check if IRQ is enabled. tst R0,#0x80 ;Check if IRQ is enabled.
\s\smoveq R0,#1 moveq R0,#1
\s\smovne R0,#0 movne R0,#0
\s\sbx LR bx LR
ArmEnableFiq ArmEnableFiq
\s\smrs R0,CPSR mrs R0,CPSR
\s\sbic R0,R0,#0x40\s\s\s\s;Enable IRQ interrupts bic R0,R0,#0x40 ;Enable IRQ interrupts
\s\smsr CPSR_c,R0 msr CPSR_c,R0
\s\sbx LR bx LR
ArmDisableFiq ArmDisableFiq
\s\smrs R0,CPSR mrs R0,CPSR
\s\sorr R1,R0,#0x40\s\s\s\s;Disable IRQ interrupts orr R1,R0,#0x40 ;Disable IRQ interrupts
\s\smsr CPSR_c,R1 msr CPSR_c,R1
tst R0,#0x40 tst R0,#0x40
moveq R0,#1 moveq R0,#1
movne R0,#0 movne R0,#0
\s\sbx LR bx LR
ArmGetFiqState ArmGetFiqState
\s\smrs R0,CPSR mrs R0,CPSR
\s\stst R0,#0x40\s\s ;Check if IRQ is enabled. tst R0,#0x40 ;Check if IRQ is enabled.
\s\smoveq R0,#1 moveq R0,#1
\s\smovne R0,#0 movne R0,#0
\s\sbx LR bx LR
ArmInvalidateTlb ArmInvalidateTlb
mov r0,#0 mov r0,#0

2
ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c
View File

@ -17,7 +17,7 @@
#include <Library/IoLib.h> #include <Library/IoLib.h>
VOID ArmClearMPCoreMailbox() { VOID ArmClearMPCoreMailbox() {
\s\sMmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue)); MmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue));
} }
UINTN ArmGetMPCoreMailbox() { UINTN ArmGetMPCoreMailbox() {

4
ArmPkg/Library/ArmTrustZoneLib/ArmTrustZone.c
View File

@ -72,8 +72,8 @@ EFI_STATUS TZASCSetRegion(UINTN TzascBase, UINTN RegionId, UINTN Enabled, UINTN
Region = (UINT32*)((UINTN)TzascBase + TZASC_REGIONS_REG + (RegionId * 0x10)); Region = (UINT32*)((UINTN)TzascBase + TZASC_REGIONS_REG + (RegionId * 0x10));
MmioWrite32((UINTN)(Region), LowAddress&0xFFFF8000); MmioWrite32((UINTN)(Region), LowAddress&0xFFFF8000);
\s\sMmioWrite32((UINTN)(Region+1), HighAddress); MmioWrite32((UINTN)(Region+1), HighAddress);
\s\sMmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & 0x3F) << 1) | (Enabled & 0x1)); MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & 0x3F) << 1) | (Enabled & 0x1));
return EFI_SUCCESS; return EFI_SUCCESS;
} }

120
ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.S
View File

@ -42,71 +42,71 @@ InternalMemCopyMem (
GCC_ASM_EXPORT(InternalMemCopyMem) GCC_ASM_EXPORT(InternalMemCopyMem)
ASM_PFX(InternalMemCopyMem): ASM_PFX(InternalMemCopyMem):
\s\sstmfd\s\ssp!, {r4-r11, lr} stmfd sp!, {r4-r11, lr}
\s\stst\s\sr0, #3 tst r0, #3
\s\smov\s\sr11, r0 mov r11, r0
\s\smov\s\sr10, r0 mov r10, r0
\s\smov\s\sip, r2 mov ip, r2
\s\smov\s\slr, r1 mov lr, r1
\s\smovne\s\sr0, #0 movne r0, #0
\s\sbne\s\sL4 bne L4
\s\stst\s\sr1, #3 tst r1, #3
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #1 moveq r3, #1
\s\scmp\s\sr2, #31 cmp r2, #31
\s\smovls\s\sr0, #0 movls r0, #0
\s\sandhi\s\sr0, r3, #1 andhi r0, r3, #1
L4: L4:
\s\scmp\s\sr11, r1 cmp r11, r1
\s\sbcc\s\sL26 bcc L26
\s\sbls\s\sL7 bls L7
\s\srsb\s\sr3, r1, r11 rsb r3, r1, r11
\s\scmp\s\sip, r3 cmp ip, r3
\s\sbcc\s\sL26 bcc L26
\s\scmp\s\sip, #0 cmp ip, #0
\s\sbeq\s\sL7 beq L7
\s\sadd\s\sr10, r11, ip add r10, r11, ip
\s\sadd\s\slr, ip, r1 add lr, ip, r1
\s\sb\s\sL16 b L16
L29: L29:
\s\ssub\s\sip, ip, #8 sub ip, ip, #8
\s\scmp\s\sip, #7 cmp ip, #7
\s\sldrd\s\sr2, [lr, #-8]! ldrd r2, [lr, #-8]!
\s\smovls\s\sr0, #0 movls r0, #0
\s\scmp\s\sip, #0 cmp ip, #0
\s\sstrd\s\sr2, [r10, #-8]! strd r2, [r10, #-8]!
\s\sbeq\s\sL7 beq L7
L16: L16:
\s\scmp\s\sr0, #0 cmp r0, #0
\s\sbne\s\sL29 bne L29
\s\ssub\s\sr3, lr, #1 sub r3, lr, #1
\s\ssub\s\sip, ip, #1 sub ip, ip, #1
\s\sldrb\s\sr3, [r3, #0]\s\s ldrb r3, [r3, #0]
\s\ssub\s\sr2, r10, #1 sub r2, r10, #1
\s\scmp\s\sip, #0 cmp ip, #0
\s\ssub\s\sr10, r10, #1 sub r10, r10, #1
\s\ssub\s\slr, lr, #1 sub lr, lr, #1
\s\sstrb\s\sr3, [r2, #0] strb r3, [r2, #0]
\s\sbne\s\sL16 bne L16
\s\sb L7 b L7
L11: L11:
\s\sldrb\s\sr3, [lr], #1\s\s ldrb r3, [lr], #1
\s\ssub\s\sip, ip, #1 sub ip, ip, #1
\s\sstrb\s\sr3, [r10], #1 strb r3, [r10], #1
L26: L26:
\s\scmp\s\sip, #0 cmp ip, #0
\s\sbeq\s\sL7 beq L7
L30: L30:
\s\scmp\s\sr0, #0 cmp r0, #0
\s\sbeq\s\sL11 beq L11
\s\ssub\s\sip, ip, #32 sub ip, ip, #32
\s\scmp\s\sip, #31 cmp ip, #31
\s\sldmia\s\slr!, {r2-r9} ldmia lr!, {r2-r9}
\s\smovls\s\sr0, #0 movls r0, #0
\s\scmp\s\sip, #0 cmp ip, #0
\s\sstmia\s\sr10!, {r2-r9} stmia r10!, {r2-r9}
\s\sbne\s\sL30 bne L30
L7: L7:
mov\s\sr0, r11 mov r0, r11
\s\sldmfd\s\ssp!, {r4-r11, pc} ldmfd sp!, {r4-r11, pc}

126
ArmPkg/Library/BaseMemoryLibStm/Arm/CopyMem.asm
View File

@ -37,78 +37,78 @@ InternalMemCopyMem (
IN UINTN Length IN UINTN Length
) )
**/ **/
\s\sEXPORT InternalMemCopyMem EXPORT InternalMemCopyMem
\s\sAREA AsmMemStuff, CODE, READONLY AREA AsmMemStuff, CODE, READONLY
InternalMemCopyMem InternalMemCopyMem
\s\sstmfd\s\ssp!, {r4-r11, lr} stmfd sp!, {r4-r11, lr}
\s\stst\s\sr0, #3 tst r0, #3
\s\smov\s\sr11, r0 mov r11, r0
\s\smov\s\sr10, r0 mov r10, r0
\s\smov\s\sip, r2 mov ip, r2
\s\smov\s\slr, r1 mov lr, r1
\s\smovne\s\sr0, #0 movne r0, #0
\s\sbne\s\sL4 bne L4
\s\stst\s\sr1, #3 tst r1, #3
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #1 moveq r3, #1
\s\scmp\s\sr2, #31 cmp r2, #31
\s\smovls\s\sr0, #0 movls r0, #0
\s\sandhi\s\sr0, r3, #1 andhi r0, r3, #1
L4 L4
\s\scmp\s\sr11, r1 cmp r11, r1
\s\sbcc\s\sL26 bcc L26
\s\sbls\s\sL7 bls L7
\s\srsb\s\sr3, r1, r11 rsb r3, r1, r11
\s\scmp\s\sip, r3 cmp ip, r3
\s\sbcc\s\sL26 bcc L26
\s\scmp\s\sip, #0 cmp ip, #0
\s\sbeq\s\sL7 beq L7
\s\sadd\s\sr10, r11, ip add r10, r11, ip
\s\sadd\s\slr, ip, r1 add lr, ip, r1
\s\sb\s\sL16 b L16
L29 L29
\s\ssub\s\sip, ip, #8 sub ip, ip, #8
\s\scmp\s\sip, #7 cmp ip, #7
\s\sldrd\s\sr2, [lr, #-8]! ldrd r2, [lr, #-8]!
\s\smovls\s\sr0, #0 movls r0, #0
\s\scmp\s\sip, #0 cmp ip, #0
\s\sstrd\s\sr2, [r10, #-8]! strd r2, [r10, #-8]!
\s\sbeq\s\sL7 beq L7
L16 L16
\s\scmp\s\sr0, #0 cmp r0, #0
\s\sbne\s\sL29 bne L29
\s\ssub\s\sr3, lr, #1 sub r3, lr, #1
\s\ssub\s\sip, ip, #1 sub ip, ip, #1
\s\sldrb\s\sr3, [r3, #0]\s\s ldrb r3, [r3, #0]
\s\ssub\s\sr2, r10, #1 sub r2, r10, #1
\s\scmp\s\sip, #0 cmp ip, #0
\s\ssub\s\sr10, r10, #1 sub r10, r10, #1
\s\ssub\s\slr, lr, #1 sub lr, lr, #1
\s\sstrb\s\sr3, [r2, #0] strb r3, [r2, #0]
\s\sbne\s\sL16 bne L16
\s\sb L7 b L7
L11 L11
\s\sldrb\s\sr3, [lr], #1\s\s ldrb r3, [lr], #1
\s\ssub\s\sip, ip, #1 sub ip, ip, #1
\s\sstrb\s\sr3, [r10], #1 strb r3, [r10], #1
L26 L26
\s\scmp\s\sip, #0 cmp ip, #0
\s\sbeq\s\sL7 beq L7
L30 L30
\s\scmp\s\sr0, #0 cmp r0, #0
\s\sbeq\s\sL11 beq L11
\s\ssub\s\sip, ip, #32 sub ip, ip, #32
\s\scmp\s\sip, #31 cmp ip, #31
\s\sldmia\s\slr!, {r2-r9} ldmia lr!, {r2-r9}
\s\smovls\s\sr0, #0 movls r0, #0
\s\scmp\s\sip, #0 cmp ip, #0
\s\sstmia\s\sr10!, {r2-r9} stmia r10!, {r2-r9}
\s\sbne\s\sL30 bne L30
L7 L7
mov\s\sr0, r11 mov r0, r11
\s\sldmfd\s\ssp!, {r4-r11, pc} ldmfd sp!, {r4-r11, pc}
\s\s
END END

68
ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.S
View File

@ -34,49 +34,49 @@ InternalMemSetMem (
IN UINT8 Value IN UINT8 Value
) )
**/ **/
\s\s
.text .text
.align 2 .align 2
GCC_ASM_EXPORT(InternalMemSetMem) GCC_ASM_EXPORT(InternalMemSetMem)
ASM_PFX(InternalMemSetMem): ASM_PFX(InternalMemSetMem):
\s\sstmfd\s\ssp!, {r4-r11, lr} stmfd sp!, {r4-r11, lr}
\s\stst\s\s r0, #3 tst r0, #3
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #1 moveq r3, #1
\s\scmp\s\s r1, #31 cmp r1, #31
\s\smovls lr, #0 movls lr, #0
\s\sandhi\s\slr, r3, #1 andhi lr, r3, #1
\s\scmp\s\s lr, #0 cmp lr, #0
\s\smov\s\s r12, r0 mov r12, r0
\s\sbne\s\s L31 bne L31
L32: L32:
\s\smov\s\s r3, #0 mov r3, #0
\s\sb\s\s L43 b L43
L31: L31:
and r4, r2, #0xff and r4, r2, #0xff
orr r4, r4, r4, LSL #8 orr r4, r4, r4, LSL #8
orr r4, r4, r4, LSL #16 orr r4, r4, r4, LSL #16
\s\smov r5, r4 mov r5, r4
\s\smov r5, r4 mov r5, r4
\s\smov r6, r4 mov r6, r4
\s\smov r7, r4 mov r7, r4
\s\smov r8, r4 mov r8, r4
\s\smov r9, r4 mov r9, r4
\s\smov r10, r4 mov r10, r4
\s\smov r11, r4 mov r11, r4
\s\sb\s\s L32 b L32
L34: L34:
\s\scmp\s\s lr, #0 cmp lr, #0
\s\sstreqb\s\sr2, [r12], #1 streqb r2, [r12], #1
\s\ssubeq\s\s r1, r1, #1 subeq r1, r1, #1
\s\sbeq\s\s L43 beq L43
\s\ssub\s\s r1, r1, #32 sub r1, r1, #32
\s\scmp\s\s r1, #31 cmp r1, #31
\s\smovls\s\s lr, r3 movls lr, r3
\s\sstmia\s\s r12!, {r4-r11} stmia r12!, {r4-r11}
L43: L43:
\s\scmp\s\s r1, #0 cmp r1, #0
\s\sbne\s\s L34 bne L34
\s\sldmfd\s\s sp!, {r4-r11, pc} ldmfd sp!, {r4-r11, pc}
\s\s

74
ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm
View File

@ -33,51 +33,51 @@ InternalMemSetMem (
IN UINT8 Value IN UINT8 Value
) )
**/ **/
\s\s
\s\sEXPORT InternalMemSetMem EXPORT InternalMemSetMem
\s\s
\s\sAREA AsmMemStuff, CODE, READONLY AREA AsmMemStuff, CODE, READONLY
InternalMemSetMem InternalMemSetMem
\s\sstmfd\s\ssp!, {r4-r11, lr} stmfd sp!, {r4-r11, lr}
\s\stst\s\s r0, #3 tst r0, #3
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #1 moveq r3, #1
\s\scmp\s\s r1, #31 cmp r1, #31
\s\smovls lr, #0 movls lr, #0
\s\sandhi\s\slr, r3, #1 andhi lr, r3, #1
\s\scmp\s\s lr, #0 cmp lr, #0
\s\smov\s\s r12, r0 mov r12, r0
\s\sbne\s\s L31 bne L31
L32 L32
\s\smov\s\s r3, #0 mov r3, #0
\s\sb\s\s L43 b L43
L31 L31
and r4, r2, #0xff and r4, r2, #0xff
orr r4, r4, r4, LSL #8 orr r4, r4, r4, LSL #8
orr r4, r4, r4, LSL #16 orr r4, r4, r4, LSL #16
\s\smov r5, r4 mov r5, r4
\s\smov r5, r4 mov r5, r4
\s\smov r6, r4 mov r6, r4
\s\smov r7, r4 mov r7, r4
\s\smov r8, r4 mov r8, r4
\s\smov r9, r4 mov r9, r4
\s\smov r10, r4 mov r10, r4
\s\smov r11, r4 mov r11, r4
\s\sb\s\s L32 b L32
L34 L34
\s\scmp\s\s lr, #0 cmp lr, #0
\s\sstreqb\s\sr2, [r12], #1 streqb r2, [r12], #1
\s\ssubeq\s\s r1, r1, #1 subeq r1, r1, #1
\s\sbeq\s\s L43 beq L43
\s\ssub\s\s r1, r1, #32 sub r1, r1, #32
\s\scmp\s\s r1, #31 cmp r1, #31
\s\smovls\s\s lr, r3 movls lr, r3
\s\sstmia\s\s r12!, {r4-r11} stmia r12!, {r4-r11}
L43 L43
\s\scmp\s\s r1, #0 cmp r1, #0
\s\sbne\s\s L34 bne L34
\s\sldmfd\s\s sp!, {r4-r11, pc} ldmfd sp!, {r4-r11, pc}
\s\s
END END

120
ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.S
View File

@ -42,73 +42,73 @@ InternalMemCopyMem (
GCC_ASM_EXPORT(InternalMemCopyMem) GCC_ASM_EXPORT(InternalMemCopyMem)
ASM_PFX(InternalMemCopyMem): ASM_PFX(InternalMemCopyMem):
\s\sstmfd\s\ssp!, {r4, r9, lr} stmfd sp!, {r4, r9, lr}
\s\stst\s\sr0, #3 tst r0, #3
\s\smov\s\sr4, r0 mov r4, r0
\s\smov\s\sr9, r0 mov r9, r0
\s\smov\s\sip, r2 mov ip, r2
\s\smov\s\slr, r1 mov lr, r1
\s\smovne\s\sr0, #0 movne r0, #0
\s\sbne\s\sL4 bne L4
\s\stst\s\sr1, #3 tst r1, #3
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #1 moveq r3, #1
\s\scmp\s\sr2, #127 cmp r2, #127
\s\smovls\s\sr0, #0 movls r0, #0
\s\sandhi\s\sr0, r3, #1 andhi r0, r3, #1
L4: L4:
\s\scmp\s\sr4, r1 cmp r4, r1
\s\sbcc\s\sL26 bcc L26
\s\sbls\s\sL7 bls L7
\s\srsb\s\sr3, r1, r4 rsb r3, r1, r4
\s\scmp\s\sip, r3 cmp ip, r3
\s\sbcc\s\sL26 bcc L26
\s\scmp\s\sip, #0 cmp ip, #0
\s\sbeq\s\sL7 beq L7
\s\sadd\s\sr9, r4, ip add r9, r4, ip
\s\sadd\s\slr, ip, r1 add lr, ip, r1
\s\sb\s\sL16 b L16
L29: L29:
\s\ssub\s\sip, ip, #8 sub ip, ip, #8
\s\scmp\s\sip, #7 cmp ip, #7
\s\sldrd\s\sr2, [lr, #-8]! ldrd r2, [lr, #-8]!
\s\smovls\s\sr0, #0 movls r0, #0
\s\scmp\s\sip, #0 cmp ip, #0
\s\sstrd\s\sr2, [r9, #-8]! strd r2, [r9, #-8]!
\s\sbeq\s\sL7 beq L7
L16: L16:
\s\scmp\s\sr0, #0 cmp r0, #0
\s\sbne\s\sL29 bne L29
\s\ssub\s\sr3, lr, #1 sub r3, lr, #1
\s\ssub\s\sip, ip, #1 sub ip, ip, #1
\s\sldrb\s\sr3, [r3, #0]\s\s ldrb r3, [r3, #0]
\s\ssub\s\sr2, r9, #1 sub r2, r9, #1
\s\scmp\s\sip, #0 cmp ip, #0
\s\ssub\s\sr9, r9, #1 sub r9, r9, #1
\s\ssub\s\slr, lr, #1 sub lr, lr, #1
\s\sstrb\s\sr3, [r2, #0] strb r3, [r2, #0]
\s\sbne\s\sL16 bne L16
\s\sb L7 b L7
L11: L11:
\s\sldrb\s\sr3, [lr], #1\s\s ldrb r3, [lr], #1
\s\ssub\s\sip, ip, #1 sub ip, ip, #1
\s\sstrb\s\sr3, [r9], #1 strb r3, [r9], #1
L26: L26:
\s\scmp\s\sip, #0 cmp ip, #0
\s\sbeq\s\sL7 beq L7
L30: L30:
\s\scmp\s\sr0, #0 cmp r0, #0
\s\sbeq\s\sL11 beq L11
\s\ssub\s\sip, ip, #128 // 32 sub ip, ip, #128 // 32
\s\scmp\s\sip, #127 // 31 cmp ip, #127 // 31
\s\svldm lr!, {d0-d15} vldm lr!, {d0-d15}
\s\smovls\s\sr0, #0 movls r0, #0
\s\scmp\s\sip, #0 cmp ip, #0
\s\svstm r9!, {d0-d15} vstm r9!, {d0-d15}
\s\sbne\s\sL30 bne L30
L7: L7:
dsb dsb
mov\s\sr0, r4 mov r0, r4
\s\sldmfd\s\ssp!, {r4, r9, pc} ldmfd sp!, {r4, r9, pc}

124
ArmPkg/Library/BaseMemoryLibVstm/Arm/CopyMem.asm
View File

@ -37,79 +37,79 @@ InternalMemCopyMem (
IN UINTN Length IN UINTN Length
) )
**/ **/
\s\sEXPORT InternalMemCopyMem EXPORT InternalMemCopyMem
\s\sAREA AsmMemStuff, CODE, READONLY AREA AsmMemStuff, CODE, READONLY
InternalMemCopyMem InternalMemCopyMem
\s\sstmfd\s\ssp!, {r4, r9, lr} stmfd sp!, {r4, r9, lr}
\s\stst\s\sr0, #3 tst r0, #3
\s\smov\s\sr4, r0 mov r4, r0
\s\smov\s\sr9, r0 mov r9, r0
\s\smov\s\sip, r2 mov ip, r2
\s\smov\s\slr, r1 mov lr, r1
\s\smovne\s\sr0, #0 movne r0, #0
\s\sbne\s\sL4 bne L4
\s\stst\s\sr1, #3 tst r1, #3
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #1 moveq r3, #1
\s\scmp\s\sr2, #127 cmp r2, #127
\s\smovls\s\sr0, #0 movls r0, #0
\s\sandhi\s\sr0, r3, #1 andhi r0, r3, #1
L4 L4
\s\scmp\s\sr4, r1 cmp r4, r1
\s\sbcc\s\sL26 bcc L26
\s\sbls\s\sL7 bls L7
\s\srsb\s\sr3, r1, r4 rsb r3, r1, r4
\s\scmp\s\sip, r3 cmp ip, r3
\s\sbcc\s\sL26 bcc L26
\s\scmp\s\sip, #0 cmp ip, #0
\s\sbeq\s\sL7 beq L7
\s\sadd\s\sr9, r4, ip add r9, r4, ip
\s\sadd\s\slr, ip, r1 add lr, ip, r1
\s\sb\s\sL16 b L16
L29 L29
\s\ssub\s\sip, ip, #8 sub ip, ip, #8
\s\scmp\s\sip, #7 cmp ip, #7
\s\sldrd\s\sr2, [lr, #-8]! ldrd r2, [lr, #-8]!
\s\smovls\s\sr0, #0 movls r0, #0
\s\scmp\s\sip, #0 cmp ip, #0
\s\sstrd\s\sr2, [r9, #-8]! strd r2, [r9, #-8]!
\s\sbeq\s\sL7 beq L7
L16 L16
\s\scmp\s\sr0, #0 cmp r0, #0
\s\sbne\s\sL29 bne L29
\s\ssub\s\sr3, lr, #1 sub r3, lr, #1
\s\ssub\s\sip, ip, #1 sub ip, ip, #1
\s\sldrb\s\sr3, [r3, #0]\s\s ldrb r3, [r3, #0]
\s\ssub\s\sr2, r9, #1 sub r2, r9, #1
\s\scmp\s\sip, #0 cmp ip, #0
\s\ssub\s\sr9, r9, #1 sub r9, r9, #1
\s\ssub\s\slr, lr, #1 sub lr, lr, #1
\s\sstrb\s\sr3, [r2, #0] strb r3, [r2, #0]
\s\sbne\s\sL16 bne L16
\s\sb L7 b L7
L11 L11
\s\sldrb\s\sr3, [lr], #1\s\s ldrb r3, [lr], #1
\s\ssub\s\sip, ip, #1 sub ip, ip, #1
\s\sstrb\s\sr3, [r9], #1 strb r3, [r9], #1
L26 L26
\s\scmp\s\sip, #0 cmp ip, #0
\s\sbeq\s\sL7 beq L7
L30 L30
\s\scmp\s\sr0, #0 cmp r0, #0
\s\sbeq\s\sL11 beq L11
\s\ssub\s\sip, ip, #128 // 32 sub ip, ip, #128 // 32
\s\scmp\s\sip, #127 // 31 cmp ip, #127 // 31
\s\svldm lr!, {d0-d15} vldm lr!, {d0-d15}
\s\smovls\s\sr0, #0 movls r0, #0
\s\scmp\s\sip, #0 cmp ip, #0
\s\svstm r9!, {d0-d15} vstm r9!, {d0-d15}
\s\sbne\s\sL30 bne L30
L7 L7
dsb dsb
mov\s\sr0, r4 mov r0, r4
\s\sldmfd\s\ssp!, {r4, r9, pc} ldmfd sp!, {r4, r9, pc}
END END

54
ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.S
View File

@ -34,25 +34,25 @@ InternalMemSetMem (
IN UINT8 Value IN UINT8 Value
) )
**/ **/
\s\s
.text .text
.align 2 .align 2
GCC_ASM_EXPORT(InternalMemSetMem) GCC_ASM_EXPORT(InternalMemSetMem)
ASM_PFX(InternalMemSetMem): ASM_PFX(InternalMemSetMem):
\s\sstmfd\s\ssp!, {r4-r7, lr} stmfd sp!, {r4-r7, lr}
\s\stst\s\s r0, #3 tst r0, #3
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #1 moveq r3, #1
\s\scmp\s\s r1, #127 cmp r1, #127
\s\smovls lr, #0 movls lr, #0
\s\sandhi\s\slr, r3, #1 andhi lr, r3, #1
\s\scmp\s\s lr, #0 cmp lr, #0
\s\smov\s\s r12, r0 mov r12, r0
\s\sbne\s\s L31 bne L31
L32: L32:
\s\smov\s\s r3, #0 mov r3, #0
\s\sb\s\s L43 b L43
L31: L31:
vdup.8 q0,r2 vdup.8 q0,r2
vmov q1,q0 vmov q1,q0
@ -62,19 +62,19 @@ L31:
vmov q5,q0 vmov q5,q0
vmov q6,q0 vmov q6,q0
vmov q7,q0 vmov q7,q0
\s\sb\s\s L32 b L32
L34: L34:
\s\scmp\s\s lr, #0 cmp lr, #0
\s\sstreqb\s\sr2, [r12], #1 streqb r2, [r12], #1
\s\ssubeq\s\s r1, r1, #1 subeq r1, r1, #1
\s\sbeq\s\s L43 beq L43
\s\ssub\s\s r1, r1, #128 sub r1, r1, #128
\s\scmp\s\s r1, #127 cmp r1, #127
\s\scmp\s\s r1, #31 cmp r1, #31
\s\smovls\s\s lr, r3 movls lr, r3
\s\svstm r12!, {d0-d15} vstm r12!, {d0-d15}
L43: L43:
\s\scmp\s\s r1, #0 cmp r1, #0
\s\sbne\s\s L34 bne L34
\s\sldmfd\s\s sp!, {pc} ldmfd sp!, {pc}
\s\s

58
ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm
View File

@ -33,25 +33,25 @@ InternalMemSetMem (
IN UINT8 Value IN UINT8 Value
) )
**/ **/
\s\s
\s\sEXPORT InternalMemSetMem EXPORT InternalMemSetMem
\s\s
\s\sAREA AsmMemStuff, CODE, READONLY AREA AsmMemStuff, CODE, READONLY
InternalMemSetMem InternalMemSetMem
\s\sstmfd\s\ssp!, {lr} stmfd sp!, {lr}
\s\stst\s\s r0, #3 tst r0, #3
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #1 moveq r3, #1
\s\scmp\s\s r1, #127 cmp r1, #127
\s\smovls lr, #0 movls lr, #0
\s\sandhi\s\slr, r3, #1 andhi lr, r3, #1
\s\scmp\s\s lr, #0 cmp lr, #0
\s\smov\s\s r12, r0 mov r12, r0
\s\sbne\s\s L31 bne L31
L32 L32
\s\smov\s\s r3, #0 mov r3, #0
\s\sb\s\s L43 b L43
L31 L31
vdup.8 q0,r2 vdup.8 q0,r2
vmov q1,q0 vmov q1,q0
@ -61,20 +61,20 @@ L31
vmov q5,q0 vmov q5,q0
vmov q6,q0 vmov q6,q0
vmov q7,q0 vmov q7,q0
\s\sb\s\s L32 b L32
L34 L34
\s\scmp\s\s lr, #0 cmp lr, #0
\s\sstreqb\s\sr2, [r12], #1 streqb r2, [r12], #1
\s\ssubeq\s\s r1, r1, #1 subeq r1, r1, #1
\s\sbeq\s\s L43 beq L43
\s\ssub\s\s r1, r1, #128 sub r1, r1, #128
\s\scmp\s\s r1, #127 cmp r1, #127
\s\smovls\s\s lr, r3 movls lr, r3
\s\svstm r12!, {d0-d15} vstm r12!, {d0-d15}
L43 L43
\s\scmp\s\s r1, #0 cmp r1, #0
\s\sbne\s\s L34 bne L34
\s\sldmfd\s\s sp!, {pc} ldmfd sp!, {pc}
\s\s
END END

4
ArmPkg/Library/BdsLib/BdsFilePathFs.c
View File

@ -34,8 +34,8 @@ EFI_STATUS BdsLoadFileFromSimpleFileSystem(
} }
//Try to Open the volume and get root directory //Try to Open the volume and get root directory
\s\sStatus = FsProtocol->OpenVolume(FsProtocol, &Fs); Status = FsProtocol->OpenVolume(FsProtocol, &Fs);
\s\sif (EFI_ERROR(Status)) { if (EFI_ERROR(Status)) {
return Status; return Status;
} }

38
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
View File

@ -12,24 +12,24 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__ashldi3) GCC_ASM_EXPORT(__ashldi3)
\s\s
ASM_PFX(__ashldi3): ASM_PFX(__ashldi3):
\s\scmp\s\sr2, #31 cmp r2, #31
\s\sbls\s\sL2 bls L2
\s\scmp\s\sr2, #63 cmp r2, #63
\s\ssubls\s\sr2, r2, #32 subls r2, r2, #32
\s\smovls\s\sr2, r0, asl r2 movls r2, r0, asl r2
\s\smovhi\s\sr2, #0 movhi r2, #0
\s\smov\s\sr1, r2 mov r1, r2
\s\smov\s\sr0, #0 mov r0, #0
\s\sbx\s\slr bx lr
L2: L2:
\s\scmp\s\sr2, #0 cmp r2, #0
\s\srsbne\s\sr3, r2, #32 rsbne r3, r2, #32
\s\smovne\s\sr3, r0, lsr r3 movne r3, r0, lsr r3
\s\smovne\s\sr0, r0, asl r2 movne r0, r0, asl r2
\s\sorrne\s\sr1, r3, r1, asl r2 orrne r1, r3, r1, asl r2
\s\sbx\s\slr bx lr

38
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
View File

@ -12,25 +12,25 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__ashrdi3) GCC_ASM_EXPORT(__ashrdi3)
ASM_PFX(__ashrdi3): ASM_PFX(__ashrdi3):
\s\scmp\s\sr2, #31 cmp r2, #31
\s\sbls\s\sL2 bls L2
\s\scmp\s\sr2, #63 cmp r2, #63
\s\ssubls\s\sr2, r2, #32 subls r2, r2, #32
\s\smov\s\sip, r1, asr #31 mov ip, r1, asr #31
\s\smovls\s\sr2, r1, asr r2 movls r2, r1, asr r2
\s\smovhi\s\sr2, ip movhi r2, ip
\s\smov\s\sr0, r2 mov r0, r2
\s\smov\s\sr1, ip mov r1, ip
\s\sbx\s\slr bx lr
L2: L2:
\s\scmp\s\sr2, #0 cmp r2, #0
\s\srsbne\s\sr3, r2, #32 rsbne r3, r2, #32
\s\smovne\s\sr3, r1, asl r3 movne r3, r1, asl r3
\s\smovne\s\sr1, r1, asr r2 movne r1, r1, asr r2
\s\sorrne\s\sr0, r3, r0, lsr r2 orrne r0, r3, r0, lsr r2
\s\sbx\s\slr bx lr

82
ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S
View File

@ -12,46 +12,46 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__clzsi2) GCC_ASM_EXPORT(__clzsi2)
ASM_PFX(__clzsi2): ASM_PFX(__clzsi2):
\s\s@ frame_needed = 1, uses_anonymous_args = 0 @ frame_needed = 1, uses_anonymous_args = 0
\s\sstmfd\s\ssp!, {r7, lr} stmfd sp!, {r7, lr}
\s\sadd\s\sr7, sp, #0 add r7, sp, #0
\s\smovs\s\sr3, r0, lsr #16 movs r3, r0, lsr #16
\s\smovne\s\sr3, #16 movne r3, #16
\s\smoveq\s\sr3, #0 moveq r3, #0
\s\smovne\s\sr9, #0 movne r9, #0
\s\smoveq\s\sr9, #16 moveq r9, #16
\s\smov\s\sr3, r0, lsr r3 mov r3, r0, lsr r3
\s\stst\s\sr3, #65280 tst r3, #65280
\s\smovne\s\sr0, #8 movne r0, #8
\s\smoveq\s\sr0, #0 moveq r0, #0
\s\smovne\s\slr, #0 movne lr, #0
\s\smoveq\s\slr, #8 moveq lr, #8
\s\smov\s\sr3, r3, lsr r0 mov r3, r3, lsr r0
\s\stst\s\sr3, #240 tst r3, #240
\s\smovne\s\sr0, #4 movne r0, #4
\s\smoveq\s\sr0, #0 moveq r0, #0
\s\smovne\s\sip, #0 movne ip, #0
\s\smoveq\s\sip, #4 moveq ip, #4
\s\smov\s\sr3, r3, lsr r0 mov r3, r3, lsr r0
\s\stst\s\sr3, #12 tst r3, #12
\s\smovne\s\sr0, #2 movne r0, #2
\s\smoveq\s\sr0, #0 moveq r0, #0
\s\smovne\s\sr1, #0 movne r1, #0
\s\smoveq\s\sr1, #2 moveq r1, #2
\s\smov\s\sr2, r3, lsr r0 mov r2, r3, lsr r0
\s\sadd\s\sr3, lr, r9 add r3, lr, r9
\s\sadd\s\sr0, r3, ip add r0, r3, ip
\s\sadd\s\sr1, r0, r1 add r1, r0, r1
\s\smov\s\sr0, r2, lsr #1 mov r0, r2, lsr #1
\s\seor\s\sr0, r0, #1 eor r0, r0, #1
\s\sands\s\sr0, r0, #1 ands r0, r0, #1
\s\smvnne\s\sr0, #0 mvnne r0, #0
\s\srsb\s\sr3, r2, #2 rsb r3, r2, #2
\s\sand\s\sr0, r0, r3 and r0, r0, r3
\s\sadd\s\sr0, r1, r0 add r0, r1, r0
\s\sldmfd\s\ssp!, {r7, pc} ldmfd sp!, {r7, pc}

68
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S
View File

@ -12,38 +12,38 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__ctzsi2) GCC_ASM_EXPORT(__ctzsi2)
\s\s
ASM_PFX(__ctzsi2): ASM_PFX(__ctzsi2):
\s\suxth\s\sr3, r0 uxth r3, r0
\s\scmp\s\sr3, #0 cmp r3, #0
\s\smoveq\s\sip, #16 moveq ip, #16
\s\smovne\s\sip, #0 movne ip, #0
\s\s@ lr needed for prologue @ lr needed for prologue
\s\smov\s\sr0, r0, lsr ip mov r0, r0, lsr ip
\s\stst\s\sr0, #255 tst r0, #255
\s\smovne\s\sr3, #0 movne r3, #0
\s\smoveq\s\sr3, #8 moveq r3, #8
\s\smov\s\sr0, r0, lsr r3 mov r0, r0, lsr r3
\s\stst\s\sr0, #15 tst r0, #15
\s\smovne\s\sr1, #0 movne r1, #0
\s\smoveq\s\sr1, #4 moveq r1, #4
\s\sadd\s\sr3, r3, ip add r3, r3, ip
\s\smov\s\sr0, r0, lsr r1 mov r0, r0, lsr r1
\s\stst\s\sr0, #3 tst r0, #3
\s\smovne\s\sr2, #0 movne r2, #0
\s\smoveq\s\sr2, #2 moveq r2, #2
\s\sadd\s\sr3, r3, r1 add r3, r3, r1
\s\smov\s\sr0, r0, lsr r2 mov r0, r0, lsr r2
\s\sand\s\sr0, r0, #3 and r0, r0, #3
\s\sadd\s\sr2, r3, r2 add r2, r3, r2
\s\seor\s\sr3, r0, #1 eor r3, r0, #1
\s\smov\s\sr0, r0, lsr #1 mov r0, r0, lsr #1
\s\sands\s\sr3, r3, #1 ands r3, r3, #1
\s\smvnne\s\sr3, #0 mvnne r3, #0
\s\srsb\s\sr0, r0, #2 rsb r0, r0, #2
\s\sand\s\sr0, r3, r0 and r0, r3, r0
\s\sadd\s\sr0, r2, r0 add r0, r2, r0
\s\sbx\s\slr bx lr

68
ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
View File

@ -12,38 +12,38 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__divdi3) GCC_ASM_EXPORT(__divdi3)
\s\s
ASM_PFX(__divdi3): ASM_PFX(__divdi3):
\s\s@ args = 0, pretend = 0, frame = 0 @ args = 0, pretend = 0, frame = 0
\s\s@ frame_needed = 1, uses_anonymous_args = 0 @ frame_needed = 1, uses_anonymous_args = 0
\s\sstmfd\s\ssp!, {r4, r5, r7, lr} stmfd sp!, {r4, r5, r7, lr}
\s\smov\s\sr4, r3, asr #31 mov r4, r3, asr #31
\s\sadd\s\sr7, sp, #8 add r7, sp, #8
\s\sstmfd\s\ssp!, {r10, r11} stmfd sp!, {r10, r11}
\s\smov\s\sr10, r1, asr #31 mov r10, r1, asr #31
\s\ssub\s\ssp, sp, #8 sub sp, sp, #8
\s\smov\s\sr11, r10 mov r11, r10
\s\smov\s\sr5, r4 mov r5, r4
\s\seor\s\sr0, r0, r10 eor r0, r0, r10
\s\seor\s\sr1, r1, r10 eor r1, r1, r10
\s\seor\s\sr2, r2, r4 eor r2, r2, r4
\s\seor\s\sr3, r3, r4 eor r3, r3, r4
\s\ssubs\s\sr2, r2, r4 subs r2, r2, r4
\s\ssbc\s\sr3, r3, r5 sbc r3, r3, r5
\s\smov\s\sip, #0 mov ip, #0
\s\ssubs\s\sr0, r0, r10 subs r0, r0, r10
\s\ssbc\s\sr1, r1, r11 sbc r1, r1, r11
\s\sstr\s\sip, [sp, #0] str ip, [sp, #0]
\s\sbl\s\sASM_PFX(__udivmoddi4) bl ASM_PFX(__udivmoddi4)
\s\seor\s\sr2, r10, r4 eor r2, r10, r4
\s\seor\s\sr3, r10, r4 eor r3, r10, r4
\s\seor\s\sr0, r0, r2 eor r0, r0, r2
\s\seor\s\sr1, r1, r3 eor r1, r1, r3
\s\ssubs\s\sr0, r0, r2 subs r0, r0, r2
\s\ssbc\s\sr1, r1, r3 sbc r1, r1, r3
\s\ssub\s\ssp, r7, #16 sub sp, r7, #16
\s\sldmfd\s\ssp!, {r10, r11} ldmfd sp!, {r10, r11}
\s\sldmfd\s\ssp!, {r4, r5, r7, pc} ldmfd sp!, {r4, r5, r7, pc}

34
ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
View File

@ -12,21 +12,21 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__divsi3) GCC_ASM_EXPORT(__divsi3)
\s\s
ASM_PFX(__divsi3): ASM_PFX(__divsi3):
\s\seor\s\sr3, r0, r0, asr #31 eor r3, r0, r0, asr #31
\s\seor\s\sr2, r1, r1, asr #31 eor r2, r1, r1, asr #31
\s\sstmfd\s\ssp!, {r4, r5, r7, lr} stmfd sp!, {r4, r5, r7, lr}
\s\smov\s\sr5, r0, asr #31 mov r5, r0, asr #31
\s\sadd\s\sr7, sp, #8 add r7, sp, #8
\s\smov\s\sr4, r1, asr #31 mov r4, r1, asr #31
\s\ssub\s\sr0, r3, r0, asr #31 sub r0, r3, r0, asr #31
\s\ssub\s\sr1, r2, r1, asr #31 sub r1, r2, r1, asr #31
\s\sbl\s\sASM_PFX(__udivsi3) bl ASM_PFX(__udivsi3)
\s\seor\s\sr1, r5, r4 eor r1, r5, r4
\s\seor\s\sr0, r0, r1 eor r0, r0, r1
\s\srsb\s\sr0, r1, r0 rsb r0, r1, r0
\s\sldmfd\s\ssp!, {r4, r5, r7, pc} ldmfd sp!, {r4, r5, r7, pc}

6
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S
View File

@ -13,9 +13,9 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__aeabi_ldivmod) GCC_ASM_EXPORT(__aeabi_ldivmod)
// //
// A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}}, // A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}},

38
ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
View File

@ -12,24 +12,24 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__lshrdi3) GCC_ASM_EXPORT(__lshrdi3)
\s\s
ASM_PFX(__lshrdi3): ASM_PFX(__lshrdi3):
\s\scmp\s\sr2, #31 cmp r2, #31
\s\sbls\s\sL2 bls L2
\s\scmp\s\sr2, #63 cmp r2, #63
\s\ssubls\s\sr2, r2, #32 subls r2, r2, #32
\s\smovls\s\sr2, r1, lsr r2 movls r2, r1, lsr r2
\s\smovhi\s\sr2, #0 movhi r2, #0
\s\smov\s\sr0, r2 mov r0, r2
\s\smov\s\sr1, #0 mov r1, #0
\s\sbx\s\slr bx lr
L2: L2:
\s\scmp\s\sr2, #0 cmp r2, #0
\s\srsbne\s\sr3, r2, #32 rsbne r3, r2, #32
\s\smovne\s\sr3, r1, asl r3 movne r3, r1, asl r3
\s\smovne\s\sr1, r1, lsr r2 movne r1, r1, lsr r2
\s\sorrne\s\sr0, r3, r0, lsr r2 orrne r0, r3, r0, lsr r2
\s\sbx\s\slr bx lr

30
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S
View File

@ -12,23 +12,23 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(memcpy) GCC_ASM_EXPORT(memcpy)
ASM_PFX(memcpy): ASM_PFX(memcpy):
\s\sstmfd\s\ssp!, {r7, lr} stmfd sp!, {r7, lr}
\s\smov\s\sip, #0 mov ip, #0
\s\sadd\s\sr7, sp, #0 add r7, sp, #0
\s\smov\s\slr, r0 mov lr, r0
\s\sb\s\sL4 b L4
L5: L5:
\s\sldrb\s\sr3, [r1], #1\s\s@ zero_extendqisi2 ldrb r3, [r1], #1 @ zero_extendqisi2
\s\sadd\s\sip, ip, #1 add ip, ip, #1
\s\sand\s\sr3, r3, #255 and r3, r3, #255
\s\sstrb\s\sr3, [lr], #1 strb r3, [lr], #1
L4: L4:
\s\scmp\s\sip, r2 cmp ip, r2
\s\sbne\s\sL5 bne L5
\s\sldmfd\s\ssp!, {r7, pc} ldmfd sp!, {r7, pc}

30
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S
View File

@ -14,25 +14,25 @@
.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT (memset) GCC_ASM_EXPORT (memset)
ASM_PFX(memset): ASM_PFX(memset):
\s\s@ args = 0, pretend = 0, frame = 0 @ args = 0, pretend = 0, frame = 0
\s\s@ frame_needed = 1, uses_anonymous_args = 0 @ frame_needed = 1, uses_anonymous_args = 0
\s\sstmfd\s\ssp!, {r7, lr} stmfd sp!, {r7, lr}
\s\smov\s\sip, #0 mov ip, #0
\s\sadd\s\sr7, sp, #0 add r7, sp, #0
\s\smov\s\slr, r0 mov lr, r0
\s\sb\s\sL9 b L9
L10: L10:
\s\sand\s\sr3, r1, #255 and r3, r1, #255
\s\sadd\s\sip, ip, #1 add ip, ip, #1
\s\sstrb\s\sr3, [lr], #1 strb r3, [lr], #1
L9: L9:
\s\scmp\s\sip, r2 cmp ip, r2
\s\sbne\s\sL10 bne L10
\s\sldmfd\s\ssp!, {r7, pc} ldmfd sp!, {r7, pc}

60
ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S
View File

@ -12,35 +12,35 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__moddi3) GCC_ASM_EXPORT(__moddi3)
ASM_PFX(__moddi3): ASM_PFX(__moddi3):
\s\sstmfd\s\ssp!, {r4, r5, r7, lr} stmfd sp!, {r4, r5, r7, lr}
\s\smov\s\sr4, r1, asr #31 mov r4, r1, asr #31
\s\sadd\s\sr7, sp, #8 add r7, sp, #8
\s\sstmfd\s\ssp!, {r10, r11} stmfd sp!, {r10, r11}
\s\smov\s\sr10, r3, asr #31 mov r10, r3, asr #31
\s\ssub\s\ssp, sp, #16 sub sp, sp, #16
\s\smov\s\sr5, r4 mov r5, r4
\s\smov\s\sr11, r10 mov r11, r10
\s\seor\s\sr0, r0, r4 eor r0, r0, r4
\s\seor\s\sr1, r1, r4 eor r1, r1, r4
\s\seor\s\sr2, r2, r10 eor r2, r2, r10
\s\seor\s\sr3, r3, r10 eor r3, r3, r10
\s\sadd\s\sip, sp, #8 add ip, sp, #8
\s\ssubs\s\sr0, r0, r4 subs r0, r0, r4
\s\ssbc\s\sr1, r1, r5 sbc r1, r1, r5
\s\ssubs\s\sr2, r2, r10 subs r2, r2, r10
\s\ssbc\s\sr3, r3, r11 sbc r3, r3, r11
\s\sstr\s\sip, [sp, #0] str ip, [sp, #0]
\s\sbl\s\sASM_PFX(__udivmoddi4) bl ASM_PFX(__udivmoddi4)
\s\sldrd\s\sr0, [sp, #8] ldrd r0, [sp, #8]
\s\seor\s\sr0, r0, r4 eor r0, r0, r4
\s\seor\s\sr1, r1, r4 eor r1, r1, r4
\s\ssubs\s\sr0, r0, r4 subs r0, r0, r4
\s\ssbc\s\sr1, r1, r5 sbc r1, r1, r5
\s\ssub\s\ssp, r7, #16 sub sp, r7, #16
\s\sldmfd\s\ssp!, {r10, r11} ldmfd sp!, {r10, r11}
\s\sldmfd\s\ssp!, {r4, r5, r7, pc} ldmfd sp!, {r4, r5, r7, pc}

22
ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S
View File

@ -12,16 +12,16 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__modsi3) GCC_ASM_EXPORT(__modsi3)
ASM_PFX(__modsi3): ASM_PFX(__modsi3):
\s\sstmfd\s\ssp!, {r4, r5, r7, lr} stmfd sp!, {r4, r5, r7, lr}
\s\sadd\s\sr7, sp, #8 add r7, sp, #8
\s\smov\s\sr5, r0 mov r5, r0
\s\smov\s\sr4, r1 mov r4, r1
\s\sbl\s\s___divsi3 bl ___divsi3
\s\smul\s\sr0, r4, r0 mul r0, r4, r0
\s\srsb\s\sr0, r0, r5 rsb r0, r0, r5
\s\sldmfd\s\ssp!, {r4, r5, r7, pc} ldmfd sp!, {r4, r5, r7, pc}

80
ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S
View File

@ -12,47 +12,47 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__muldi3) GCC_ASM_EXPORT(__muldi3)
ASM_PFX(__muldi3): ASM_PFX(__muldi3):
\s\sstmfd\s\ssp!, {r4, r5, r6, r7, lr} stmfd sp!, {r4, r5, r6, r7, lr}
\s\sadd\s\sr7, sp, #12 add r7, sp, #12
\s\sstmfd\s\ssp!, {r8, r10, r11} stmfd sp!, {r8, r10, r11}
\s\sldr\s\sr11, L4 ldr r11, L4
\s\smov\s\sr4, r0, lsr #16 mov r4, r0, lsr #16
\s\sand\s\sr8, r0, r11 and r8, r0, r11
\s\sand\s\sip, r2, r11 and ip, r2, r11
\s\smul\s\slr, ip, r8 mul lr, ip, r8
\s\smul\s\sip, r4, ip mul ip, r4, ip
\s\ssub\s\ssp, sp, #8 sub sp, sp, #8
\s\sadd\s\sr10, ip, lr, lsr #16 add r10, ip, lr, lsr #16
\s\sand\s\sip, r10, r11 and ip, r10, r11
\s\sand\s\slr, lr, r11 and lr, lr, r11
\s\smov\s\sr6, r2, lsr #16 mov r6, r2, lsr #16
\s\sstr\s\sr4, [sp, #4] str r4, [sp, #4]
\s\sadd\s\sr4, lr, ip, asl #16 add r4, lr, ip, asl #16
\s\smul\s\sip, r8, r6 mul ip, r8, r6
\s\smov\s\sr5, r10, lsr #16 mov r5, r10, lsr #16
\s\sadd\s\sr10, ip, r4, lsr #16 add r10, ip, r4, lsr #16
\s\sand\s\sip, r10, r11 and ip, r10, r11
\s\sand\s\slr, r4, r11 and lr, r4, r11
\s\sadd\s\sr4, lr, ip, asl #16 add r4, lr, ip, asl #16
\s\smul\s\sr0, r3, r0 mul r0, r3, r0
\s\sadd\s\sip, r5, r10, lsr #16 add ip, r5, r10, lsr #16
\s\sldr\s\sr5, [sp, #4] ldr r5, [sp, #4]
\s\smla\s\sr0, r2, r1, r0 mla r0, r2, r1, r0
\s\smla\s\sr5, r6, r5, ip mla r5, r6, r5, ip
\s\smov\s\sr10, r4 mov r10, r4
\s\sadd\s\sr11, r0, r5 add r11, r0, r5
\s\smov\s\sr1, r11 mov r1, r11
\s\smov\s\sr0, r4 mov r0, r4
\s\ssub\s\ssp, r7, #24 sub sp, r7, #24
\s\sldmfd\s\ssp!, {r8, r10, r11} ldmfd sp!, {r8, r10, r11}
\s\sldmfd\s\ssp!, {r4, r5, r6, r7, pc} ldmfd sp!, {r4, r5, r6, r7, pc}
\s\s.p2align 2 .p2align 2
L5: L5:
\s\s.align 2 .align 2
L4: L4:
\s\s.long\s\s65535 .long 65535

4
ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm
View File

@ -13,8 +13,8 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
EXPORT\s\s__ARM_ll_mullu EXPORT __ARM_ll_mullu
EXPORT\s\s__aeabi_lmul EXPORT __aeabi_lmul
AREA Math, CODE, READONLY AREA Math, CODE, READONLY

18
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm
View File

@ -14,16 +14,16 @@
EXPORT\s\s__ARM_switch8 EXPORT __ARM_switch8
AREA ArmSwitch, CODE, READONLY
AREA\s\sArmSwitch, CODE, READONLY
\s\s
__ARM_switch8 __ARM_switch8
\s\sLDRB\s\s r12,[lr,#-1] LDRB r12,[lr,#-1]
\s\sCMP\s\s\s\s r3,r12 CMP r3,r12
\s\sLDRBCC\s\sr3,[lr,r3] LDRBCC r3,[lr,r3]
\s\sLDRBCS\s\sr3,[lr,r12] LDRBCS r3,[lr,r12]
\s\sADD\s\s\s\s r12,lr,r3,LSL #1 ADD r12,lr,r3,LSL #1
\s\sBX\s\s\s\s r12 BX r12
END END

40
ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S
View File

@ -12,27 +12,27 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__ucmpdi2) GCC_ASM_EXPORT(__ucmpdi2)
\s\s
ASM_PFX(__ucmpdi2): ASM_PFX(__ucmpdi2):
\s\sstmfd\s\ssp!, {r4, r5, r8, lr} stmfd sp!, {r4, r5, r8, lr}
\s\scmp\s\sr1, r3 cmp r1, r3
\s\smov\s\sr8, r0 mov r8, r0
\s\smov\s\sr4, r2 mov r4, r2
\s\smov\s\sr5, r3 mov r5, r3
\s\sbcc\s\sL2 bcc L2
\s\sbhi\s\sL4 bhi L4
\s\scmp\s\sr0, r2 cmp r0, r2
\s\sbcc\s\sL2 bcc L2
\s\smovls\s\sr0, #1 movls r0, #1
\s\sbls\s\sL8 bls L8
\s\sb\s\sL4 b L4
L2: L2:
\s\smov\s\sr0, #0 mov r0, #0
\s\sb\s\sL8 b L8
L4: L4:
\s\smov\s\sr0, #2 mov r0, #2
L8: L8:
\s\sldmfd\s\ssp!, {r4, r5, r8, pc} ldmfd sp!, {r4, r5, r8, pc}

22
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S
View File

@ -12,16 +12,16 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__udivdi3) GCC_ASM_EXPORT(__udivdi3)
ASM_PFX(__udivdi3): ASM_PFX(__udivdi3):
\s\sstmfd\s\ssp!, {r7, lr} stmfd sp!, {r7, lr}
\s\sadd\s\sr7, sp, #0 add r7, sp, #0
\s\ssub\s\ssp, sp, #8 sub sp, sp, #8
\s\smov\s\sip, #0 mov ip, #0
\s\sstr\s\sip, [sp, #0] str ip, [sp, #0]
\s\sbl\s\sASM_PFX(__udivmoddi4) bl ASM_PFX(__udivmoddi4)
\s\ssub\s\ssp, r7, #0 sub sp, r7, #0
\s\sldmfd\s\ssp!, {r7, pc} ldmfd sp!, {r7, pc}

412
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S
View File

@ -12,231 +12,231 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__udivmoddi4) GCC_ASM_EXPORT(__udivmoddi4)
\s\s
ASM_PFX(__udivmoddi4): ASM_PFX(__udivmoddi4):
\s\sstmfd\s\ssp!, {r4, r5, r6, r7, lr} stmfd sp!, {r4, r5, r6, r7, lr}
\s\sadd\s\sr7, sp, #12 add r7, sp, #12
\s\sstmfd\s\ssp!, {r10, r11} stmfd sp!, {r10, r11}
\s\ssub\s\ssp, sp, #20 sub sp, sp, #20
\s\sstmia\s\ssp, {r2-r3} stmia sp, {r2-r3}
\s\sldr\s\sr6, [sp, #48] ldr r6, [sp, #48]
\s\sorrs\s\sr2, r2, r3 orrs r2, r2, r3
\s\smov\s\sr10, r0 mov r10, r0
\s\smov\s\sr11, r1 mov r11, r1
\s\sbeq\s\sL2 beq L2
\s\ssubs\s\sip, r1, #0 subs ip, r1, #0
\s\sbne\s\sL4 bne L4
\s\scmp\s\sr3, #0 cmp r3, #0
\s\sbne\s\sL6 bne L6
\s\scmp\s\sr6, #0 cmp r6, #0
\s\sbeq\s\sL8 beq L8
\s\smov\s\sr1, r2 mov r1, r2
\s\sbl\s\sASM_PFX(__umodsi3) bl ASM_PFX(__umodsi3)
\s\smov\s\sr1, #0 mov r1, #0
\s\sstmia\s\sr6, {r0-r1} stmia r6, {r0-r1}
L8: L8:
\s\sldr\s\sr1, [sp, #0] ldr r1, [sp, #0]
\s\smov\s\sr0, r10 mov r0, r10
\s\sb\s\sL45 b L45
L6: L6:
\s\scmp\s\sr6, #0 cmp r6, #0
\s\smovne\s\sr1, #0 movne r1, #0
\s\sstmneia\s\sr6, {r0-r1} stmneia r6, {r0-r1}
\s\sb\s\sL2 b L2
L4: L4:
\s\sldr\s\sr1, [sp, #0] ldr r1, [sp, #0]
\s\scmp\s\sr1, #0 cmp r1, #0
\s\sbne\s\sL12 bne L12
\s\sldr\s\sr2, [sp, #4] ldr r2, [sp, #4]
\s\scmp\s\sr2, #0 cmp r2, #0
\s\sbne\s\sL14 bne L14
\s\scmp\s\sr6, #0 cmp r6, #0
\s\sbeq\s\sL16 beq L16
\s\smov\s\sr1, r2 mov r1, r2
\s\smov\s\sr0, r11 mov r0, r11
\s\sbl\s\sASM_PFX(__umodsi3) bl ASM_PFX(__umodsi3)
\s\smov\s\sr1, #0 mov r1, #0
\s\sstmia\s\sr6, {r0-r1} stmia r6, {r0-r1}
L16: L16:
\s\sldr\s\sr1, [sp, #4] ldr r1, [sp, #4]
\s\smov\s\sr0, r11 mov r0, r11
L45: L45:
\s\sbl\s\sASM_PFX(__udivsi3) bl ASM_PFX(__udivsi3)
L46: L46:
\s\smov\s\sr10, r0 mov r10, r0
\s\smov\s\sr11, #0 mov r11, #0
\s\sb\s\sL10 b L10
L14: L14:
\s\ssubs\s\sr1, r0, #0 subs r1, r0, #0
\s\sbne\s\sL18 bne L18
\s\scmp\s\sr6, #0 cmp r6, #0
\s\sbeq\s\sL16 beq L16
\s\sldr\s\sr1, [sp, #4] ldr r1, [sp, #4]
\s\smov\s\sr0, r11 mov r0, r11
\s\sbl\s\sASM_PFX(__umodsi3) bl ASM_PFX(__umodsi3)
\s\smov\s\sr4, r10 mov r4, r10
\s\smov\s\sr5, r0 mov r5, r0
\s\sstmia\s\sr6, {r4-r5} stmia r6, {r4-r5}
\s\sb\s\sL16 b L16
L18: L18:
\s\ssub\s\sr3, r2, #1 sub r3, r2, #1
\s\stst\s\sr2, r3 tst r2, r3
\s\sbne\s\sL22 bne L22
\s\scmp\s\sr6, #0 cmp r6, #0
\s\smovne\s\sr4, r0 movne r4, r0
\s\sandne\s\sr5, ip, r3 andne r5, ip, r3
\s\sstmneia\s\sr6, {r4-r5} stmneia r6, {r4-r5}
L24: L24:
\s\srsb\s\sr3, r2, #0 rsb r3, r2, #0
\s\sand\s\sr3, r2, r3 and r3, r2, r3
\s\sclz\s\sr3, r3 clz r3, r3
\s\srsb\s\sr3, r3, #31 rsb r3, r3, #31
\s\smov\s\sr0, ip, lsr r3 mov r0, ip, lsr r3
\s\sb\s\sL46 b L46
L22: L22:
\s\sclz\s\sr2, r2 clz r2, r2
\s\sclz\s\sr3, ip clz r3, ip
\s\srsb\s\sr3, r3, r2 rsb r3, r3, r2
\s\scmp\s\sr3, #30 cmp r3, #30
\s\sbhi\s\sL48 bhi L48
\s\srsb\s\sr2, r3, #31 rsb r2, r3, #31
\s\sadd\s\slr, r3, #1 add lr, r3, #1
\s\smov\s\sr3, r1, asl r2 mov r3, r1, asl r2
\s\sstr\s\sr3, [sp, #12] str r3, [sp, #12]
\s\smov\s\sr3, r1, lsr lr mov r3, r1, lsr lr
\s\sldr\s\sr0, [sp, #0] ldr r0, [sp, #0]
\s\smov\s\sr5, ip, lsr lr mov r5, ip, lsr lr
\s\sorr\s\sr4, r3, ip, asl r2 orr r4, r3, ip, asl r2
\s\sstr\s\sr0, [sp, #8] str r0, [sp, #8]
\s\sb\s\sL29 b L29
L12: L12:
\s\sldr\s\sr3, [sp, #4] ldr r3, [sp, #4]
\s\scmp\s\sr3, #0 cmp r3, #0
\s\sbne\s\sL30 bne L30
\s\ssub\s\sr3, r1, #1 sub r3, r1, #1
\s\stst\s\sr1, r3 tst r1, r3
\s\sbne\s\sL32 bne L32
\s\scmp\s\sr6, #0 cmp r6, #0
\s\sandne\s\sr3, r3, r0 andne r3, r3, r0
\s\smovne\s\sr2, r3 movne r2, r3
\s\smovne\s\sr3, #0 movne r3, #0
\s\sstmneia\s\sr6, {r2-r3} stmneia r6, {r2-r3}
L34: L34:
\s\scmp\s\sr1, #1 cmp r1, #1
\s\sbeq\s\sL10 beq L10
\s\srsb\s\sr3, r1, #0 rsb r3, r1, #0
\s\sand\s\sr3, r1, r3 and r3, r1, r3
\s\sclz\s\sr3, r3 clz r3, r3
\s\srsb\s\sr0, r3, #31 rsb r0, r3, #31
\s\smov\s\sr1, ip, lsr r0 mov r1, ip, lsr r0
\s\srsb\s\sr3, r0, #32 rsb r3, r0, #32
\s\smov\s\sr0, r10, lsr r0 mov r0, r10, lsr r0
\s\sorr\s\sip, r0, ip, asl r3 orr ip, r0, ip, asl r3
\s\sstr\s\sr1, [sp, #12] str r1, [sp, #12]
\s\sstr\s\sip, [sp, #8] str ip, [sp, #8]
\s\sldrd\s\sr10, [sp, #8] ldrd r10, [sp, #8]
\s\sb\s\sL10 b L10
L32: L32:
\s\sclz\s\sr2, r1 clz r2, r1
\s\sclz\s\sr3, ip clz r3, ip
\s\srsb\s\sr3, r3, r2 rsb r3, r3, r2
\s\srsb\s\sr4, r3, #31 rsb r4, r3, #31
\s\smov\s\sr2, r0, asl r4 mov r2, r0, asl r4
\s\smvn\s\sr1, r3 mvn r1, r3
\s\sand\s\sr2, r2, r1, asr #31 and r2, r2, r1, asr #31
\s\sadd\s\slr, r3, #33 add lr, r3, #33
\s\sstr\s\sr2, [sp, #8] str r2, [sp, #8]
\s\sadd\s\sr2, r3, #1 add r2, r3, #1
\s\smov\s\sr3, r3, asr #31 mov r3, r3, asr #31
\s\sand\s\sr0, r3, r0, asl r1 and r0, r3, r0, asl r1
\s\smov\s\sr3, r10, lsr r2 mov r3, r10, lsr r2
\s\sorr\s\sr3, r3, ip, asl r4 orr r3, r3, ip, asl r4
\s\sand\s\sr3, r3, r1, asr #31 and r3, r3, r1, asr #31
\s\sorr\s\sr0, r0, r3 orr r0, r0, r3
\s\smov\s\sr3, ip, lsr lr mov r3, ip, lsr lr
\s\sstr\s\sr0, [sp, #12] str r0, [sp, #12]
\s\smov\s\sr0, r10, lsr lr mov r0, r10, lsr lr
\s\sand\s\sr5, r3, r2, asr #31 and r5, r3, r2, asr #31
\s\srsb\s\sr3, lr, #31 rsb r3, lr, #31
\s\smov\s\sr3, r3, asr #31 mov r3, r3, asr #31
\s\sorr\s\sr0, r0, ip, asl r1 orr r0, r0, ip, asl r1
\s\sand\s\sr3, r3, ip, lsr r2 and r3, r3, ip, lsr r2
\s\sand\s\sr0, r0, r2, asr #31 and r0, r0, r2, asr #31
\s\sorr\s\sr4, r3, r0 orr r4, r3, r0
\s\sb\s\sL29 b L29
L30: L30:
\s\sclz\s\sr2, r3 clz r2, r3
\s\sclz\s\sr3, ip clz r3, ip
\s\srsb\s\sr3, r3, r2 rsb r3, r3, r2
\s\scmp\s\sr3, #31 cmp r3, #31
\s\sbls\s\sL37 bls L37
L48: L48:
\s\scmp\s\sr6, #0 cmp r6, #0
\s\sstmneia\s\sr6, {r10-r11} stmneia r6, {r10-r11}
\s\sb\s\sL2 b L2
L37: L37:
\s\srsb\s\sr1, r3, #31 rsb r1, r3, #31
\s\smov\s\sr0, r0, asl r1 mov r0, r0, asl r1
\s\sadd\s\slr, r3, #1 add lr, r3, #1
\s\smov\s\sr2, #0 mov r2, #0
\s\sstr\s\sr0, [sp, #12] str r0, [sp, #12]
\s\smov\s\sr0, r10, lsr lr mov r0, r10, lsr lr
\s\sstr\s\sr2, [sp, #8] str r2, [sp, #8]
\s\ssub\s\sr2, r3, #31 sub r2, r3, #31
\s\sand\s\sr0, r0, r2, asr #31 and r0, r0, r2, asr #31
\s\smov\s\sr3, ip, lsr lr mov r3, ip, lsr lr
\s\sorr\s\sr4, r0, ip, asl r1 orr r4, r0, ip, asl r1
\s\sand\s\sr5, r3, r2, asr #31 and r5, r3, r2, asr #31
L29: L29:
\s\smov\s\sip, #0 mov ip, #0
\s\smov\s\sr10, ip mov r10, ip
\s\sb\s\sL40 b L40
L41: L41:
\s\sldr\s\sr1, [sp, #12] ldr r1, [sp, #12]
\s\sldr\s\sr2, [sp, #8] ldr r2, [sp, #8]
\s\smov\s\sr3, r4, lsr #31 mov r3, r4, lsr #31
\s\sorr\s\sr5, r3, r5, asl #1 orr r5, r3, r5, asl #1
\s\smov\s\sr3, r1, lsr #31 mov r3, r1, lsr #31
\s\sorr\s\sr4, r3, r4, asl #1 orr r4, r3, r4, asl #1
\s\smov\s\sr3, r2, lsr #31 mov r3, r2, lsr #31
\s\sorr\s\sr0, r3, r1, asl #1 orr r0, r3, r1, asl #1
\s\sorr\s\sr1, ip, r2, asl #1 orr r1, ip, r2, asl #1
\s\sldmia\s\ssp, {r2-r3} ldmia sp, {r2-r3}
\s\sstr\s\sr0, [sp, #12] str r0, [sp, #12]
\s\ssubs\s\sr2, r2, r4 subs r2, r2, r4
\s\ssbc\s\sr3, r3, r5 sbc r3, r3, r5
\s\sstr\s\sr1, [sp, #8] str r1, [sp, #8]
\s\ssubs\s\sr0, r2, #1 subs r0, r2, #1
\s\ssbc\s\sr1, r3, #0 sbc r1, r3, #0
\s\smov\s\sr2, r1, asr #31 mov r2, r1, asr #31
\s\sldmia\s\ssp, {r0-r1} ldmia sp, {r0-r1}
\s\smov\s\sr3, r2 mov r3, r2
\s\sand\s\sip, r2, #1 and ip, r2, #1
\s\sand\s\sr3, r3, r1 and r3, r3, r1
\s\sand\s\sr2, r2, r0 and r2, r2, r0
\s\ssubs\s\sr4, r4, r2 subs r4, r4, r2
\s\ssbc\s\sr5, r5, r3 sbc r5, r5, r3
\s\sadd\s\sr10, r10, #1 add r10, r10, #1
L40: L40:
\s\scmp\s\sr10, lr cmp r10, lr
\s\sbne\s\sL41 bne L41
\s\sldrd\s\sr0, [sp, #8] ldrd r0, [sp, #8]
\s\sadds\s\sr0, r0, r0 adds r0, r0, r0
\s\sadc\s\sr1, r1, r1 adc r1, r1, r1
\s\scmp\s\sr6, #0 cmp r6, #0
\s\sorr\s\sr10, r0, ip orr r10, r0, ip
\s\smov\s\sr11, r1 mov r11, r1
\s\sstmneia\s\sr6, {r4-r5} stmneia r6, {r4-r5}
\s\sb\s\sL10 b L10
L2: L2:
\s\smov\s\sr10, #0 mov r10, #0
\s\smov\s\sr11, #0 mov r11, #0
L10: L10:
\s\smov\s\sr0, r10 mov r0, r10
\s\smov\s\sr1, r11 mov r1, r11
\s\ssub\s\ssp, r7, #20 sub sp, r7, #20
\s\sldmfd\s\ssp!, {r10, r11} ldmfd sp!, {r10, r11}
\s\sldmfd\s\ssp!, {r4, r5, r6, r7, pc} ldmfd sp!, {r4, r5, r6, r7, pc}

74
ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S
View File

@ -12,46 +12,46 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__udivsi3) GCC_ASM_EXPORT(__udivsi3)
ASM_PFX(__udivsi3): ASM_PFX(__udivsi3):
\s\scmp\s\sr1, #0 cmp r1, #0
\s\scmpne\s\sr0, #0 cmpne r0, #0
\s\sstmfd\s\ssp!, {r4, r5, r7, lr} stmfd sp!, {r4, r5, r7, lr}
\s\sadd\s\sr7, sp, #8 add r7, sp, #8
\s\sbeq\s\sL2 beq L2
\s\sclz\s\sr2, r1 clz r2, r1
\s\sclz\s\sr3, r0 clz r3, r0
\s\srsb\s\sr3, r3, r2 rsb r3, r3, r2
\s\scmp\s\sr3, #31 cmp r3, #31
\s\sbhi\s\sL2 bhi L2
\s\sldmeqfd\s\ssp!, {r4, r5, r7, pc} ldmeqfd sp!, {r4, r5, r7, pc}
\s\sadd\s\sr5, r3, #1 add r5, r3, #1
\s\srsb\s\sr3, r3, #31 rsb r3, r3, #31
\s\smov\s\slr, #0 mov lr, #0
\s\smov\s\sr2, r0, asl r3 mov r2, r0, asl r3
\s\smov\s\sip, r0, lsr r5 mov ip, r0, lsr r5
\s\smov\s\sr4, lr mov r4, lr
\s\sb\s\sL8 b L8
L9: L9:
\s\smov\s\sr0, r2, lsr #31 mov r0, r2, lsr #31
\s\sorr\s\sip, r0, ip, asl #1 orr ip, r0, ip, asl #1
\s\sorr\s\sr2, r3, lr orr r2, r3, lr
\s\srsb\s\sr3, ip, r1 rsb r3, ip, r1
\s\ssub\s\sr3, r3, #1 sub r3, r3, #1
\s\sand\s\sr0, r1, r3, asr #31 and r0, r1, r3, asr #31
\s\smov\s\slr, r3, lsr #31 mov lr, r3, lsr #31
\s\srsb\s\sip, r0, ip rsb ip, r0, ip
\s\sadd\s\sr4, r4, #1 add r4, r4, #1
L8: L8:
\s\scmp\s\sr4, r5 cmp r4, r5
\s\smov\s\sr3, r2, asl #1 mov r3, r2, asl #1
\s\sbne\s\sL9 bne L9
\s\sorr\s\sr0, r3, lr orr r0, r3, lr
\s\sldmfd\s\ssp!, {r4, r5, r7, pc} ldmfd sp!, {r4, r5, r7, pc}
L2: L2:
\s\smov\s\sr0, #0 mov r0, #0
\s\sldmfd\s\ssp!, {r4, r5, r7, pc} ldmfd sp!, {r4, r5, r7, pc}

6
ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S
View File

@ -14,9 +14,9 @@
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__aeabi_uldivmod) GCC_ASM_EXPORT(__aeabi_uldivmod)
// //
//UINT64 //UINT64

28
ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S
View File

@ -12,18 +12,18 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__umoddi3) GCC_ASM_EXPORT(__umoddi3)
\s\s
ASM_PFX(__umoddi3): ASM_PFX(__umoddi3):
\s\sstmfd\s\ssp!, {r7, lr} stmfd sp!, {r7, lr}
\s\sadd\s\sr7, sp, #0 add r7, sp, #0
\s\ssub\s\ssp, sp, #16 sub sp, sp, #16
\s\sadd\s\sip, sp, #8 add ip, sp, #8
\s\sstr\s\sip, [sp, #0] str ip, [sp, #0]
\s\sbl\s\sASM_PFX(__udivmoddi4) bl ASM_PFX(__udivmoddi4)
\s\sldrd\s\sr0, [sp, #8] ldrd r0, [sp, #8]
\s\ssub\s\ssp, r7, #0 sub sp, r7, #0
\s\sldmfd\s\ssp!, {r7, pc} ldmfd sp!, {r7, pc}

26
ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S
View File

@ -12,17 +12,17 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
\s\s.text .text
\s\s.align 2 .align 2
\s\sGCC_ASM_EXPORT(__umodsi3) GCC_ASM_EXPORT(__umodsi3)
\s\s
ASM_PFX(__umodsi3): ASM_PFX(__umodsi3):
\s\sstmfd\s\ssp!, {r4, r5, r7, lr} stmfd sp!, {r4, r5, r7, lr}
\s\sadd\s\sr7, sp, #8 add r7, sp, #8
\s\smov\s\sr5, r0 mov r5, r0
\s\smov\s\sr4, r1 mov r4, r1
\s\sbl \s\sASM_PFX(__udivsi3) bl ASM_PFX(__udivsi3)
\s\smul\s\sr0, r4, r0 mul r0, r4, r0
\s\srsb\s\sr0, r0, r5 rsb r0, r0, r5
\s\sldmfd\s\ssp!, {r4, r5, r7, pc} ldmfd sp!, {r4, r5, r7, pc}

12
ArmPkg/Universal/MmcDxe/Mmc.h
View File

@ -30,12 +30,12 @@
#define MMC_OCR_POWERUP 0x80000000 #define MMC_OCR_POWERUP 0x80000000
#define MMC_CSD_GET_CCC(Response)\s\s\s\s(Response[1] >> 20) #define MMC_CSD_GET_CCC(Response) (Response[1] >> 20)
#define MMC_CSD_GET_TRANSPEED(Response)\s\s\s\s(Response[0] & 0xFF) #define MMC_CSD_GET_TRANSPEED(Response) (Response[0] & 0xFF)
#define MMC_CSD_GET_READBLLEN(Response)\s\s\s\s((Response[1] >> 16) & 0xF) #define MMC_CSD_GET_READBLLEN(Response) ((Response[1] >> 16) & 0xF)
#define MMC_CSD_GET_WRITEBLLEN(Response)\s\s((Response[3] >> 22) & 0xF) #define MMC_CSD_GET_WRITEBLLEN(Response) ((Response[3] >> 22) & 0xF)
#define MMC_CSD_GET_FILEFORMAT(Response)\s\s((Response[3] >> 10) & 0x3) #define MMC_CSD_GET_FILEFORMAT(Response) ((Response[3] >> 10) & 0x3)
#define MMC_CSD_GET_FILEFORMATGRP(Response)\s\s((Response[3] >> 15) & 0x1) #define MMC_CSD_GET_FILEFORMATGRP(Response) ((Response[3] >> 15) & 0x1)
#define MMC_CSD_GET_DEVICESIZE(csd) (((Response[2] >> 30) & 0x3) | ((Response[1] & 0x3FF) << 2)) #define MMC_CSD_GET_DEVICESIZE(csd) (((Response[2] >> 30) & 0x3) | ((Response[1] & 0x3FF) << 2))
#define MMC_CSD_GET_DEVICESIZEMULT(csd) ((Response[2] >> 15) & 0x7) #define MMC_CSD_GET_DEVICESIZEMULT(csd) ((Response[2] >> 15) & 0x7)