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UefiCpuPkg: Use CpuPageTableLib to convert SMM paging attribute.

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Simplify the ConvertMemoryPageAttributes API to convert paging
attribute by CpuPageTableLib. In the new API, it calls
PageTableMap() to update the page attributes of a memory range.
With the PageTableMap() API in CpuPageTableLib, we can remove
the complicated page table manipulating code.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Dun Tan
2023-06-07 15:46:58 +08:00
committed by Ray Ni
parent 8c99839776
commit 2d212083d0
5 changed files with 125 additions and 329 deletions
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7
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
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@@ -1,7 +1,7 @@
/** @file
Page Fault (#PF) handler for X64 processors
Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -354,6 +354,11 @@ SmmInitPageTable (
m5LevelPagingNeeded = Is5LevelPagingNeeded ();
mPhysicalAddressBits = CalculateMaximumSupportAddress ();
PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1);
if (m5LevelPagingNeeded) {
mPagingMode = m1GPageTableSupport ? Paging5Level1GB : Paging5Level;
} else {
mPagingMode = m1GPageTableSupport ? Paging4Level1GB : Paging4Level;
}
DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", m5LevelPagingNeeded));
DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", m1GPageTableSupport));
DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", mCpuSmmRestrictedMemoryAccess));