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Fix License Header.

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Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wei, David <david.wei@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Cc: Wu, Mike <mike.wu@intel.com>
This commit is contained in:
zwei4
2017-12-25 16:30:50 +08:00
parent 56649f4301
commit 2ec099da13
4 changed files with 523 additions and 616 deletions
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128
Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
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@@ -1,69 +1,59 @@
/** @file /** @file
Header file of Serial port hardware definition. Header file of Serial port hardware definition.
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
the terms and conditions of the BSD License that accompanies this distribution. http://opensource.org/licenses/bsd-license.php.
The full text of the license may be found at THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
http://opensource.org/licenses/bsd-license.php.
**/
#ifndef __PLATFORM_SERIAL_PORT_LIB_H_
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, #define __PLATFORM_SERIAL_PORT_LIB_H_
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include <Base.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
This software and associated documentation #include <Library/SerialPortLib.h>
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as //
permitted by such license, no part of this software or // UART Register Offsets
documentation may be reproduced, stored in a retrieval system, or //
transmitted in any form or by any means without the express written #define BAUD_LOW_OFFSET 0x00
consent of Intel Corporation. #define BAUD_HIGH_OFFSET 0x01
#define IER_OFFSET 0x01
Module Name: PlatformSerialPortLib.h #define LCR_SHADOW_OFFSET 0x01
#define FCR_SHADOW_OFFSET 0x02
**/ #define IR_CONTROL_OFFSET 0x02
#define FCR_OFFSET 0x02
#ifndef __PLATFORM_SERIAL_PORT_LIB_H_ #define EIR_OFFSET 0x02
#define __PLATFORM_SERIAL_PORT_LIB_H_ #define BSR_OFFSET 0x03
#define LCR_OFFSET 0x03
#include <Base.h> #define MCR_OFFSET 0x04
#include <Library/BaseLib.h> #define LSR_OFFSET 0x05
#include <Library/IoLib.h> #define MSR_OFFSET 0x06
#include <Library/PcdLib.h>
#include <Library/SerialPortLib.h> //
// UART Register Bit Defines
// //
// UART Register Offsets #define LSR_TXRDY 0x20
// #define LSR_RXDA 0x01
#define BAUD_LOW_OFFSET 0x00 #define DLAB 0x01
#define BAUD_HIGH_OFFSET 0x01
#define IER_OFFSET 0x01 #define UART_DATA 8
#define LCR_SHADOW_OFFSET 0x01 #define UART_STOP 1
#define FCR_SHADOW_OFFSET 0x02 #define UART_PARITY 0
#define IR_CONTROL_OFFSET 0x02 #define UART_BREAK_SET 0
#define FCR_OFFSET 0x02
#define EIR_OFFSET 0x02 VOID
#define BSR_OFFSET 0x03 InitializeSio (
#define LCR_OFFSET 0x03 VOID
#define MCR_OFFSET 0x04 );
#define LSR_OFFSET 0x05
#define MSR_OFFSET 0x06 #endif
//
// UART Register Bit Defines
//
#define LSR_TXRDY 0x20
#define LSR_RXDA 0x01
#define DLAB 0x01
#define UART_DATA 8
#define UART_STOP 1

514
Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
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@@ -1,262 +1,252 @@
/** @file /** @file
Serial I/O Port library functions with no library constructor/destructor Serial I/O Port library functions with no library constructor/destructor
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
the terms and conditions of the BSD License that accompanies this distribution. http://opensource.org/licenses/bsd-license.php.
The full text of the license may be found at THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
http://opensource.org/licenses/bsd-license.php.
**/
#include "PlatformSerialPortLib.h"
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
UINT16 gComBase = 0x3f8;
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. UINTN gBps = 115200;
UINT8 gData = 8;
UINT8 gStop = 1;
UINT8 gParity = 0;
This software and associated documentation UINT8 gBreakSet = 0;
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as /**
permitted by such license, no part of this software or Initialize Serial Port
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written The Baud Rate Divisor registers are programmed and the LCR
consent of Intel Corporation. is used to configure the communications format. Hard coded
UART config comes from globals in DebugSerialPlatform lib.
Module Name: SerialPortLib.c
@param None
**/
@retval None
#include "PlatformSerialPortLib.h"
**/
UINT16 gComBase = 0x3f8; RETURN_STATUS
UINTN gBps = 115200; EFIAPI
UINT8 gData = 8; UARTInitialize (
UINT8 gStop = 1; VOID
UINT8 gParity = 0; )
UINT8 gBreakSet = 0; {
UINTN Divisor;
/** UINT8 OutputData;
Initialize Serial Port UINT8 Data;
The Baud Rate Divisor registers are programmed and the LCR //
is used to configure the communications format. Hard coded // Map 5..8 to 0..3
UART config comes from globals in DebugSerialPlatform lib. //
Data = (UINT8) (gData - (UINT8) 5);
@param None
//
@retval None // Calculate divisor for baud generator
//
**/ Divisor = 115200 / gBps;
RETURN_STATUS
EFIAPI //
UARTInitialize ( // Set communications format
VOID //
) OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
{ IoWrite8 (gComBase + LCR_OFFSET, OutputData);
UINTN Divisor;
UINT8 OutputData; //
UINT8 Data; // Configure baud rate
//
// IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));
// Map 5..8 to 0..3 IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
//
Data = (UINT8) (gData - (UINT8) 5); //
// Switch back to bank 0
// //
// Calculate divisor for baud generator OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
// IoWrite8 (gComBase + LCR_OFFSET, OutputData);
Divisor = 115200 / gBps;
return RETURN_SUCCESS;
// }
// Set communications format
// /**
OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data)))); Common function to initialize UART Serial device and USB Serial device.
IoWrite8 (gComBase + LCR_OFFSET, OutputData);
@param None
//
// Configure baud rate @retval None
//
IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); **/
IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff)); RETURN_STATUS
EFIAPI
// SerialPortInitialize (
// Switch back to bank 0 VOID
// )
OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data)))); {
IoWrite8 (gComBase + LCR_OFFSET, OutputData);
UARTInitialize ();
return RETURN_SUCCESS;
}
return RETURN_SUCCESS;
/** }
Common function to initialize UART Serial device and USB Serial device.
/**
@param None Write data to serial device.
@retval None If the buffer is NULL, then return 0;
if NumberOfBytes is zero, then return 0.
**/
RETURN_STATUS @param Buffer Point of data buffer which need to be writed.
EFIAPI @param NumberOfBytes Number of output bytes which are cached in Buffer.
SerialPortInitialize (
VOID @retval 0 Write data failed.
) @retval !0 Actual number of bytes writed to serial device.
{
**/
UARTInitialize (); UINTN
EFIAPI
UARTDbgOut (
return RETURN_SUCCESS; IN UINT8 *Buffer,
} IN UINTN NumberOfBytes
)
/** {
Write data to serial device. UINTN Result;
UINT8 Data;
If the buffer is NULL, then return 0;
if NumberOfBytes is zero, then return 0. if (NULL == Buffer) {
return 0;
@param Buffer Point of data buffer which need to be writed. }
@param NumberOfBytes Number of output bytes which are cached in Buffer.
Result = NumberOfBytes;
@retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device. while (NumberOfBytes--) {
//
**/ // Wait for the serial port to be ready.
UINTN //
EFIAPI do {
UARTDbgOut ( Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
IN UINT8 *Buffer, } while ((Data & LSR_TXRDY) == 0);
IN UINTN NumberOfBytes IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++);
) }
{
UINTN Result; return Result;
UINT8 Data; }
if (NULL == Buffer) { /**
return 0; Common function to write data to UART Serial device and USB Serial device.
}
@param Buffer Point of data buffer which need to be writed.
Result = NumberOfBytes; @param NumberOfBytes Number of output bytes which are cached in Buffer.
while (NumberOfBytes--) { **/
// UINTN
// Wait for the serial port to be ready. EFIAPI
// SerialPortWrite (
do { IN UINT8 *Buffer,
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET); IN UINTN NumberOfBytes
} while ((Data & LSR_TXRDY) == 0); )
IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++); {
} if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgOut (Buffer, NumberOfBytes);
return Result; }
}
return RETURN_SUCCESS;
/** }
Common function to write data to UART Serial device and USB Serial device.
/**
@param Buffer Point of data buffer which need to be writed. Read data from serial device and save the datas in buffer.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
If the buffer is NULL, then return 0;
**/ if NumberOfBytes is zero, then return 0.
UINTN
EFIAPI @param Buffer Point of data buffer which need to be writed.
SerialPortWrite ( @param NumberOfBytes Number of output bytes which are cached in Buffer.
IN UINT8 *Buffer,
IN UINTN NumberOfBytes @retval 0 Read data failed.
) @retval !0 Actual number of bytes raed to serial device.
{
if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) { **/
UARTDbgOut (Buffer, NumberOfBytes); UINTN
} EFIAPI
UARTDbgIn (
return RETURN_SUCCESS; OUT UINT8 *Buffer,
} IN UINTN NumberOfBytes
)
/** {
Read data from serial device and save the datas in buffer. UINTN Result;
UINT8 Data;
If the buffer is NULL, then return 0;
if NumberOfBytes is zero, then return 0. if (NULL == Buffer) {
return 0;
@param Buffer Point of data buffer which need to be writed. }
@param NumberOfBytes Number of output bytes which are cached in Buffer.
Result = NumberOfBytes;
@retval 0 Read data failed.
@retval !0 Actual number of bytes raed to serial device. while (NumberOfBytes--) {
//
**/ // Wait for the serial port to be ready.
UINTN //
EFIAPI do {
UARTDbgIn ( Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
OUT UINT8 *Buffer, } while ((Data & LSR_RXDA) == 0);
IN UINTN NumberOfBytes
) *Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase));
{ }
UINTN Result;
UINT8 Data; return Result;
}
if (NULL == Buffer) {
return 0; /**
} Common function to Read data from UART serial device, USB serial device and save the datas in buffer.
Result = NumberOfBytes; @param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
while (NumberOfBytes--) {
// **/
// Wait for the serial port to be ready. UINTN
// EFIAPI
do { SerialPortRead (
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET); OUT UINT8 *Buffer,
} while ((Data & LSR_RXDA) == 0); IN UINTN NumberOfBytes
)
*Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase)); {
} if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgIn (Buffer, NumberOfBytes);
return Result; }
}
return RETURN_SUCCESS;
/** }
Common function to Read data from UART serial device, USB serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed. /**
@param NumberOfBytes Number of output bytes which are cached in Buffer. Polls a serial device to see if there is any data waiting to be read.
**/ Polls aserial device to see if there is any data waiting to be read.
UINTN If there is data waiting to be read from the serial device, then TRUE is returned.
EFIAPI If there is no data waiting to be read from the serial device, then FALSE is returned.
SerialPortRead (
OUT UINT8 *Buffer, @retval TRUE Data is waiting to be read from the serial device.
IN UINTN NumberOfBytes @retval FALSE There is no data waiting to be read from the serial device.
)
{ **/
if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) { BOOLEAN
UARTDbgIn (Buffer, NumberOfBytes); EFIAPI
} SerialPortPoll (
VOID
return RETURN_SUCCESS; )
} {
UINT8 Data;
/** //
Polls a serial device to see if there is any data waiting to be read. // Read the serial port status.
//
Polls aserial device to see if there is any data waiting to be read. Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
If there is data waiting to be read from the serial device, then TRUE is returned.
If there is no data waiting to be read from the serial device, then FALSE is returned. return (BOOLEAN) ((Data & LSR_RXDA) != 0);
}
@retval TRUE Data is waiting to be read from the serial device.
@retval FALSE There is no data waiting to be read from the serial device.
**/
BOOLEAN
EFIAPI
SerialPortPoll (
VOID
)
{

146
Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
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@@ -1,78 +1,68 @@
/** @file /** @file
Header file of Serial port hardware definition. Header file of Serial port hardware definition.
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
the terms and conditions of the BSD License that accompanies this distribution. http://opensource.org/licenses/bsd-license.php.
The full text of the license may be found at THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
http://opensource.org/licenses/bsd-license.php.
**/
#ifndef _SIO_INIT_H_
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, #define _SIO_INIT_H_
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define WPCN381U_CONFIG_INDEX 0x2E
#define WPCN381U_CONFIG_DATA 0x2F
#define WPCN381U_CONFIG_INDEX1 0x164E
#define WPCN381U_CONFIG_DATA1 0x164F
This software and associated documentation #define WPCN381U_CHIP_ID 0xF4
(if any) is furnished under a license and may only be used or #define WDCP376_CHIP_ID 0xF1
copied in accordance with the terms of the license. Except as
permitted by such license, no part of this software or //
documentation may be reproduced, stored in a retrieval system, or // SIO Logical Devices Numbers
transmitted in any form or by any means without the express written //
consent of Intel Corporation. #define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller
#define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller
Module Name: PlatformSerialPortLib.h #define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller
#define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller
**/ #define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller
#define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller
#ifndef _SIO_INIT_H_ #define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source
#define _SIO_INIT_H_ #define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO
#define WPCN381U_CONFIG_INDEX 0x2E //
#define WPCN381U_CONFIG_DATA 0x2F // SIO Registers Layout
#define WPCN381U_CONFIG_INDEX1 0x164E //
#define WPCN381U_CONFIG_DATA1 0x164F #define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address
#define WPCN381U_CHIP_ID 0xF4 #define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address
#define WDCP376_CHIP_ID 0xF1 #define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address
#define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address
// #define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address
// SIO Logical Devices Numbers #define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address
// #define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address
#define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller #define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address
#define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller #define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address
#define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller
#define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller //
#define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller // SIO Activation Values
#define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller //
#define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source #define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device
#define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO #define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device
// //
// SIO Registers Layout // SIO GPIO
// //
#define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address #define WPCN381U_GPIO_BASE_ADDRESS 0x0A20 // SIO GPIO Base Address
#define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address
#define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address //
#define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address // SIO Serial Port Settings
#define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address //
#define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address #define WPCN381U_SERIAL_PORT0_BASE_ADDRESS 0x03F8 // Base Address of Serial Port 0 (COMA / UART0)
#define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address #define WPCN381U_SERIAL_PORT1_BASE_ADDRESS 0x02F8 // Base Address of Serial Port 1 (COMB / UART1)
#define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address
#define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address #endif
//
// SIO Activation Values
//
#define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device
#define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device
//
// SIO GPIO
//

351
Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.h
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@@ -1,207 +1,144 @@
/*++ /*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
the terms and conditions of the BSD License that accompanies this distribution. http://opensource.org/licenses/bsd-license.php.
The full text of the license may be found at THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
http://opensource.org/licenses/bsd-license.php.
Module Name:
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, PlatformStatusCode.h
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. Abstract:
Contains Platform specific implementations required to use status codes.
--*/
Module Name:
#ifndef _PLATFORM_STATUS_CODE_H_
PlatformStatusCode.h #define _PLATFORM_STATUS_CODE_H_
Abstract:
#define CONFIG_PORT0 0x4E
Contains Platform specific implementations required to use status codes. #define INDEX_PORT0 0x4E
#define DATA_PORT0 0x4F
--*/ #define PCI_IDX 0xCF8
#define PCI_DAT 0xCFC
#ifndef _PLATFORM_STATUS_CODE_H_
#define _PLATFORM_STATUS_CODE_H_ #include "MonoStatusCode.h"
#ifndef _PEI_PORT_80_STATUS_CODE_H_
#define _PEI_PORT_80_STATUS_CODE_H_
#define CONFIG_PORT0 0x4E
#define INDEX_PORT0 0x4E
#define DATA_PORT0 0x4F
#define PCI_IDX 0xCF8 //
#define PCI_DAT 0xCFC // Status code reporting function
//
#include "MonoStatusCode.h" EFI_STATUS
Port80ReportStatusCode (
/*++ IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_STATUS_CODE_TYPE CodeType,
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved IN EFI_STATUS_CODE_VALUE Value,
IN UINT32 Instance,
IN CONST EFI_GUID * CallerId,
This program and the accompanying materials are licensed and made available under IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
);
the terms and conditions of the BSD License that accompanies this distribution.
#endif
The full text of the license may be found at
#ifndef _PEI_SERIAL_STATUS_CODE_LIB_H_
http://opensource.org/licenses/bsd-license.php. #define _PEI_SERIAL_STATUS_CODE_LIB_H_
#include <Guid/StatusCodeDataTypeId.h>
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, #include <Guid/StatusCodeDataTypeDebug.h>
#include <Library/ReportStatusCodeLib.h>
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include <Library/PrintLib.h>
#include <Library/BaseMemoryLib.h>
//
This software and associated documentation (if any) is furnished // Initialization function
under a license and may only be used or copied in accordance //
with the terms of the license. Except as permitted by such VOID
license, no part of this software or documentation may be SerialInitializeStatusCode (
reproduced, stored in a retrieval system, or transmitted in any VOID
form or by any means without the express written consent of );
Intel Corporation.
//
// Status code reporting function
Module Name: //
EFI_STATUS
Port80StatusCodeLib.h SerialReportStatusCode (
IN CONST EFI_PEI_SERVICES **PeiServices,
Abstract: IN EFI_STATUS_CODE_TYPE CodeType,
IN EFI_STATUS_CODE_VALUE Value,
Lib to provide status code reporting via port 80. IN UINT32 Instance,
IN CONST EFI_GUID * CallerId,
--*/ IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
);
#ifndef _PEI_PORT_80_STATUS_CODE_H_
#define _PEI_PORT_80_STATUS_CODE_H_ #endif
extern EFI_PEI_PROGRESS_CODE_PPI mStatusCodePpi;
extern EFI_PEI_PPI_DESCRIPTOR mPpiListStatusCode;
// #define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
// Status code reporting function #define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))
// #define STATUSCODE_PEIM_SIGNATURE EFI_SIGNATURE_32 ('p', 's', 't', 'c')
EFI_STATUS
Port80ReportStatusCode ( typedef struct {
IN CONST EFI_PEI_SERVICES **PeiServices, UINT32 Signature;
IN EFI_STATUS_CODE_TYPE CodeType, EFI_FFS_FILE_HEADER *FfsHeader;
IN EFI_STATUS_CODE_VALUE Value, EFI_PEI_NOTIFY_DESCRIPTOR StatusCodeNotify;
IN UINT32 Instance, } STATUSCODE_CALLBACK_STATE_INFORMATION;
IN CONST EFI_GUID * CallerId,
IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL #pragma pack(1)
); typedef struct {
UINT16 Limit;
#endif UINT32 Base;
} GDT_DSCRIPTOR;
/*++ #pragma pack()
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved #define STATUSCODE_PEIM_FROM_THIS(a) \
BASE_CR ( \
a, \
This program and the accompanying materials are licensed and made available under STATUSCODE_CALLBACK_STATE_INFORMATION, \
StatusCodeNotify \
the terms and conditions of the BSD License that accompanies this distribution. )
The full text of the license may be found at VOID
EFIAPI
http://opensource.org/licenses/bsd-license.php. PlatformInitializeStatusCode (
IN EFI_FFS_FILE_HEADER *FfsHeader,
IN CONST EFI_PEI_SERVICES **PeiServices
);
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. //
// Function declarations
//
/**
This software and associated documentation (if any) is furnished Install Firmware Volume Hob's once there is main memory
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such @param PeiServices General purpose services available to every PEIM.
license, no part of this software or documentation may be @param NotifyDescriptor Not Used
reproduced, stored in a retrieval system, or transmitted in any @param Ppi Not Used
form or by any means without the express written consent of
Intel Corporation. @retval Status EFI_SUCCESS if the interface could be successfully
installed
Module Name: **/
EFI_STATUS
SerialStatusCodeLib.h EFIAPI
MemoryDiscoveredPpiNotifyCallback (
Abstract: IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
Lib to provide Serial I/O status code reporting. IN VOID *Ppi
);
--*/
#endif
#ifndef _PEI_SERIAL_STATUS_CODE_LIB_H_
#define _PEI_SERIAL_STATUS_CODE_LIB_H_
#include <Guid/StatusCodeDataTypeId.h>
#include <Guid/StatusCodeDataTypeDebug.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/PrintLib.h>
#include <Library/BaseMemoryLib.h>
//
// Initialization function
//
VOID
SerialInitializeStatusCode (
VOID
);
//
// Status code reporting function
//
EFI_STATUS
SerialReportStatusCode (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_STATUS_CODE_TYPE CodeType,
IN EFI_STATUS_CODE_VALUE Value,
IN UINT32 Instance,
IN CONST EFI_GUID * CallerId,
IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
);
#endif
extern EFI_PEI_PROGRESS_CODE_PPI mStatusCodePpi;
extern EFI_PEI_PPI_DESCRIPTOR mPpiListStatusCode;
#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))
#define STATUSCODE_PEIM_SIGNATURE EFI_SIGNATURE_32 ('p', 's', 't', 'c')
typedef struct {
UINT32 Signature;
EFI_FFS_FILE_HEADER *FfsHeader;
EFI_PEI_NOTIFY_DESCRIPTOR StatusCodeNotify;
} STATUSCODE_CALLBACK_STATE_INFORMATION;
#pragma pack(1)
typedef struct {
UINT16 Limit;
UINT32 Base;
} GDT_DSCRIPTOR;
#pragma pack()
#define STATUSCODE_PEIM_FROM_THIS(a) \
BASE_CR ( \
a, \
STATUSCODE_CALLBACK_STATE_INFORMATION, \
StatusCodeNotify \
)
VOID
EFIAPI
PlatformInitializeStatusCode (
IN EFI_FFS_FILE_HEADER *FfsHeader,