Adding support for BeagleBoard.
ArmPkg - Supoprt for ARM specific things that can change as the architecture changes. Plus semihosting JTAG drivers. EmbeddedPkg - Generic support for an embeddded platform. Including a light weight command line shell. BeagleBoardPkg - Platform specifics for BeagleBoard. SD Card works, but USB has issues. Looks like a bug in the open source USB stack (Our internal stack works fine). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9518 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
32
ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
Normal file
32
ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
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@@ -0,0 +1,32 @@
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#%HEADER%
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = Arm11ArmLib
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FILE_GUID = 00586300-0E06-4790-AC44-86C56ACBB942
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmLib
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[Sources.common]
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../Common/ArmLibSupport.S | GCC
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../Common/ArmLibSupport.asm | RVCT
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../Common/ArmLib.c
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Arm11Support.S | GCC
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Arm11Support.asm | RVCT
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Arm11Lib.c
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../Arm9/Arm9CacheInformation.c
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[Packages]
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ArmPkg/ArmPkg.dec
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MdePkg/MdePkg.dec
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[LibraryClasses]
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MemoryAllocationLib
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
32
ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
Normal file
32
ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
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@@ -0,0 +1,32 @@
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#%HEADER%
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = Arm11ArmLib
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FILE_GUID = 8dfb4ea2-3901-44f9-ae54-ca3d50362d2f
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmLib
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[Sources.common]
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../Common/ArmLibSupport.S | GCC
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../Common/ArmLibSupport.asm | RVCT
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../Common/ArmLib.c
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Arm11Support.S | GCC
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Arm11Support.asm | RVCT
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Arm11Lib.c
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../Arm9/Arm9CacheInformation.c
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[Packages]
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ArmPkg/ArmPkg.dec
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MdePkg/MdePkg.dec
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[LibraryClasses]
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PrePiLib
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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118
ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
Normal file
118
ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
Normal file
@@ -0,0 +1,118 @@
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/** @file
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Copyright (c) 2008-2009, Apple Inc. All rights reserved.
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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||||
which accompanies this distribution. The full text of the license may be found at
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||||
http://opensource.org/licenses/bsd-license.php
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||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Chipset/ARM1176JZ-S.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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VOID
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FillTranslationTable (
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IN UINT32 *TranslationTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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UINT32 *Entry;
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UINTN Sections;
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UINTN Index;
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UINT32 Attributes;
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UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
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switch (MemoryRegion->Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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default:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
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break;
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}
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Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
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for (Index = 0; Index < Sections; Index++)
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{
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*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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}
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}
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VOID
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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)
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{
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VOID *TranslationTable;
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// Allocate pages for translation table.
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TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
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TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
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if (TranslationTableBase != NULL) {
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*TranslationTableBase = TranslationTable;
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}
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if (TranslationTableBase != NULL) {
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*TranslationTableSize = TRANSLATION_TABLE_SIZE;
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}
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ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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ArmInvalidateTlb();
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ArmDisableDataCache();
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ArmDisableInstructionCache();
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ArmDisableMmu();
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// Make sure nothing sneaked into the cache
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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while (MemoryTable->Length != 0) {
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FillTranslationTable(TranslationTable, MemoryTable);
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MemoryTable++;
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}
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ArmSetTranslationTableBaseAddress(TranslationTable);
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ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
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DOMAIN_ACCESS_CONTROL_NONE(14) |
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DOMAIN_ACCESS_CONTROL_NONE(13) |
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DOMAIN_ACCESS_CONTROL_NONE(12) |
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DOMAIN_ACCESS_CONTROL_NONE(11) |
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DOMAIN_ACCESS_CONTROL_NONE(10) |
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DOMAIN_ACCESS_CONTROL_NONE( 9) |
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DOMAIN_ACCESS_CONTROL_NONE( 8) |
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DOMAIN_ACCESS_CONTROL_NONE( 7) |
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DOMAIN_ACCESS_CONTROL_NONE( 6) |
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DOMAIN_ACCESS_CONTROL_NONE( 5) |
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DOMAIN_ACCESS_CONTROL_NONE( 4) |
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DOMAIN_ACCESS_CONTROL_NONE( 3) |
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DOMAIN_ACCESS_CONTROL_NONE( 2) |
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DOMAIN_ACCESS_CONTROL_NONE( 1) |
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DOMAIN_ACCESS_CONTROL_MANAGER(0));
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ArmEnableInstructionCache();
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ArmEnableDataCache();
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ArmEnableMmu();
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}
|
129
ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
Normal file
129
ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
Normal file
@@ -0,0 +1,129 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
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#
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# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
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||||
#
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||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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.globl ASM_PFX(ArmCleanInvalidateDataCache)
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.globl ASM_PFX(ArmCleanDataCache)
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.globl ASM_PFX(ArmInvalidateDataCache)
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.globl ASM_PFX(ArmInvalidateInstructionCache)
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.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
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.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
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.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
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.globl ASM_PFX(ArmEnableMmu)
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.globl ASM_PFX(ArmDisableMmu)
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.globl ASM_PFX(ArmEnableDataCache)
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.globl ASM_PFX(ArmDisableDataCache)
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.globl ASM_PFX(ArmEnableInstructionCache)
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.globl ASM_PFX(ArmDisableInstructionCache)
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.globl ASM_PFX(ArmEnableBranchPrediction)
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.globl ASM_PFX(ArmDisableBranchPrediction)
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.set DC_ON, (0x1<<2)
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.set IC_ON, (0x1<<12)
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.set XP_ON, (0x1<<23)
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ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
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mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
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bx lr
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ASM_PFX(ArmCleanDataCache):
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mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
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bx lr
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ASM_PFX(ArmCleanInvalidateDataCache):
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mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
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bx lr
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ASM_PFX(ArmInvalidateDataCache):
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mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
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bx lr
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ASM_PFX(ArmInvalidateInstructionCache):
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mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
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bx lr
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ASM_PFX(ArmEnableMmu):
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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bx LR
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ASM_PFX(ArmDisableMmu):
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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mov R0,#0
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mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
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mov R0,#0
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mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
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bx LR
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ASM_PFX(ArmEnableDataCache):
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmDisableDataCache):
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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ASM_PFX(ArmEnableInstructionCache):
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set I bit
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||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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bx LR
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||||
|
||||
ASM_PFX(ArmDisableInstructionCache):
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||||
ldr R1,=IC_ON
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||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear I bit.
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
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||||
|
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ASM_PFX(ArmEnableBranchPrediction):
|
||||
mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableBranchPrediction):
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
133
ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
Normal file
133
ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
Normal file
@@ -0,0 +1,133 @@
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
|
||||
//
|
||||
// All rights reserved. This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
EXPORT ArmCleanInvalidateDataCache
|
||||
EXPORT ArmCleanDataCache
|
||||
EXPORT ArmInvalidateDataCache
|
||||
EXPORT ArmInvalidateInstructionCache
|
||||
EXPORT ArmInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmCleanDataCacheEntryByMVA
|
||||
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmEnableMmu
|
||||
EXPORT ArmDisableMmu
|
||||
EXPORT ArmEnableDataCache
|
||||
EXPORT ArmDisableDataCache
|
||||
EXPORT ArmEnableInstructionCache
|
||||
EXPORT ArmDisableInstructionCache
|
||||
EXPORT ArmEnableBranchPrediction
|
||||
EXPORT ArmDisableBranchPrediction
|
||||
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
XP_ON EQU ( 0x1:SHL:23 )
|
||||
|
||||
|
||||
AREA ArmCacheLib, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCacheEntryByMVA
|
||||
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanDataCache
|
||||
mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCache
|
||||
mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmInvalidateDataCache
|
||||
mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
|
||||
bx lr
|
||||
|
||||
|
||||
ArmInvalidateInstructionCache
|
||||
mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
|
||||
bx lr
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmEnableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set I bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear I bit.
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
END
|
32
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
Normal file
32
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
Normal file
@@ -0,0 +1,32 @@
|
||||
#%HEADER%
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = Arm9ArmLib
|
||||
FILE_GUID = 375D70D3-91E0-4374-A540-68BD959EB184
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmLib
|
||||
|
||||
[Sources.common]
|
||||
../Common/ArmLibSupport.S | GCC
|
||||
../Common/ArmLibSupport.asm | RVCT
|
||||
../Common/ArmLib.c
|
||||
|
||||
Arm9Support.S | GCC
|
||||
Arm9Support.asm | RVCT
|
||||
|
||||
Arm9Lib.c
|
||||
Arm9CacheInformation.c
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
MemoryAllocationLib
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
32
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
Executable file
32
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
Executable file
@@ -0,0 +1,32 @@
|
||||
#%HEADER%
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = Arm9ArmLibPrePi
|
||||
FILE_GUID = e9b6011f-ee15-4e59-ab8f-a819a081fa54
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmLib
|
||||
|
||||
[Sources.common]
|
||||
../Common/ArmLibSupport.S | GCC
|
||||
../Common/ArmLibSupport.asm | RVCT
|
||||
../Common/ArmLib.c
|
||||
|
||||
Arm9Support.S | GCC
|
||||
Arm9Support.asm | RVCT
|
||||
|
||||
Arm9Lib.c
|
||||
Arm9CacheInformation.c
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
PrePiLib
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
164
ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
Normal file
164
ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
Normal file
@@ -0,0 +1,164 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
#include "ArmLibPrivate.h"
|
||||
|
||||
ARM_CACHE_TYPE
|
||||
EFIAPI
|
||||
ArmCacheType (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (CACHE_TYPE(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;
|
||||
default: return ARM_CACHE_TYPE_UNKNOWN;
|
||||
}
|
||||
}
|
||||
|
||||
ARM_CACHE_ARCHITECTURE
|
||||
EFIAPI
|
||||
ArmCacheArchitecture (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (CACHE_ARCHITECTURE(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_ARCHITECTURE_UNIFIED: return ARM_CACHE_ARCHITECTURE_UNIFIED;
|
||||
case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;
|
||||
default: return ARM_CACHE_ARCHITECTURE_UNKNOWN;
|
||||
}
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmDataCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (DATA_CACHE_PRESENT(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_PRESENT: return TRUE;
|
||||
case CACHE_NOT_PRESENT: return FALSE;
|
||||
default: return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (DATA_CACHE_SIZE(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_SIZE_4_KB: return 4 * 1024;
|
||||
case CACHE_SIZE_8_KB: return 8 * 1024;
|
||||
case CACHE_SIZE_16_KB: return 16 * 1024;
|
||||
case CACHE_SIZE_32_KB: return 32 * 1024;
|
||||
case CACHE_SIZE_64_KB: return 64 * 1024;
|
||||
case CACHE_SIZE_128_KB: return 128 * 1024;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (DATA_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_ASSOCIATIVITY_4_WAY: return 4;
|
||||
case CACHE_ASSOCIATIVITY_DIRECT: return 1;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (DATA_CACHE_LINE_LENGTH(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_LINE_LENGTH_32_BYTES: return 32;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmInstructionCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (INSTRUCTION_CACHE_PRESENT(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_PRESENT: return TRUE;
|
||||
case CACHE_NOT_PRESENT: return FALSE;
|
||||
default: return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (INSTRUCTION_CACHE_SIZE(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_SIZE_4_KB: return 4 * 1024;
|
||||
case CACHE_SIZE_8_KB: return 8 * 1024;
|
||||
case CACHE_SIZE_16_KB: return 16 * 1024;
|
||||
case CACHE_SIZE_32_KB: return 32 * 1024;
|
||||
case CACHE_SIZE_64_KB: return 64 * 1024;
|
||||
case CACHE_SIZE_128_KB: return 128 * 1024;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (INSTRUCTION_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_ASSOCIATIVITY_8_WAY: return 8;
|
||||
case CACHE_ASSOCIATIVITY_4_WAY: return 4;
|
||||
case CACHE_ASSOCIATIVITY_DIRECT: return 1;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
switch (INSTRUCTION_CACHE_LINE_LENGTH(Cp15CacheInfo()))
|
||||
{
|
||||
case CACHE_LINE_LENGTH_32_BYTES: return 32;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
118
ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
Normal file
118
ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
Normal file
@@ -0,0 +1,118 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Chipset/ARM926EJ-S.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
|
||||
VOID
|
||||
FillTranslationTable (
|
||||
IN UINT32 *TranslationTable,
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
|
||||
)
|
||||
{
|
||||
UINT32 *Entry;
|
||||
UINTN Sections;
|
||||
UINTN Index;
|
||||
UINT32 Attributes;
|
||||
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
|
||||
|
||||
switch (MemoryRegion->Attributes) {
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
|
||||
default:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
|
||||
break;
|
||||
}
|
||||
|
||||
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
|
||||
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
|
||||
|
||||
for (Index = 0; Index < Sections; Index++)
|
||||
{
|
||||
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
|
||||
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmConfigureMmu (
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
|
||||
OUT VOID **TranslationTableBase OPTIONAL,
|
||||
OUT UINTN *TranslationTableSize OPTIONAL
|
||||
)
|
||||
{
|
||||
VOID *TranslationTable;
|
||||
|
||||
// Allocate pages for translation table.
|
||||
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
|
||||
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableBase = TranslationTable;
|
||||
}
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
|
||||
}
|
||||
|
||||
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
|
||||
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
ArmInvalidateTlb();
|
||||
|
||||
ArmDisableDataCache();
|
||||
ArmDisableInstructionCache();
|
||||
ArmDisableMmu();
|
||||
|
||||
// Make sure nothing sneaked into the cache
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
|
||||
while (MemoryTable->Length != 0) {
|
||||
FillTranslationTable(TranslationTable, MemoryTable);
|
||||
MemoryTable++;
|
||||
}
|
||||
|
||||
ArmSetTranslationTableBaseAddress(TranslationTable);
|
||||
|
||||
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(14) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(13) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(12) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(11) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(10) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 9) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 8) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 7) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 6) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 5) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 4) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 3) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 2) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 1) |
|
||||
DOMAIN_ACCESS_CONTROL_MANAGER(0));
|
||||
|
||||
ArmEnableInstructionCache();
|
||||
ArmEnableDataCache();
|
||||
ArmEnableMmu();
|
||||
}
|
128
ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
Normal file
128
ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
Normal file
@@ -0,0 +1,128 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
|
||||
#
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
.globl ASM_PFX(ArmCleanInvalidateDataCache)
|
||||
.globl ASM_PFX(ArmCleanDataCache)
|
||||
.globl ASM_PFX(ArmInvalidateDataCache)
|
||||
.globl ASM_PFX(ArmInvalidateInstructionCache)
|
||||
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
|
||||
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
|
||||
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
|
||||
.globl ASM_PFX(ArmEnableMmu)
|
||||
.globl ASM_PFX(ArmDisableMmu)
|
||||
.globl ASM_PFX(ArmEnableDataCache)
|
||||
.globl ASM_PFX(ArmDisableDataCache)
|
||||
.globl ASM_PFX(ArmEnableInstructionCache)
|
||||
.globl ASM_PFX(ArmDisableInstructionCache)
|
||||
.globl ASM_PFX(ArmEnableBranchPrediction)
|
||||
.globl ASM_PFX(ArmDisableBranchPrediction)
|
||||
|
||||
.set DC_ON, (1<<2)
|
||||
.set IC_ON, (1<<12)
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCleanDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmEnableInstructionCache):
|
||||
ldr r1,=IC_ON
|
||||
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
|
||||
orr r0,r0,r1 @Set I bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInstructionCache):
|
||||
ldr r1,=IC_ON
|
||||
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
|
||||
bic r0,r0,r1 @Clear I bit.
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateInstructionCache):
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
|
||||
@Also flushes the branch target cache.
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c7,c10,4 @Data write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableDataCache):
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableDataCache):
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmCleanDataCache):
|
||||
mrc p15,0,r15,c7,c10,3
|
||||
bne ASM_PFX(ArmCleanDataCache)
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCache):
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCache):
|
||||
mrc p15,0,r15,c7,c14,3
|
||||
bne ASM_PFX(ArmCleanInvalidateDataCache)
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Drain write buffer
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableBranchPrediction):
|
||||
bx LR @Branch prediction is not supported.
|
||||
|
||||
ASM_PFX(ArmDisableBranchPrediction):
|
||||
bx LR @Branch prediction is not supported.
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
|
129
ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
Normal file
129
ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
Normal file
@@ -0,0 +1,129 @@
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
|
||||
//
|
||||
// All rights reserved. This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
EXPORT ArmCleanInvalidateDataCache
|
||||
EXPORT ArmCleanDataCache
|
||||
EXPORT ArmInvalidateDataCache
|
||||
EXPORT ArmInvalidateInstructionCache
|
||||
EXPORT ArmInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmCleanDataCacheEntryByMVA
|
||||
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmEnableMmu
|
||||
EXPORT ArmDisableMmu
|
||||
EXPORT ArmEnableDataCache
|
||||
EXPORT ArmDisableDataCache
|
||||
EXPORT ArmEnableInstructionCache
|
||||
EXPORT ArmDisableInstructionCache
|
||||
EXPORT ArmEnableBranchPrediction
|
||||
EXPORT ArmDisableBranchPrediction
|
||||
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
|
||||
AREA ArmCacheLib, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmCleanDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
||||
BX lr
|
||||
|
||||
ArmEnableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set I bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear I bit.
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmInvalidateInstructionCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmCleanDataCache
|
||||
MRC p15,0,r15,c7,c10,3
|
||||
BNE ArmCleanDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmInvalidateDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmCleanInvalidateDataCache
|
||||
MRC p15,0,r15,c7,c14,3
|
||||
BNE ArmCleanInvalidateDataCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
|
||||
BX LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
bx LR ;Branch prediction is not supported.
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
bx LR ;Branch prediction is not supported.
|
||||
|
||||
END
|
288
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c
Normal file
288
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c
Normal file
@@ -0,0 +1,288 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Chipset/Cortex-A8.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include "ArmCortexALib.h"
|
||||
|
||||
VOID
|
||||
FillTranslationTable (
|
||||
IN UINT32 *TranslationTable,
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
|
||||
)
|
||||
{
|
||||
UINT32 *Entry;
|
||||
UINTN Sections;
|
||||
UINTN Index;
|
||||
UINT32 Attributes;
|
||||
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
|
||||
|
||||
switch (MemoryRegion->Attributes) {
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_DEVICE;
|
||||
break;
|
||||
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
|
||||
default:
|
||||
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
|
||||
break;
|
||||
}
|
||||
|
||||
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
|
||||
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
|
||||
|
||||
for (Index = 0; Index < Sections; Index++)
|
||||
{
|
||||
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
|
||||
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmConfigureMmu (
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
|
||||
OUT VOID **TranslationTableBase OPTIONAL,
|
||||
OUT UINTN *TranslationTableSize OPTIONAL
|
||||
)
|
||||
{
|
||||
VOID *TranslationTable;
|
||||
|
||||
// Allocate pages for translation table.
|
||||
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
|
||||
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableBase = TranslationTable;
|
||||
}
|
||||
|
||||
if (TranslationTableBase != NULL) {
|
||||
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
|
||||
}
|
||||
|
||||
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
|
||||
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
ArmInvalidateTlb();
|
||||
|
||||
ArmDisableDataCache();
|
||||
ArmDisableInstructionCache();
|
||||
ArmDisableMmu();
|
||||
|
||||
// Make sure nothing sneaked into the cache
|
||||
ArmCleanInvalidateDataCache();
|
||||
ArmInvalidateInstructionCache();
|
||||
|
||||
while (MemoryTable->Length != 0) {
|
||||
FillTranslationTable(TranslationTable, MemoryTable);
|
||||
MemoryTable++;
|
||||
}
|
||||
|
||||
ArmSetTranslationTableBaseAddress(TranslationTable);
|
||||
|
||||
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(14) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(13) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(12) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(11) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE(10) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 9) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 8) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 7) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 6) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 5) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 4) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 3) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 2) |
|
||||
DOMAIN_ACCESS_CONTROL_NONE( 1) |
|
||||
DOMAIN_ACCESS_CONTROL_MANAGER(0));
|
||||
|
||||
ArmEnableInstructionCache();
|
||||
ArmEnableDataCache();
|
||||
ArmEnableMmu();
|
||||
}
|
||||
|
||||
ARM_CACHE_TYPE
|
||||
EFIAPI
|
||||
ArmCacheType (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ARM_CACHE_TYPE_WRITE_BACK;
|
||||
}
|
||||
|
||||
ARM_CACHE_ARCHITECTURE
|
||||
EFIAPI
|
||||
ArmCacheArchitecture (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ARM_CACHE_ARCHITECTURE_SEPARATE;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmDataCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 16 * 1024;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
ArmDataCacheSets (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 64;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 64;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmInstructionCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 16 * 1024;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 4;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 64;
|
||||
}
|
||||
|
||||
VOID
|
||||
ArmCortexADataCacheOperation (
|
||||
IN ARM_CORTEX_A_CACHE_OPERATION DataCacheOperation
|
||||
)
|
||||
{
|
||||
UINTN Set;
|
||||
UINTN SetCount;
|
||||
UINTN SetShift;
|
||||
UINTN Way;
|
||||
UINTN WayCount;
|
||||
UINTN WayShift;
|
||||
UINT32 SetWayFormat;
|
||||
UINTN SavedInterruptState;
|
||||
|
||||
SetCount = ArmDataCacheSets();
|
||||
WayCount = ArmDataCacheAssociativity();
|
||||
|
||||
// Cortex-A8 Manual, System Control Coprocessor chapter
|
||||
SetShift = 6;
|
||||
WayShift = 32 - LowBitSet32 ((UINT32)WayCount);
|
||||
|
||||
SavedInterruptState = ArmDisableInterrupts();
|
||||
|
||||
for (Way = 0; Way < WayCount; Way++) {
|
||||
for (Set = 0; Set < SetCount; Set++) {
|
||||
// Build the format that the CP15 instruction can understand
|
||||
SetWayFormat = (Way << WayShift) | (Set << SetShift);
|
||||
|
||||
// Pass it through
|
||||
(*DataCacheOperation)(SetWayFormat);
|
||||
}
|
||||
}
|
||||
|
||||
ArmDrainWriteBuffer();
|
||||
|
||||
if (SavedInterruptState) {
|
||||
ArmEnableInterrupts();
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmCortexADataCacheOperation(ArmInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmCortexADataCacheOperation(ArmCleanInvalidateDataCacheEntryBySetWay);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
ArmCortexADataCacheOperation(ArmCleanDataCacheEntryBySetWay);
|
||||
}
|
45
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.h
Normal file
45
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.h
Normal file
@@ -0,0 +1,45 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __ARMCORTEXALIB_H__
|
||||
#define __ARMCORTEXALIB_H__
|
||||
|
||||
typedef VOID (*ARM_CORTEX_A_CACHE_OPERATION)(UINT32);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmDrainWriteBuffer (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateDataCacheEntryBySetWay (
|
||||
IN UINT32 SetWayFormat
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCacheEntryBySetWay (
|
||||
IN UINT32 SetWayFormat
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanInvalidateDataCacheEntryBySetWay (
|
||||
IN UINT32 SetWayFormat
|
||||
);
|
||||
|
||||
#endif // __ARMCORTEXALIB_H__
|
||||
|
140
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S
Normal file
140
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S
Normal file
@@ -0,0 +1,140 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
|
||||
#
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
.globl ASM_PFX(ArmInvalidateInstructionCache)
|
||||
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
|
||||
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
|
||||
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
|
||||
.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
|
||||
.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
|
||||
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
|
||||
.globl ASM_PFX(ArmDrainWriteBuffer)
|
||||
.globl ASM_PFX(ArmEnableMmu)
|
||||
.globl ASM_PFX(ArmDisableMmu)
|
||||
.globl ASM_PFX(ArmEnableDataCache)
|
||||
.globl ASM_PFX(ArmDisableDataCache)
|
||||
.globl ASM_PFX(ArmEnableInstructionCache)
|
||||
.globl ASM_PFX(ArmDisableInstructionCache)
|
||||
.globl ASM_PFX(ArmEnableExtendPTConfig)
|
||||
.globl ASM_PFX(ArmDisableExtendPTConfig)
|
||||
.globl ASM_PFX(ArmEnableBranchPrediction)
|
||||
.globl ASM_PFX(ArmDisableBranchPrediction)
|
||||
|
||||
.set DC_ON, (0x1<<2)
|
||||
.set IC_ON, (0x1<<12)
|
||||
.set XP_ON, (0x1<<23)
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmCleanDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
|
||||
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
|
||||
mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
|
||||
mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
|
||||
mcr p15, 0, r0, c7, c10, 2 @ Clean this line
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmDrainWriteBuffer):
|
||||
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer for sync
|
||||
bx lr
|
||||
|
||||
|
||||
ASM_PFX(ArmInvalidateInstructionCache):
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 @Instruction synchronization barrier
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableMmu):
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableMmu):
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c13,c0,0 @FCSE PID register must be cleared before disabling MMU
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0 @Disable MMU
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 @Instruction synchronization barrier
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableDataCache):
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableDataCache):
|
||||
ldr R1,=DC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear C bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableInstructionCache):
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
orr R0,R0,R1 @Set I bit
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInstructionCache):
|
||||
ldr R1,=IC_ON
|
||||
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
|
||||
bic R0,R0,R1 @Clear I bit.
|
||||
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableBranchPrediction):
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableBranchPrediction):
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
141
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.asm
Normal file
141
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.asm
Normal file
@@ -0,0 +1,141 @@
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
|
||||
//
|
||||
// All rights reserved. This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
EXPORT ArmInvalidateInstructionCache
|
||||
EXPORT ArmInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmCleanDataCacheEntryByMVA
|
||||
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
|
||||
EXPORT ArmInvalidateDataCacheEntryBySetWay
|
||||
EXPORT ArmCleanDataCacheEntryBySetWay
|
||||
EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
|
||||
EXPORT ArmDrainWriteBuffer
|
||||
EXPORT ArmEnableMmu
|
||||
EXPORT ArmDisableMmu
|
||||
EXPORT ArmEnableDataCache
|
||||
EXPORT ArmDisableDataCache
|
||||
EXPORT ArmEnableInstructionCache
|
||||
EXPORT ArmDisableInstructionCache
|
||||
EXPORT ArmEnableBranchPrediction
|
||||
EXPORT ArmDisableBranchPrediction
|
||||
|
||||
DC_ON EQU ( 0x1:SHL:2 )
|
||||
IC_ON EQU ( 0x1:SHL:12 )
|
||||
XP_ON EQU ( 0x1:SHL:23 )
|
||||
|
||||
|
||||
AREA ArmCacheLib, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmCleanDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCacheEntryByMVA
|
||||
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
|
||||
BX lr
|
||||
|
||||
|
||||
ArmInvalidateDataCacheEntryBySetWay
|
||||
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanInvalidateDataCacheEntryBySetWay
|
||||
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmCleanDataCacheEntryBySetWay
|
||||
mcr p15, 0, r0, c7, c10, 2 ; Clean this line
|
||||
bx lr
|
||||
|
||||
|
||||
ArmDrainWriteBuffer
|
||||
mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
|
||||
bx lr
|
||||
|
||||
|
||||
ArmInvalidateInstructionCache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
|
||||
MOV R0,#0
|
||||
MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
|
||||
BX LR
|
||||
|
||||
ArmEnableMmu
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
orr R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0
|
||||
bx LR
|
||||
|
||||
ArmDisableMmu
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
|
||||
mrc p15,0,R0,c1,c0,0
|
||||
bic R0,R0,#1
|
||||
mcr p15,0,R0,c1,c0,0 ;Disable MMU
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
|
||||
mov R0,#0
|
||||
mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
|
||||
bx LR
|
||||
|
||||
ArmEnableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableDataCache
|
||||
LDR R1,=DC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear C bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmEnableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
ORR R0,R0,R1 ;Set I bit
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmDisableInstructionCache
|
||||
LDR R1,=IC_ON
|
||||
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
|
||||
BIC R0,R0,R1 ;Clear I bit.
|
||||
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
|
||||
BX LR
|
||||
|
||||
ArmEnableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
ArmDisableBranchPrediction
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
bic r0, r0, #0x00000800
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
bx LR
|
||||
|
||||
END
|
31
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
Normal file
31
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
Normal file
@@ -0,0 +1,31 @@
|
||||
#%HEADER%
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmCortexArmLib
|
||||
FILE_GUID = 411cdfd8-f964-4b9d-a3e3-1719a9c15559
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmLib
|
||||
|
||||
[Sources.common]
|
||||
../Common/ArmLibSupport.S | GCC
|
||||
../Common/ArmLibSupport.asm | RVCT
|
||||
../Common/ArmLib.c
|
||||
|
||||
ArmCortexASupport.S | GCC
|
||||
ArmCortexASupport.asm | RVCT
|
||||
|
||||
ArmCortexALib.c
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
MemoryAllocationLib
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
31
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
Normal file
31
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
Normal file
@@ -0,0 +1,31 @@
|
||||
#%HEADER%
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmCortexArmLibPrePi
|
||||
FILE_GUID = A150FA0C-F4E8-4207-9BEB-CD6DFB430D73
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmLib
|
||||
|
||||
[Sources.common]
|
||||
../Common/ArmLibSupport.S | GCC
|
||||
../Common/ArmLibSupport.asm | RVCT
|
||||
../Common/ArmLib.c
|
||||
|
||||
ArmCortexASupport.S | GCC
|
||||
ArmCortexASupport.asm | RVCT
|
||||
|
||||
ArmCortexALib.c
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
PrePiLib
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
60
ArmPkg/Library/ArmLib/Common/ArmLib.c
Normal file
60
ArmPkg/Library/ArmLib/Common/ArmLib.c
Normal file
@@ -0,0 +1,60 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
|
||||
#include "ArmLibPrivate.h"
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCacheInformation (
|
||||
OUT ARM_CACHE_INFO *CacheInfo
|
||||
)
|
||||
{
|
||||
if (CacheInfo != NULL) {
|
||||
CacheInfo->Type = ArmCacheType();
|
||||
CacheInfo->Architecture = ArmCacheArchitecture();
|
||||
CacheInfo->DataCachePresent = ArmDataCachePresent();
|
||||
CacheInfo->DataCacheSize = ArmDataCacheSize();
|
||||
CacheInfo->DataCacheAssociativity = ArmDataCacheAssociativity();
|
||||
CacheInfo->DataCacheLineLength = ArmDataCacheLineLength();
|
||||
CacheInfo->InstructionCachePresent = ArmInstructionCachePresent();
|
||||
CacheInfo->InstructionCacheSize = ArmInstructionCacheSize();
|
||||
CacheInfo->InstructionCacheAssociativity = ArmInstructionCacheAssociativity();
|
||||
CacheInfo->InstructionCacheLineLength = ArmInstructionCacheLineLength();
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmSwitchProcessorMode (
|
||||
IN ARM_PROCESSOR_MODE Mode
|
||||
)
|
||||
{
|
||||
CPSRMaskInsert(ARM_PROCESSOR_MODE_MASK, Mode);
|
||||
}
|
||||
|
||||
|
||||
ARM_PROCESSOR_MODE
|
||||
EFIAPI
|
||||
ArmProcessorMode (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);
|
||||
}
|
70
ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
Normal file
70
ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
Normal file
@@ -0,0 +1,70 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __ARM_LIB_PRIVATE_H__
|
||||
#define __ARM_LIB_PRIVATE_H__
|
||||
|
||||
#define CACHE_SIZE_4_KB (3UL)
|
||||
#define CACHE_SIZE_8_KB (4UL)
|
||||
#define CACHE_SIZE_16_KB (5UL)
|
||||
#define CACHE_SIZE_32_KB (6UL)
|
||||
#define CACHE_SIZE_64_KB (7UL)
|
||||
#define CACHE_SIZE_128_KB (8UL)
|
||||
|
||||
#define CACHE_ASSOCIATIVITY_DIRECT (0UL)
|
||||
#define CACHE_ASSOCIATIVITY_4_WAY (2UL)
|
||||
#define CACHE_ASSOCIATIVITY_8_WAY (3UL)
|
||||
|
||||
#define CACHE_PRESENT (0UL)
|
||||
#define CACHE_NOT_PRESENT (1UL)
|
||||
|
||||
#define CACHE_LINE_LENGTH_32_BYTES (2UL)
|
||||
|
||||
#define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)
|
||||
#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)
|
||||
#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
|
||||
#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
|
||||
|
||||
#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
|
||||
#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
|
||||
|
||||
#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
|
||||
#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
|
||||
#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
|
||||
#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
|
||||
|
||||
#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
|
||||
#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
|
||||
#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
|
||||
#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
|
||||
|
||||
#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
|
||||
#define CACHE_TYPE_WRITE_BACK (0x0EUL)
|
||||
|
||||
#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
|
||||
#define CACHE_ARCHITECTURE_UNIFIED (0UL)
|
||||
#define CACHE_ARCHITECTURE_SEPARATE (1UL)
|
||||
|
||||
VOID
|
||||
CPSRMaskInsert (
|
||||
IN UINT32 Mask,
|
||||
IN UINT32 Value
|
||||
);
|
||||
|
||||
UINT32
|
||||
CPSRRead (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif // __ARM_LIB_PRIVATE_H__
|
89
ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
Normal file
89
ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
Normal file
@@ -0,0 +1,89 @@
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
|
||||
#
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
.globl ASM_PFX(Cp15IdCode)
|
||||
.globl ASM_PFX(Cp15CacheInfo)
|
||||
.globl ASM_PFX(ArmEnableInterrupts)
|
||||
.globl ASM_PFX(ArmDisableInterrupts)
|
||||
.globl ASM_PFX(ArmGetInterruptState)
|
||||
.globl ASM_PFX(ArmInvalidateTlb)
|
||||
.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
|
||||
.globl ASM_PFX(ArmSetDomainAccessControl)
|
||||
.globl ASM_PFX(CPSRMaskInsert)
|
||||
.globl ASM_PFX(CPSRRead)
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
ASM_PFX(Cp15IdCode):
|
||||
mrc p15,0,R0,c0,c0,0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(Cp15CacheInfo):
|
||||
mrc p15,0,R0,c0,c0,1
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmEnableInterrupts):
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x80 @Enable IRQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmDisableInterrupts):
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x80 @Disable IRQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmGetInterruptState):
|
||||
mrs R0,CPSR
|
||||
tst R0,#0x80 @Check if IRQ is enabled.
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ASM_PFX(ArmInvalidateTlb):
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c8,c7,0
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmSetTranslationTableBaseAddress):
|
||||
mcr p15,0,r0,c2,c0,0
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmSetDomainAccessControl):
|
||||
mcr p15,0,r0,c3,c0,0
|
||||
bx lr
|
||||
|
||||
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
|
||||
stmfd sp!, {r4-r12, lr} @ save all the banked registers
|
||||
mov r3, sp @ copy the stack pointer into a non-banked register
|
||||
mrs r2, cpsr @ read the cpsr
|
||||
bic r2, r2, r0 @ clear mask in the cpsr
|
||||
and r1, r1, r0 @ clear bits outside the mask in the input
|
||||
orr r2, r2, r1 @ set field
|
||||
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
|
||||
mov sp, r3 @ restore stack pointer
|
||||
ldmfd sp!, {r4-r12, lr} @ restore registers
|
||||
bx lr @ return (hopefully thumb-safe!)
|
||||
|
||||
ASM_PFX(CPSRRead):
|
||||
mrs r0, cpsr
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
90
ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
Normal file
90
ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
Normal file
@@ -0,0 +1,90 @@
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
|
||||
//
|
||||
// All rights reserved. This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
EXPORT Cp15IdCode
|
||||
EXPORT Cp15CacheInfo
|
||||
EXPORT ArmEnableInterrupts
|
||||
EXPORT ArmDisableInterrupts
|
||||
EXPORT ArmGetInterruptState
|
||||
EXPORT ArmInvalidateTlb
|
||||
EXPORT ArmSetTranslationTableBaseAddress
|
||||
EXPORT ArmSetDomainAccessControl
|
||||
EXPORT CPSRMaskInsert
|
||||
EXPORT CPSRRead
|
||||
|
||||
AREA ArmLibSupport, CODE, READONLY
|
||||
|
||||
Cp15IdCode
|
||||
mrc p15,0,R0,c0,c0,0
|
||||
bx LR
|
||||
|
||||
Cp15CacheInfo
|
||||
mrc p15,0,R0,c0,c0,1
|
||||
bx LR
|
||||
|
||||
ArmEnableInterrupts
|
||||
mrs R0,CPSR
|
||||
bic R0,R0,#0x80 ;Enable IRQ interrupts
|
||||
msr CPSR_c,R0
|
||||
bx LR
|
||||
|
||||
ArmDisableInterrupts
|
||||
mrs R0,CPSR
|
||||
orr R1,R0,#0x80 ;Disable IRQ interrupts
|
||||
msr CPSR_c,R1
|
||||
tst R0,#0x80
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ArmGetInterruptState
|
||||
mrs R0,CPSR
|
||||
tst R0,#0x80 ;Check if IRQ is enabled.
|
||||
moveq R0,#1
|
||||
movne R0,#0
|
||||
bx LR
|
||||
|
||||
ArmInvalidateTlb
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c8,c7,0
|
||||
bx lr
|
||||
|
||||
ArmSetTranslationTableBaseAddress
|
||||
mcr p15,0,r0,c2,c0,0
|
||||
bx lr
|
||||
|
||||
ArmSetDomainAccessControl
|
||||
mcr p15,0,r0,c3,c0,0
|
||||
bx lr
|
||||
|
||||
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
|
||||
stmfd sp!, {r4-r12, lr} ; save all the banked registers
|
||||
mov r3, sp ; copy the stack pointer into a non-banked register
|
||||
mrs r2, cpsr ; read the cpsr
|
||||
bic r2, r2, r0 ; clear mask in the cpsr
|
||||
and r1, r1, r0 ; clear bits outside the mask in the input
|
||||
orr r2, r2, r1 ; set field
|
||||
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
|
||||
mov sp, r3 ; restore stack pointer
|
||||
ldmfd sp!, {r4-r12, lr} ; restore registers
|
||||
bx lr ; return (hopefully thumb-safe!)
|
||||
|
||||
CPSRRead
|
||||
mrs r0, cpsr
|
||||
bx lr
|
||||
|
||||
END
|
||||
|
||||
|
106
ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c
Normal file
106
ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c
Normal file
@@ -0,0 +1,106 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
#include "ArmLibPrivate.h"
|
||||
|
||||
ARM_CACHE_TYPE
|
||||
EFIAPI
|
||||
ArmCacheType (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ARM_CACHE_TYPE_UNKNOWN;
|
||||
}
|
||||
|
||||
ARM_CACHE_ARCHITECTURE
|
||||
EFIAPI
|
||||
ArmCacheArchitecture (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return ARM_CACHE_ARCHITECTURE_UNKNOWN;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmDataCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmDataCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmInstructionCachePresent (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheSize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheAssociativity (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmInstructionCacheLineLength (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
117
ArmPkg/Library/ArmLib/Null/NullArmLib.c
Normal file
117
ArmPkg/Library/ArmLib/Null/NullArmLib.c
Normal file
@@ -0,0 +1,117 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanInvalidateDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateInstructionCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmInvalidateDataCacheEntryByMVA (
|
||||
IN UINTN Address
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanDataCacheEntryByMVA (
|
||||
IN UINTN Address
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmCleanInvalidateDataCacheEntryByMVA (
|
||||
IN UINTN Address
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmEnableDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmDisableDataCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmEnableInstructionCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmDisableInstructionCache (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Do not run code using the Null cache library.
|
||||
ASSERT(FALSE);
|
||||
}
|
26
ArmPkg/Library/ArmLib/Null/NullArmLib.inf
Normal file
26
ArmPkg/Library/ArmLib/Null/NullArmLib.inf
Normal file
@@ -0,0 +1,26 @@
|
||||
#%HEADER%
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = NullArmLib
|
||||
FILE_GUID = 00586300-0E06-4790-AC44-86C56ACBB942
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmLib
|
||||
|
||||
[Sources.common]
|
||||
../Common/ArmLibSupport.S | GCC
|
||||
../Common/ArmLibSupport.asm | RVCT
|
||||
../Common/ArmLib.c
|
||||
|
||||
NullArmLib.c
|
||||
NullArmCacheInformation.c
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
|
Reference in New Issue
Block a user