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Adding support for BeagleBoard.

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ArmPkg - Supoprt for ARM specific things that can change as the architecture changes. Plus semihosting JTAG drivers.
EmbeddedPkg - Generic support for an embeddded platform. Including a light weight command line shell.
BeagleBoardPkg - Platform specifics for BeagleBoard. SD Card works, but USB has issues. Looks like a bug in the open source USB stack (Our internal stack works fine).


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9518 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
AJFISH
2009-12-06 01:57:05 +00:00
parent f7753a96ba
commit 2ef2b01e07
294 changed files with 47954 additions and 0 deletions
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32
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf Normal file
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#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Arm9ArmLib
FILE_GUID = 375D70D3-91E0-4374-A540-68BD959EB184
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmLib
[Sources.common]
../Common/ArmLibSupport.S | GCC
../Common/ArmLibSupport.asm | RVCT
../Common/ArmLib.c
Arm9Support.S | GCC
Arm9Support.asm | RVCT
Arm9Lib.c
Arm9CacheInformation.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
MemoryAllocationLib
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

32
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf Executable file
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#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Arm9ArmLibPrePi
FILE_GUID = e9b6011f-ee15-4e59-ab8f-a819a081fa54
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmLib
[Sources.common]
../Common/ArmLibSupport.S | GCC
../Common/ArmLibSupport.asm | RVCT
../Common/ArmLib.c
Arm9Support.S | GCC
Arm9Support.asm | RVCT
Arm9Lib.c
Arm9CacheInformation.c
[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
PrePiLib
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

164
ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Library/ArmLib.h>
#include "ArmLibPrivate.h"
ARM_CACHE_TYPE
EFIAPI
ArmCacheType (
VOID
)
{
switch (CACHE_TYPE(Cp15CacheInfo()))
{
case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;
default: return ARM_CACHE_TYPE_UNKNOWN;
}
}
ARM_CACHE_ARCHITECTURE
EFIAPI
ArmCacheArchitecture (
VOID
)
{
switch (CACHE_ARCHITECTURE(Cp15CacheInfo()))
{
case CACHE_ARCHITECTURE_UNIFIED: return ARM_CACHE_ARCHITECTURE_UNIFIED;
case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;
default: return ARM_CACHE_ARCHITECTURE_UNKNOWN;
}
}
BOOLEAN
EFIAPI
ArmDataCachePresent (
VOID
)
{
switch (DATA_CACHE_PRESENT(Cp15CacheInfo()))
{
case CACHE_PRESENT: return TRUE;
case CACHE_NOT_PRESENT: return FALSE;
default: return FALSE;
}
}
UINTN
EFIAPI
ArmDataCacheSize (
VOID
)
{
switch (DATA_CACHE_SIZE(Cp15CacheInfo()))
{
case CACHE_SIZE_4_KB: return 4 * 1024;
case CACHE_SIZE_8_KB: return 8 * 1024;
case CACHE_SIZE_16_KB: return 16 * 1024;
case CACHE_SIZE_32_KB: return 32 * 1024;
case CACHE_SIZE_64_KB: return 64 * 1024;
case CACHE_SIZE_128_KB: return 128 * 1024;
default: return 0;
}
}
UINTN
EFIAPI
ArmDataCacheAssociativity (
VOID
)
{
switch (DATA_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))
{
case CACHE_ASSOCIATIVITY_4_WAY: return 4;
case CACHE_ASSOCIATIVITY_DIRECT: return 1;
default: return 0;
}
}
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
)
{
switch (DATA_CACHE_LINE_LENGTH(Cp15CacheInfo()))
{
case CACHE_LINE_LENGTH_32_BYTES: return 32;
default: return 0;
}
}
BOOLEAN
EFIAPI
ArmInstructionCachePresent (
VOID
)
{
switch (INSTRUCTION_CACHE_PRESENT(Cp15CacheInfo()))
{
case CACHE_PRESENT: return TRUE;
case CACHE_NOT_PRESENT: return FALSE;
default: return FALSE;
}
}
UINTN
EFIAPI
ArmInstructionCacheSize (
VOID
)
{
switch (INSTRUCTION_CACHE_SIZE(Cp15CacheInfo()))
{
case CACHE_SIZE_4_KB: return 4 * 1024;
case CACHE_SIZE_8_KB: return 8 * 1024;
case CACHE_SIZE_16_KB: return 16 * 1024;
case CACHE_SIZE_32_KB: return 32 * 1024;
case CACHE_SIZE_64_KB: return 64 * 1024;
case CACHE_SIZE_128_KB: return 128 * 1024;
default: return 0;
}
}
UINTN
EFIAPI
ArmInstructionCacheAssociativity (
VOID
)
{
switch (INSTRUCTION_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))
{
case CACHE_ASSOCIATIVITY_8_WAY: return 8;
case CACHE_ASSOCIATIVITY_4_WAY: return 4;
case CACHE_ASSOCIATIVITY_DIRECT: return 1;
default: return 0;
}
}
UINTN
EFIAPI
ArmInstructionCacheLineLength (
VOID
)
{
switch (INSTRUCTION_CACHE_LINE_LENGTH(Cp15CacheInfo()))
{
case CACHE_LINE_LENGTH_32_BYTES: return 32;
default: return 0;
}
}

118
ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Chipset/ARM926EJ-S.h>
#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
VOID
FillTranslationTable (
IN UINT32 *TranslationTable,
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
)
{
UINT32 *Entry;
UINTN Sections;
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
default:
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
break;
}
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
for (Index = 0; Index < Sections; Index++)
{
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
}
}
VOID
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
VOID *TranslationTable;
// Allocate pages for translation table.
TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
ArmInvalidateTlb();
ArmDisableDataCache();
ArmDisableInstructionCache();
ArmDisableMmu();
// Make sure nothing sneaked into the cache
ArmCleanInvalidateDataCache();
ArmInvalidateInstructionCache();
while (MemoryTable->Length != 0) {
FillTranslationTable(TranslationTable, MemoryTable);
MemoryTable++;
}
ArmSetTranslationTableBaseAddress(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
DOMAIN_ACCESS_CONTROL_NONE(12) |
DOMAIN_ACCESS_CONTROL_NONE(11) |
DOMAIN_ACCESS_CONTROL_NONE(10) |
DOMAIN_ACCESS_CONTROL_NONE( 9) |
DOMAIN_ACCESS_CONTROL_NONE( 8) |
DOMAIN_ACCESS_CONTROL_NONE( 7) |
DOMAIN_ACCESS_CONTROL_NONE( 6) |
DOMAIN_ACCESS_CONTROL_NONE( 5) |
DOMAIN_ACCESS_CONTROL_NONE( 4) |
DOMAIN_ACCESS_CONTROL_NONE( 3) |
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();
}

128
ArmPkg/Library/ArmLib/Arm9/Arm9Support.S Normal file
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#------------------------------------------------------------------------------
#
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
.globl ASM_PFX(ArmCleanInvalidateDataCache)
.globl ASM_PFX(ArmCleanDataCache)
.globl ASM_PFX(ArmInvalidateDataCache)
.globl ASM_PFX(ArmInvalidateInstructionCache)
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmEnableMmu)
.globl ASM_PFX(ArmDisableMmu)
.globl ASM_PFX(ArmEnableDataCache)
.globl ASM_PFX(ArmDisableDataCache)
.globl ASM_PFX(ArmEnableInstructionCache)
.globl ASM_PFX(ArmDisableInstructionCache)
.globl ASM_PFX(ArmEnableBranchPrediction)
.globl ASM_PFX(ArmDisableBranchPrediction)
.set DC_ON, (1<<2)
.set IC_ON, (1<<12)
#------------------------------------------------------------------------------
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
bx lr
ASM_PFX(ArmEnableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
orr r0,r0,r1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
bic r0,r0,r1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmInvalidateInstructionCache):
mov r0,#0
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
@Also flushes the branch target cache.
mov r0,#0
mcr p15,0,r0,c7,c10,4 @Data write buffer
bx LR
ASM_PFX(ArmEnableMmu):
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ASM_PFX(ArmDisableMmu):
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmEnableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
bic R0,R0,R1 @Clear C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmCleanDataCache):
mrc p15,0,r15,c7,c10,3
bne ASM_PFX(ArmCleanDataCache)
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmInvalidateDataCache):
mov R0,#0
mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmCleanInvalidateDataCache):
mrc p15,0,r15,c7,c14,3
bne ASM_PFX(ArmCleanInvalidateDataCache)
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmEnableBranchPrediction):
bx LR @Branch prediction is not supported.
ASM_PFX(ArmDisableBranchPrediction):
bx LR @Branch prediction is not supported.
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

129
ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm Normal file
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//------------------------------------------------------------------------------
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT ArmCleanInvalidateDataCache
EXPORT ArmCleanDataCache
EXPORT ArmInvalidateDataCache
EXPORT ArmInvalidateInstructionCache
EXPORT ArmInvalidateDataCacheEntryByMVA
EXPORT ArmCleanDataCacheEntryByMVA
EXPORT ArmCleanInvalidateDataCacheEntryByMVA
EXPORT ArmEnableMmu
EXPORT ArmDisableMmu
EXPORT ArmEnableDataCache
EXPORT ArmDisableDataCache
EXPORT ArmEnableInstructionCache
EXPORT ArmDisableInstructionCache
EXPORT ArmEnableBranchPrediction
EXPORT ArmDisableBranchPrediction
DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 )
AREA ArmCacheLib, CODE, READONLY
PRESERVE8
ArmInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
BX lr
ArmCleanDataCacheEntryByMVA
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
BX lr
ArmCleanInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
BX lr
ArmEnableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit.
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmInvalidateInstructionCache
MOV R0,#0
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmEnableMmu
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
bx LR
ArmDisableMmu
mrc p15,0,R0,c1,c0,0
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0
mov R0,#0
mcr p15,0,R0,c7,c10,4 ;Drain write buffer
bx LR
ArmEnableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmCleanDataCache
MRC p15,0,r15,c7,c10,3
BNE ArmCleanDataCache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmInvalidateDataCache
MOV R0,#0
MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmCleanInvalidateDataCache
MRC p15,0,r15,c7,c14,3
BNE ArmCleanInvalidateDataCache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmEnableBranchPrediction
bx LR ;Branch prediction is not supported.
ArmDisableBranchPrediction
bx LR ;Branch prediction is not supported.
END