Adding support for BeagleBoard.
ArmPkg - Supoprt for ARM specific things that can change as the architecture changes. Plus semihosting JTAG drivers. EmbeddedPkg - Generic support for an embeddded platform. Including a light weight command line shell. BeagleBoardPkg - Platform specifics for BeagleBoard. SD Card works, but USB has issues. Looks like a bug in the open source USB stack (Our internal stack works fine). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9518 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
AJFISH
288
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c
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288
ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c
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/** @file
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Copyright (c) 2008-2009, Apple Inc. All rights reserved.
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Chipset/Cortex-A8.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include "ArmCortexALib.h"
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VOID
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FillTranslationTable (
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IN UINT32 *TranslationTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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UINT32 *Entry;
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UINTN Sections;
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UINTN Index;
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UINT32 Attributes;
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UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
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switch (MemoryRegion->Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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Attributes = TT_DESCRIPTOR_SECTION_DEVICE;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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default:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
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break;
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}
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Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
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for (Index = 0; Index < Sections; Index++)
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{
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*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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}
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}
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VOID
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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)
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{
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VOID *TranslationTable;
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// Allocate pages for translation table.
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TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
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TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
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if (TranslationTableBase != NULL) {
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*TranslationTableBase = TranslationTable;
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}
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if (TranslationTableBase != NULL) {
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*TranslationTableSize = TRANSLATION_TABLE_SIZE;
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}
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ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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ArmInvalidateTlb();
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ArmDisableDataCache();
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ArmDisableInstructionCache();
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ArmDisableMmu();
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// Make sure nothing sneaked into the cache
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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while (MemoryTable->Length != 0) {
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FillTranslationTable(TranslationTable, MemoryTable);
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MemoryTable++;
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}
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ArmSetTranslationTableBaseAddress(TranslationTable);
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ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
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DOMAIN_ACCESS_CONTROL_NONE(14) |
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DOMAIN_ACCESS_CONTROL_NONE(13) |
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DOMAIN_ACCESS_CONTROL_NONE(12) |
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DOMAIN_ACCESS_CONTROL_NONE(11) |
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DOMAIN_ACCESS_CONTROL_NONE(10) |
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DOMAIN_ACCESS_CONTROL_NONE( 9) |
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DOMAIN_ACCESS_CONTROL_NONE( 8) |
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DOMAIN_ACCESS_CONTROL_NONE( 7) |
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DOMAIN_ACCESS_CONTROL_NONE( 6) |
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DOMAIN_ACCESS_CONTROL_NONE( 5) |
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DOMAIN_ACCESS_CONTROL_NONE( 4) |
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DOMAIN_ACCESS_CONTROL_NONE( 3) |
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DOMAIN_ACCESS_CONTROL_NONE( 2) |
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DOMAIN_ACCESS_CONTROL_NONE( 1) |
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DOMAIN_ACCESS_CONTROL_MANAGER(0));
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ArmEnableInstructionCache();
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ArmEnableDataCache();
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ArmEnableMmu();
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}
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ARM_CACHE_TYPE
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EFIAPI
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ArmCacheType (
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VOID
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)
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{
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return ARM_CACHE_TYPE_WRITE_BACK;
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}
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ARM_CACHE_ARCHITECTURE
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EFIAPI
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ArmCacheArchitecture (
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VOID
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)
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{
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return ARM_CACHE_ARCHITECTURE_SEPARATE;
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}
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BOOLEAN
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EFIAPI
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ArmDataCachePresent (
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VOID
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)
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{
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return TRUE;
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}
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UINTN
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EFIAPI
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ArmDataCacheSize (
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VOID
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)
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{
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return 16 * 1024;
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}
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UINTN
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EFIAPI
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ArmDataCacheAssociativity (
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VOID
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)
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{
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return 4;
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}
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UINTN
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ArmDataCacheSets (
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VOID
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)
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{
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return 64;
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}
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UINTN
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EFIAPI
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ArmDataCacheLineLength (
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VOID
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)
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{
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return 64;
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}
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BOOLEAN
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EFIAPI
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ArmInstructionCachePresent (
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VOID
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)
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{
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return TRUE;
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}
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UINTN
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EFIAPI
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ArmInstructionCacheSize (
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VOID
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)
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{
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return 16 * 1024;
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}
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UINTN
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EFIAPI
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ArmInstructionCacheAssociativity (
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VOID
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)
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{
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return 4;
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}
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UINTN
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EFIAPI
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ArmInstructionCacheLineLength (
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VOID
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)
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{
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return 64;
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}
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VOID
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ArmCortexADataCacheOperation (
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IN ARM_CORTEX_A_CACHE_OPERATION DataCacheOperation
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)
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{
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UINTN Set;
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UINTN SetCount;
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UINTN SetShift;
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UINTN Way;
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UINTN WayCount;
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UINTN WayShift;
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UINT32 SetWayFormat;
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UINTN SavedInterruptState;
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SetCount = ArmDataCacheSets();
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WayCount = ArmDataCacheAssociativity();
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// Cortex-A8 Manual, System Control Coprocessor chapter
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SetShift = 6;
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WayShift = 32 - LowBitSet32 ((UINT32)WayCount);
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SavedInterruptState = ArmDisableInterrupts();
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for (Way = 0; Way < WayCount; Way++) {
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for (Set = 0; Set < SetCount; Set++) {
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// Build the format that the CP15 instruction can understand
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SetWayFormat = (Way << WayShift) | (Set << SetShift);
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// Pass it through
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(*DataCacheOperation)(SetWayFormat);
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}
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}
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ArmDrainWriteBuffer();
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if (SavedInterruptState) {
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ArmEnableInterrupts();
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}
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}
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VOID
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EFIAPI
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ArmInvalidateDataCache (
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VOID
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)
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{
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ArmCortexADataCacheOperation(ArmInvalidateDataCacheEntryBySetWay);
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}
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VOID
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EFIAPI
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ArmCleanInvalidateDataCache (
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VOID
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)
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{
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ArmCortexADataCacheOperation(ArmCleanInvalidateDataCacheEntryBySetWay);
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}
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VOID
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EFIAPI
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ArmCleanDataCache (
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VOID
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)
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{
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ArmCortexADataCacheOperation(ArmCleanDataCacheEntryBySetWay);
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}
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