Adding support for BeagleBoard.
ArmPkg - Supoprt for ARM specific things that can change as the architecture changes. Plus semihosting JTAG drivers. EmbeddedPkg - Generic support for an embeddded platform. Including a light weight command line shell. BeagleBoardPkg - Platform specifics for BeagleBoard. SD Card works, but USB has issues. Looks like a bug in the open source USB stack (Our internal stack works fine). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9518 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
60
ArmPkg/Library/ArmLib/Common/ArmLib.c
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60
ArmPkg/Library/ArmLib/Common/ArmLib.c
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/** @file
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Copyright (c) 2008-2009, Apple Inc. All rights reserved.
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include "ArmLibPrivate.h"
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VOID
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EFIAPI
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ArmCacheInformation (
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OUT ARM_CACHE_INFO *CacheInfo
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)
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{
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if (CacheInfo != NULL) {
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CacheInfo->Type = ArmCacheType();
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CacheInfo->Architecture = ArmCacheArchitecture();
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CacheInfo->DataCachePresent = ArmDataCachePresent();
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CacheInfo->DataCacheSize = ArmDataCacheSize();
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CacheInfo->DataCacheAssociativity = ArmDataCacheAssociativity();
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CacheInfo->DataCacheLineLength = ArmDataCacheLineLength();
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CacheInfo->InstructionCachePresent = ArmInstructionCachePresent();
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CacheInfo->InstructionCacheSize = ArmInstructionCacheSize();
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CacheInfo->InstructionCacheAssociativity = ArmInstructionCacheAssociativity();
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CacheInfo->InstructionCacheLineLength = ArmInstructionCacheLineLength();
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}
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}
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VOID
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EFIAPI
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ArmSwitchProcessorMode (
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IN ARM_PROCESSOR_MODE Mode
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)
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{
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CPSRMaskInsert(ARM_PROCESSOR_MODE_MASK, Mode);
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}
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ARM_PROCESSOR_MODE
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EFIAPI
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ArmProcessorMode (
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VOID
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)
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{
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return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);
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}
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70
ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
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70
ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
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/** @file
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Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __ARM_LIB_PRIVATE_H__
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#define __ARM_LIB_PRIVATE_H__
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#define CACHE_SIZE_4_KB (3UL)
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#define CACHE_SIZE_8_KB (4UL)
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#define CACHE_SIZE_16_KB (5UL)
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#define CACHE_SIZE_32_KB (6UL)
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#define CACHE_SIZE_64_KB (7UL)
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#define CACHE_SIZE_128_KB (8UL)
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#define CACHE_ASSOCIATIVITY_DIRECT (0UL)
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#define CACHE_ASSOCIATIVITY_4_WAY (2UL)
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#define CACHE_ASSOCIATIVITY_8_WAY (3UL)
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#define CACHE_PRESENT (0UL)
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#define CACHE_NOT_PRESENT (1UL)
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#define CACHE_LINE_LENGTH_32_BYTES (2UL)
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#define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)
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#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)
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#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
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#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
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#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
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#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
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#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
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#define CACHE_TYPE_WRITE_BACK (0x0EUL)
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#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
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#define CACHE_ARCHITECTURE_UNIFIED (0UL)
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#define CACHE_ARCHITECTURE_SEPARATE (1UL)
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VOID
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CPSRMaskInsert (
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IN UINT32 Mask,
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IN UINT32 Value
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);
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UINT32
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CPSRRead (
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VOID
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);
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#endif // __ARM_LIB_PRIVATE_H__
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89
ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
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89
ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
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#
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# All rights reserved. This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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.globl ASM_PFX(Cp15IdCode)
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.globl ASM_PFX(Cp15CacheInfo)
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.globl ASM_PFX(ArmEnableInterrupts)
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.globl ASM_PFX(ArmDisableInterrupts)
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.globl ASM_PFX(ArmGetInterruptState)
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.globl ASM_PFX(ArmInvalidateTlb)
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.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
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.globl ASM_PFX(ArmSetDomainAccessControl)
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.globl ASM_PFX(CPSRMaskInsert)
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.globl ASM_PFX(CPSRRead)
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#------------------------------------------------------------------------------
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ASM_PFX(Cp15IdCode):
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mrc p15,0,R0,c0,c0,0
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bx LR
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ASM_PFX(Cp15CacheInfo):
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mrc p15,0,R0,c0,c0,1
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bx LR
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ASM_PFX(ArmEnableInterrupts):
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mrs R0,CPSR
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bic R0,R0,#0x80 @Enable IRQ interrupts
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msr CPSR_c,R0
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bx LR
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ASM_PFX(ArmDisableInterrupts):
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mrs R0,CPSR
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orr R1,R0,#0x80 @Disable IRQ interrupts
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msr CPSR_c,R1
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tst R0,#0x80
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_PFX(ArmGetInterruptState):
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mrs R0,CPSR
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tst R0,#0x80 @Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ASM_PFX(ArmInvalidateTlb):
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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bx lr
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ASM_PFX(ArmSetTranslationTableBaseAddress):
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mcr p15,0,r0,c2,c0,0
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bx lr
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ASM_PFX(ArmSetDomainAccessControl):
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mcr p15,0,r0,c3,c0,0
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bx lr
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ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
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stmfd sp!, {r4-r12, lr} @ save all the banked registers
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mov r3, sp @ copy the stack pointer into a non-banked register
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mrs r2, cpsr @ read the cpsr
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bic r2, r2, r0 @ clear mask in the cpsr
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and r1, r1, r0 @ clear bits outside the mask in the input
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orr r2, r2, r1 @ set field
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msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
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mov sp, r3 @ restore stack pointer
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ldmfd sp!, {r4-r12, lr} @ restore registers
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bx lr @ return (hopefully thumb-safe!)
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ASM_PFX(CPSRRead):
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mrs r0, cpsr
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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90
ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
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90
ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
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//
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// All rights reserved. This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT Cp15IdCode
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EXPORT Cp15CacheInfo
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EXPORT ArmEnableInterrupts
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EXPORT ArmDisableInterrupts
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EXPORT ArmGetInterruptState
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EXPORT ArmInvalidateTlb
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EXPORT ArmSetTranslationTableBaseAddress
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EXPORT ArmSetDomainAccessControl
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EXPORT CPSRMaskInsert
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EXPORT CPSRRead
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AREA ArmLibSupport, CODE, READONLY
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Cp15IdCode
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mrc p15,0,R0,c0,c0,0
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bx LR
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Cp15CacheInfo
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mrc p15,0,R0,c0,c0,1
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bx LR
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ArmEnableInterrupts
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mrs R0,CPSR
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bic R0,R0,#0x80 ;Enable IRQ interrupts
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msr CPSR_c,R0
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bx LR
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ArmDisableInterrupts
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mrs R0,CPSR
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orr R1,R0,#0x80 ;Disable IRQ interrupts
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msr CPSR_c,R1
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tst R0,#0x80
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmGetInterruptState
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mrs R0,CPSR
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tst R0,#0x80 ;Check if IRQ is enabled.
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moveq R0,#1
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movne R0,#0
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bx LR
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ArmInvalidateTlb
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mov r0,#0
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mcr p15,0,r0,c8,c7,0
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bx lr
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ArmSetTranslationTableBaseAddress
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mcr p15,0,r0,c2,c0,0
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bx lr
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ArmSetDomainAccessControl
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mcr p15,0,r0,c3,c0,0
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bx lr
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CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
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stmfd sp!, {r4-r12, lr} ; save all the banked registers
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mov r3, sp ; copy the stack pointer into a non-banked register
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mrs r2, cpsr ; read the cpsr
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bic r2, r2, r0 ; clear mask in the cpsr
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and r1, r1, r0 ; clear bits outside the mask in the input
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orr r2, r2, r1 ; set field
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msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
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mov sp, r3 ; restore stack pointer
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ldmfd sp!, {r4-r12, lr} ; restore registers
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bx lr ; return (hopefully thumb-safe!)
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CPSRRead
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mrs r0, cpsr
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bx lr
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END
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