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Adding support for BeagleBoard.

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ArmPkg - Supoprt for ARM specific things that can change as the architecture changes. Plus semihosting JTAG drivers.
EmbeddedPkg - Generic support for an embeddded platform. Including a light weight command line shell.
BeagleBoardPkg - Platform specifics for BeagleBoard. SD Card works, but USB has issues. Looks like a bug in the open source USB stack (Our internal stack works fine).


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9518 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
AJFISH
2009-12-06 01:57:05 +00:00
parent f7753a96ba
commit 2ef2b01e07
294 changed files with 47954 additions and 0 deletions
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366
BeagleBoardPkg/AppleBeagleBoardPkg.dsc Normal file
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#/** @file
# Beagle board package.
#
# Copyright (c) 2009, Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = AppleBeagleBoardPkg
PLATFORM_GUID = 1C1D4FD7-703A-4DD5-A97B-FB794921859E
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/AppleBeagleBoard
SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = BeagleBoardPkg/AppleBeagleBoardPkg.fdf
[LibraryClasses.common]
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
BeagleBoardSystemLib|BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf
EfiResetSystemLib|BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
EblCmdLib|BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf
EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
SerialPortLib|BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf
SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
#
# Assume everything is fixed at build
#
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
UsbLib|AppleCommonPkg/Library/AppleUsbLib/AppleUsbDxeLib.inf
EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
GdbSerialLib|BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
[LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
[LibraryClasses.common.PEI_CORE]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
[LibraryClasses.common.DXE_CORE]
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
[LibraryClasses.common.DXE_DRIVER]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
[LibraryClasses.common.UEFI_APPLICATION]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
[LibraryClasses.common.UEFI_DRIVER]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
[BuildOptions]
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv6 -march=armv6
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv6
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv6
RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8
RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsFeatureFlag.common]
gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
#
# Control what commands are supported from the UI
# Turn these on and off to add features or save size
#
gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
#
# Beagle board Specific PCDs
#
[PcdsFixedAtBuild.common]
gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"AppleEFI"
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
gEmbeddedTokenSpaceGuid.PcdPrePiTempMemorySize|0
gEmbeddedTokenSpaceGuid.PcdPrePiBfvBaseAddress|0
gEmbeddedTokenSpaceGuid.PcdPrePiBfvSize|0
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0
gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0
#
# Optional feature to help prevent EFI memory map fragments
# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
# Values are in EFI Pages (4K). DXE Core will make sure that
# at least this much of each type of memory can be allocated
# from a single memory range. This way you only end up with
# maximum of two fragements for each type in the memory map
# (the memory used, and the free memory that was prereserved
# but not used).
#
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
#
# Beagle board Specific PCDs
#
gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000
gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack
gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize|0x00000000
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000
gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset|0x6E000000
gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base|0x4809C000
# Console
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart|3
# Timers
# gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|OMAP3530_GPTIMER3
gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|3
# gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|OMAP3530_GPTIMER4
gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|4
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds|77
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterFrequencyInHz|13000000
#
# ARM Pcds
#
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
#
################################################################################
[Components.common]
#
# SEC
#
BeagleBoardPkg/Sec/Sec.inf
#
# DXE
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
}
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf
#
# Semi-hosting filesystem
#
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
#
# FAT filesystem + GPT/MBR partitioning
#
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
EnhancedFat/FatDxe/FatDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
#
# USB
#
BeagleBoardPkg/PciEmulation/PciEmulation.inf
AppleCommonPkg/Bus/Pci/EhciDxe/Ehci.inf
AppleCommonPkg/Bus/Usb/UsbBotDxe/UsbBot.inf
AppleCommonPkg/Bus/Usb/UsbCbiDxe/Cbi0/UsbCbi0.inf
AppleCommonPkg/Bus/Usb/UsbCbiDxe/Cbi1/UsbCbi1.inf
AppleCommonPkg/Bus/Usb/UsbBusDxe/UsbBus.inf
AppleCommonPkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorage.inf
#NOTE: Open source EHCI stack doesn't work on Beagleboard.
#NOTE: UsbBus and UsbMassStorage don't work using iPhond SDK tool chain.
#MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
#MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
#MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# Nand Flash
#
BeagleBoardPkg/Flash/Flash.inf
#
# MMC/SD
#
BeagleBoardPkg/MMCHSDxe/MMCHS.inf
#
# I2C
#
BeagleBoardPkg/SmbusDxe/Smbus.inf
#
# SoC Drivers
#
BeagleBoardPkg/Gpio/Gpio.inf
BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
BeagleBoardPkg/TimerDxe/TimerDxe.inf
#
# Power IC
#
BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
#
# Application
#
EmbeddedPkg/Ebl/Ebl.inf
#
# Bds
#
BeagleBoardPkg/Bds/Bds.inf
#
# Gdb Stub
#
EmbeddedPkg/GdbStub/GdbStub.inf
ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf

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BeagleBoardPkg/AppleBeagleBoardPkg.fdf Normal file
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# FLASH layout file for Beagle board.
#
# Copyright (c) 2009, Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into the Flash Device Image. Each FD section
# defines one flash "device" image. A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash" image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.BeagleBoard_EFI]
BaseAddress = 0x80008000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress #The base address of the FLASH Device.
Size = 0x00080000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize #The size in bytes of the FLASH Device
ErasePolarity = 1
BlockSize = 0x40
NumBlocks = 0x2000
################################################################################
#
# Following are lists of FD Region layout which correspond to the locations of different
# images within the flash device.
#
# Regions must be defined in ascending order and may not overlap.
#
# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
# the pipe "|" character, followed by the size of the region, also in hex with the leading
# "0x" characters. Like:
# Offset|Size
# PcdOffsetCName|PcdSizeCName
# RegionType <FV, DATA, or FILE>
#
################################################################################
# 512 bytes of configuration header & 8 bytes of image header
0x00000000|0x00000208
0x00000208|0x0007FDF8
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
FV = FVMAIN_COMPACT
################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file. This section also defines order the components and modules are positioned
# within the image. The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FvMain]
BlockSize = 0x40
NumBlocks = 0x9000
FvAlignment = 8 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
#
# PI DXE Drivers producing Architectural Protocols (EFI Services)
#
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf
#
# Semi-hosting filesystem
#
INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
#
# Nand Flash
#
INF BeagleBoardPkg/Flash/Flash.inf
#
# MMC/SD
#
INF BeagleBoardPkg/MMCHSDxe/MMCHS.inf
#
# I2C
#
INF BeagleBoardPkg/SmbusDxe/Smbus.inf
#
# SoC Drivers
#
INF BeagleBoardPkg/Gpio/Gpio.inf
INF BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
INF BeagleBoardPkg/TimerDxe/TimerDxe.inf
#
# Power IC
#
INF BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
#
# FAT filesystem + GPT/MBR partitioning
#
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF EnhancedFat/FatDxe/FatDxe.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
#
# USB Support
#
INF BeagleBoardPkg/PciEmulation/PciEmulation.inf
INF AppleCommonPkg/Bus/Pci/EhciDxe/Ehci.inf
INF AppleCommonPkg/Bus/Usb/UsbBotDxe/UsbBot.inf
INF AppleCommonPkg/Bus/Usb/UsbCbiDxe/Cbi0/UsbCbi0.inf
INF AppleCommonPkg/Bus/Usb/UsbCbiDxe/Cbi1/UsbCbi1.inf
INF AppleCommonPkg/Bus/Usb/UsbBusDxe/UsbBus.inf
INF AppleCommonPkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorage.inf
#NOTE: Open source EHCI stack doesn't work on Beagleboard.
#NOTE: UsbBus and UsbMassStorage don't work using iPhond SDK tool chain.
#INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
#INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
#INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# UEFI application (Shell Embedded Boot Loader)
#
INF EmbeddedPkg/Ebl/Ebl.inf
#
# Bds
#
INF BeagleBoardPkg/Bds/Bds.inf
#
# Gdb Stub
#
#INF ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
#INF ApplePkg/Universal/GdbStub/GdbStub.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
INF BeagleBoardPkg/Sec/Sec.inf
INF MdeModulePkg/Core/Dxe/DxeMain.inf
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
}
}
################################################################################
#
# Rules are use with the [FV] section's module INF type to define
# how an FFS file is created for a given INF file. The following Rule are the default
# rules for the different module type. User can add the customized rules to define the
# content of the FFS file.
#
################################################################################
############################################################################
# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
############################################################################
#
#[Rule.Common.DXE_DRIVER]
# FILE DRIVER = $(NAMED_GUID) {
# DXE_DEPEX DXE_DEPEX Optional |.depex
# COMPRESS PI_STD {
# GUIDED {
# PE32 PE32 |.efi
# UI STRING="$(MODULE_NAME)" Optional
# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
# }
# }
# }
#
############################################################################
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 8 |.efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE |.efi
UI STRING ="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM.TIANOCOMPRESSED]
FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
PEI_DEPEX PEI_DEPEX Optional |.depex
GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
}
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
}
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_RUNTIME_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 |.efi
}

70
BeagleBoardPkg/Bds/Bds.inf Normal file
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#%HEADER%
#/** @file
#
# Component discription file for Bds module
#
# Copyright (c) 2009 Apple, Inc. All rights reserved.
#
# This document is the property of Apple, Inc.
# It is considered confidential and proprietary.
#
# This document may not be reproduced or transmitted in any form,
# in whole or in part, without the express written permission of
# Apple, Inc.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardBds
FILE_GUID = 934431fe-5745-402e-913d-17b4434eb0f3
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = BdsInitialize
[Sources.common]
BdsEntry.c
FirmwareVolume.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
DevicePathLib
BaseLib
HobLib
UefiRuntimeServicesTableLib
ReportStatusCodeLib
PerformanceLib
DxeServicesTableLib
MemoryAllocationLib
UefiLib
UefiBootServicesTableLib
BaseMemoryLib
DebugLib
PrintLib
UefiDriverEntryPoint
[Guids]
[Protocols]
gEfiBdsArchProtocolGuid
gEfiSimpleTextInProtocolGuid
gEfiSimpleTextOutProtocolGuid
gEfiSerialIoProtocolGuid
gEfiDevicePathProtocolGuid
gEfiSimpleFileSystemProtocolGuid
gEfiUsbIoProtocolGuid
gEfiFirmwareVolume2ProtocolGuid
[FeaturePcd]
[FixedPcd]
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
[Depex]
TRUE

240
BeagleBoardPkg/Bds/BdsEntry.c Normal file
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/** @file
The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements
of the UEFI specification as it is designed to implement an embedded systmes
propriatary boot scheme.
This template assume a DXE driver produces a SerialIo protocol not using the EFI
driver module and it will attempt to connect a console on top of this.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BdsEntry.h"
BOOLEAN gConsolePresent = FALSE;
EFI_HANDLE mBdsImageHandle = NULL;
EFI_BDS_ARCH_PROTOCOL gBdsProtocol = {
BdsEntry,
};
/**
This function uses policy data from the platform to determine what operating
system or system utility should be loaded and invoked. This function call
also optionally make the use of user input to determine the operating system
or system utility to be loaded and invoked. When the DXE Core has dispatched
all the drivers on the dispatch queue, this function is called. This
function will attempt to connect the boot devices required to load and invoke
the selected operating system or system utility. During this process,
additional firmware volumes may be discovered that may contain addition DXE
drivers that can be dispatched by the DXE Core. If a boot device cannot be
fully connected, this function calls the DXE Service Dispatch() to allow the
DXE drivers from any newly discovered firmware volumes to be dispatched.
Then the boot device connection can be attempted again. If the same boot
device connection operation fails twice in a row, then that boot device has
failed, and should be skipped. This function should never return.
@param This The EFI_BDS_ARCH_PROTOCOL instance.
@return None.
**/
VOID
EFIAPI
BdsEntry (
IN EFI_BDS_ARCH_PROTOCOL *This
)
{
EFI_STATUS Status;
UINTN NoHandles;
EFI_HANDLE *Buffer;
EFI_HANDLE FvHandle;
EFI_HANDLE ImageHandle;
EFI_HANDLE UsbDeviceHandle;
EFI_GUID NameGuid;
UINTN Size;
UINTN HandleCount;
UINTN OldHandleCount;
EFI_HANDLE *HandleBuffer;
UINTN Index;
EFI_DEVICE_PATH_PROTOCOL *LoadImageDevicePath;
EFI_DEVICE_PATH_PROTOCOL *FileSystemDevicePath;
//
// Now do the EFI stuff
//
Size = 0x100;
gST->FirmwareVendor = AllocateRuntimePool (Size);
ASSERT (gST->FirmwareVendor != NULL);
UnicodeSPrint (gST->FirmwareVendor, Size, L"BeagleBoard EFI %a %a", __DATE__, __TIME__);
//
// Now we need to setup the EFI System Table with information about the console devices.
// This code is normally in the console spliter driver on platforms that support multiple
// consoles at the same time
//
Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextOutProtocolGuid, NULL, &NoHandles, &Buffer);
if (!EFI_ERROR (Status)) {
// Use the first SimpleTextOut we find and update the EFI System Table
gST->ConsoleOutHandle = Buffer[0];
gST->StandardErrorHandle = Buffer[0];
Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextOutProtocolGuid, (VOID **)&gST->ConOut);
ASSERT_EFI_ERROR (Status);
gST->StdErr = gST->ConOut;
gST->ConOut->OutputString (gST->ConOut, L"BDS: Console Started!!!!\n\r");
FreePool (Buffer);
gConsolePresent = TRUE;
}
Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextInProtocolGuid, NULL, &NoHandles, &Buffer);
if (!EFI_ERROR (Status)) {
// Use the first SimpleTextIn we find and update the EFI System Table
gST->ConsoleInHandle = Buffer[0];
Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextInProtocolGuid, (VOID **)&gST->ConIn);
ASSERT_EFI_ERROR (Status);
FreePool (Buffer);
}
//
// We now have EFI Consoles up and running. Print () will work now. DEBUG () and ASSERT () worked
// prior to this point as they were configured to use a more primative output scheme.
//
//
//Perform Connect
//
HandleCount = 0;
while (1) {
OldHandleCount = HandleCount;
Status = gBS->LocateHandleBuffer (
AllHandles,
NULL,
NULL,
&HandleCount,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
break;
}
if (HandleCount == OldHandleCount) {
break;
}
for (Index = 0; Index < HandleCount; Index++) {
gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);
}
}
//Locate handles for SimpleFileSystem protocol
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiSimpleFileSystemProtocolGuid,
NULL,
&HandleCount,
&HandleBuffer
);
if (!EFI_ERROR(Status)) {
for (Index = 0; Index < HandleCount; Index++) {
//Get the device path
FileSystemDevicePath = DevicePathFromHandle(HandleBuffer[Index]);
if (FileSystemDevicePath == NULL) {
continue;
}
//Check if UsbIo is on any handles in the device path.
Status = gBS->LocateDevicePath(&gEfiUsbIoProtocolGuid, &FileSystemDevicePath, &UsbDeviceHandle);
if (EFI_ERROR(Status)) {
continue;
}
//Check if Usb stick has a magic EBL file.
LoadImageDevicePath = FileDevicePath(HandleBuffer[Index], L"Ebl.efi");
Status = gBS->LoadImage (TRUE, gImageHandle, LoadImageDevicePath, NULL, 0, &ImageHandle);
if (EFI_ERROR(Status)) {
continue;
}
//Boot to Shell on USB stick.
Status = gBS->StartImage (ImageHandle, NULL, NULL);
if (EFI_ERROR(Status)) {
continue;
}
}
}
//
// Normal UEFI behavior is to process Globally Defined Variables as defined in Chapter 3
// (Boot Manager) of the UEFI specification. For this embedded system we don't do this.
//
//
// Search all the FVs for an application with a UI Section of Ebl. A .FDF file can be used
// to control the names of UI sections in an FV.
//
Status = FindApplicationMatchingUiSection (L"Ebl", &FvHandle, &NameGuid);
if (!EFI_ERROR (Status)) {
//Boot to Shell.
Status = LoadPeCoffSectionFromFv (FvHandle, &NameGuid);
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Boot from Shell failed. Status: %r\n", Status));
}
}
//
// EFI does not define the behaviour if all boot attemps fail and the last one returns.
// So we make a policy choice to reset the system since this BDS does not have a UI.
//
gRT->ResetSystem (EfiResetShutdown, Status, 0, NULL);
return ;
}
EFI_STATUS
EFIAPI
BdsInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
mBdsImageHandle = ImageHandle;
//
// Install protocol interface
//
Status = gBS->InstallMultipleProtocolInterfaces (
&mBdsImageHandle,
&gEfiBdsArchProtocolGuid, &gBdsProtocol,
NULL
);
ASSERT_EFI_ERROR (Status);
return Status;
}

65
BeagleBoardPkg/Bds/BdsEntry.h Normal file
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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __BDS_ENTRY_H__
#define __BDS_ENTRY_H__
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PrintLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/HobLib.h>
#include <Library/DevicePathLib.h>
#include <Library/PcdLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PrintLib.h>
#include <Protocol/Bds.h>
#include <Protocol/SerialIo.h>
#include <Protocol/FirmwareVolume2.h>
#include <Protocol/SimpleTextIn.h>
#include <Protocol/SimpleTextOut.h>
#include <Protocol/EmbeddedDevice.h>
#include <Protocol/DevicePath.h>
#include <Protocol/SimpleFileSystem.h>
#include <Protocol/UsbIo.h>
EFI_STATUS
LoadPeCoffSectionFromFv (
IN EFI_HANDLE FvHandle,
IN EFI_GUID *NameGuid
);
EFI_STATUS
FindApplicationMatchingUiSection (
IN CHAR16 *UiString,
OUT EFI_HANDLE *FvHandle,
OUT EFI_GUID *NameGuid
);
VOID
EFIAPI
BdsEntry (
IN EFI_BDS_ARCH_PROTOCOL *This
);
#endif

150
BeagleBoardPkg/Bds/FirmwareVolume.c Normal file
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/** @file
The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements
of the UEFI specification as it is designed to implement an embedded systmes
propriatary boot scheme.
This template assume a DXE driver produces a SerialIo protocol not using the EFI
driver module and it will attempt to connect a console on top of this.
Copyright (c) 2009 Apple, Inc. All rights reserved.
Portions copyright (c) 2008-2009, Apple Inc. All rights reserved.
This document is the property of Apple, Inc.
It is considered confidential and proprietary.
This document may not be reproduced or transmitted in any form,
in whole or in part, without the express written permission of
Apple, Inc.
**/
#include "BdsEntry.h"
EFI_STATUS
FindApplicationMatchingUiSection (
IN CHAR16 *UiString,
OUT EFI_HANDLE *FvHandle,
OUT EFI_GUID *NameGuid
)
{
EFI_STATUS Status;
EFI_STATUS NextStatus;
UINTN NoHandles;
EFI_HANDLE *Buffer;
UINTN Index;
EFI_FV_FILETYPE FileType;
EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
VOID *Key;
EFI_FV_FILE_ATTRIBUTES Attributes;
UINTN Size;
UINTN UiStringLen;
CHAR16 *UiSection;
UINT32 Authentication;
UiStringLen = 0;
if (UiString != NULL) {
DEBUG ((DEBUG_ERROR, "UiString %s\n", UiString));
UiStringLen = StrLen (UiString);
}
Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiFirmwareVolume2ProtocolGuid, NULL, &NoHandles, &Buffer);
if (!EFI_ERROR (Status)) {
for (Index = 0; Index < NoHandles; Index++) {
Status = gBS->HandleProtocol (Buffer[Index], &gEfiFirmwareVolume2ProtocolGuid, (VOID **)&Fv);
if (!EFI_ERROR (Status)) {
Key = AllocatePool (Fv->KeySize);
ASSERT (Key != NULL);
ZeroMem (Key, Fv->KeySize);
FileType = EFI_FV_FILETYPE_APPLICATION;
do {
NextStatus = Fv->GetNextFile (Fv, Key, &FileType, NameGuid, &Attributes, &Size);
if (!EFI_ERROR (NextStatus)) {
if (UiString == NULL) {
//
// If UiString is NULL match first application we find.
//
*FvHandle = Buffer[Index];
FreePool (Key);
return Status;
}
UiSection = NULL;
Status = Fv->ReadSection (
Fv,
NameGuid,
EFI_SECTION_USER_INTERFACE,
0,
(VOID **)&UiSection,
&Size,
&Authentication
);
if (!EFI_ERROR (Status)) {
if (StrnCmp (UiString, UiSection, UiStringLen) == 0) {
//
// We found a UiString match.
//
*FvHandle = Buffer[Index];
FreePool (Key);
FreePool (UiSection);
return Status;
}
FreePool (UiSection);
}
}
} while (!EFI_ERROR (NextStatus));
FreePool (Key);
}
}
FreePool (Buffer);
}
return EFI_NOT_FOUND;
}
EFI_DEVICE_PATH *
FvFileDevicePath (
IN EFI_HANDLE FvHandle,
IN EFI_GUID *NameGuid
)
{
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH NewNode;
DevicePath = DevicePathFromHandle (FvHandle);
EfiInitializeFwVolDevicepathNode (&NewNode, NameGuid);
return AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&NewNode);
}
EFI_STATUS
LoadPeCoffSectionFromFv (
IN EFI_HANDLE FvHandle,
IN EFI_GUID *NameGuid
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_HANDLE ImageHandle;
DevicePath = FvFileDevicePath (FvHandle, NameGuid);
Status = gBS->LoadImage (TRUE, gImageHandle, DevicePath, NULL, 0, &ImageHandle);
if (!EFI_ERROR (Status)) {
Status = gBS->StartImage (ImageHandle, NULL, NULL);
}
return Status;
}

65
BeagleBoardPkg/BeagleBoardPkg.dec Normal file
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#%HEADER%
#/** @file
# Beagle board package.
#
# Copyright (c) 2009, Apple Inc.
#
# All rights reserved.
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License which accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = BeagleBoardPkg
PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
PACKAGE_VERSION = 0.1
################################################################################
#
# Include Section - list of Include Paths that are provided by this package.
# Comments are used for Keywords and Module Types.
#
# Supported Module Types:
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
[Includes.common]
Include # Root include for the package
[Guids.common]
gBeagleBoardTokenSpaceGuid = { 0x6834fe45, 0x4aee, 0x4fc6, { 0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xe2 } }
#[PcdsEnumerations.common]
# OMAP3530_GPTIMER:
# OMAP3530_GPTIMER1|1
# OMAP3530_GPTIMER2|2
# OMAP3530_GPTIMER3|3
# OMAP3530_GPTIMER4|4
# OMAP3530_GPTIMER5|5
# OMAP3530_GPTIMER6|6
# OMAP3530_GPTIMER7|7
# OMAP3530_GPTIMER8|8
# OMAP3530_GPTIMER9|9
# OMAP3530_GPTIMER10|10
# OMAP3530_GPTIMER11|11
# OMAP3530_GPTIMER12|12
[PcdsFeatureFlag.common]
[PcdsFixedAtBuild.common]
gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize|0x00000000|UINT32|0x00000201
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart|3|UINT32|0x00000202
gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset|0x00000000|UINT32|0x00000203
gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base|0x00000000|UINT32|0x00000204
# gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|OMAP3530_GPTIMER3|OMAP3530_GPTIMER|0x00000205
gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|3|UINT32|0x00000205
# gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|OMAP3530_GPTIMER4|OMAP3530_GPTIMER|0x00000206
gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|4|UINT32|0x00000206

415
BeagleBoardPkg/BeagleBoardPkg.dsc Normal file
View File

@@ -0,0 +1,415 @@
#/** @file
# Beagle board package.
#
# Copyright (c) 2009, Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = BeagleBoardPkg
PLATFORM_GUID = 91fa6c28-33df-46ac-aee6-292d6811ea31
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/BeagleBoard
SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = BeagleBoardPkg/BeagleBoardPkg.fdf
DEFINE TARGET_HACK = DEBUG
[LibraryClasses.common]
!if TARGET_HACK == DEBUG
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
!else
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
!endif
ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
BeagleBoardSystemLib|BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf
EfiResetSystemLib|BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
EblCmdLib|BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf
EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
SerialPortLib|BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf
SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
#
# Assume everything is fixed at build
#
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
GdbSerialLib|BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf
[LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
[LibraryClasses.common.PEI_CORE]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
[LibraryClasses.common.DXE_CORE]
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
[LibraryClasses.common.DXE_DRIVER]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
[LibraryClasses.common.UEFI_APPLICATION]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
[LibraryClasses.common.UEFI_DRIVER]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
[BuildOptions]
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv6 -march=armv6
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv6
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv6
RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8
RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsFeatureFlag.common]
gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
#
# Control what commands are supported from the UI
# Turn these on and off to add features or save size
#
gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
#
# Beagle board Specific PCDs
#
[PcdsFixedAtBuild.common]
gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"BeagleEdk2"
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
# DEBUG_ASSERT_ENABLED 0x01
# DEBUG_PRINT_ENABLED 0x02
# DEBUG_CODE_ENABLED 0x04
# CLEAR_MEMORY_ENABLED 0x08
# ASSERT_BREAKPOINT_ENABLED 0x10
# ASSERT_DEADLOOP_ENABLED 0x20
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
# DEBUG_INIT 0x00000001 // Initialization
# DEBUG_WARN 0x00000002 // Warnings
# DEBUG_LOAD 0x00000004 // Load events
# DEBUG_FS 0x00000008 // EFI File system
# DEBUG_POOL 0x00000010 // Alloc & Free's
# DEBUG_PAGE 0x00000020 // Alloc & Free's
# DEBUG_INFO 0x00000040 // Verbose
# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
# DEBUG_VARIABLE 0x00000100 // Variable
# DEBUG_BM 0x00000400 // Boot Manager
# DEBUG_BLKIO 0x00001000 // BlkIo Driver
# DEBUG_NET 0x00004000 // SNI Driver
# DEBUG_UNDI 0x00010000 // UNDI Driver
# DEBUG_LOADFILE 0x00020000 // UNDI Driver
# DEBUG_EVENT 0x00080000 // Event messages
# DEBUG_ERROR 0x80000000 // Error
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
gEmbeddedTokenSpaceGuid.PcdPrePiTempMemorySize|0
gEmbeddedTokenSpaceGuid.PcdPrePiBfvBaseAddress|0
gEmbeddedTokenSpaceGuid.PcdPrePiBfvSize|0
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0
gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0
#
# Optional feature to help prevent EFI memory map fragments
# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
# Values are in EFI Pages (4K). DXE Core will make sure that
# at least this much of each type of memory can be allocated
# from a single memory range. This way you only end up with
# maximum of two fragements for each type in the memory map
# (the memory used, and the free memory that was prereserved
# but not used).
#
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
#
# Beagle board Specific PCDs
#
gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000
gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack
gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize|0x00000000
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000
gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset|0x6E000000
gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base|0x4809C000
# Console
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart|3
# Timers
# gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|OMAP3530_GPTIMER3
gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|3
# gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|OMAP3530_GPTIMER4
gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|4
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds|77
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterFrequencyInHz|13000000
#
# ARM Pcds
#
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
#
################################################################################
[Components.common]
#
# SEC
#
BeagleBoardPkg/Sec/Sec.inf
#
# DXE
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
}
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf
#
# Semi-hosting filesystem
#
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
#
# FAT filesystem + GPT/MBR partitioning
#
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
FatPkg/EnhancedFatDxe/Fat.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
#
# USB
#
BeagleBoardPkg/PciEmulation/PciEmulation.inf
#NOTE: Open source EHCI stack doesn't work on Beagleboard.
#NOTE: UsbBus and UsbMassStorage don't work using iPhone SDK tool chain.
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf {
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800fffff
}
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# Nand Flash
#
BeagleBoardPkg/Flash/Flash.inf
#
# MMC/SD
#
BeagleBoardPkg/MMCHSDxe/MMCHS.inf
#
# I2C
#
BeagleBoardPkg/SmbusDxe/Smbus.inf
#
# SoC Drivers
#
BeagleBoardPkg/Gpio/Gpio.inf
BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
BeagleBoardPkg/TimerDxe/TimerDxe.inf
#
# Power IC
#
BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
#
# Application
#
EmbeddedPkg/Ebl/Ebl.inf
#
# Bds
#
BeagleBoardPkg/Bds/Bds.inf
#
# Gdb Stub
#
EmbeddedPkg/GdbStub/GdbStub.inf
ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf

296
BeagleBoardPkg/BeagleBoardPkg.fdf Normal file
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# FLASH layout file for Beagle board.
#
# Copyright (c) 2009, Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into the Flash Device Image. Each FD section
# defines one flash "device" image. A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash" image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.BeagleBoard_EFI]
BaseAddress = 0x80008000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress #The base address of the FLASH Device.
Size = 0x00080000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize #The size in bytes of the FLASH Device
ErasePolarity = 1
BlockSize = 0x40
NumBlocks = 0x2000
################################################################################
#
# Following are lists of FD Region layout which correspond to the locations of different
# images within the flash device.
#
# Regions must be defined in ascending order and may not overlap.
#
# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
# the pipe "|" character, followed by the size of the region, also in hex with the leading
# "0x" characters. Like:
# Offset|Size
# PcdOffsetCName|PcdSizeCName
# RegionType <FV, DATA, or FILE>
#
################################################################################
# 512 bytes of configuration header & 8 bytes of image header
0x00000000|0x00000208
0x00000208|0x0007FDF8
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
FV = FVMAIN_COMPACT
################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file. This section also defines order the components and modules are positioned
# within the image. The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FvMain]
BlockSize = 0x40
NumBlocks = 0x9000
FvAlignment = 8 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
#
# PI DXE Drivers producing Architectural Protocols (EFI Services)
#
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf
#
# Semi-hosting filesystem
#
INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
#
# Nand Flash
#
INF BeagleBoardPkg/Flash/Flash.inf
#
# MMC/SD
#
INF BeagleBoardPkg/MMCHSDxe/MMCHS.inf
#
# I2C
#
INF BeagleBoardPkg/SmbusDxe/Smbus.inf
#
# SoC Drivers
#
INF BeagleBoardPkg/Gpio/Gpio.inf
INF BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
INF BeagleBoardPkg/TimerDxe/TimerDxe.inf
#
# Power IC
#
INF BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
#
# FAT filesystem + GPT/MBR partitioning
#
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
#
# USB Support
#
INF BeagleBoardPkg/PciEmulation/PciEmulation.inf
#NOTE: Open source EHCI stack doesn't work on Beagleboard.
#NOTE: UsbBus and UsbMassStorage don't work using iPhond SDK tool chain.
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# UEFI application (Shell Embedded Boot Loader)
#
INF EmbeddedPkg/Ebl/Ebl.inf
#
# Bds
#
INF BeagleBoardPkg/Bds/Bds.inf
#
# Gdb Stub
#
#INF ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
#INF ApplePkg/Universal/GdbStub/GdbStub.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
INF BeagleBoardPkg/Sec/Sec.inf
INF MdeModulePkg/Core/Dxe/DxeMain.inf
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
}
}
################################################################################
#
# Rules are use with the [FV] section's module INF type to define
# how an FFS file is created for a given INF file. The following Rule are the default
# rules for the different module type. User can add the customized rules to define the
# content of the FFS file.
#
################################################################################
############################################################################
# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
############################################################################
#
#[Rule.Common.DXE_DRIVER]
# FILE DRIVER = $(NAMED_GUID) {
# DXE_DEPEX DXE_DEPEX Optional |.depex
# COMPRESS PI_STD {
# GUIDED {
# PE32 PE32 |.efi
# UI STRING="$(MODULE_NAME)" Optional
# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
# }
# }
# }
#
############################################################################
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 8 |.efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE |.efi
UI STRING ="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM.TIANOCOMPRESSED]
FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
PEI_DEPEX PEI_DEPEX Optional |.depex
GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
}
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
}
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.DXE_RUNTIME_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 |.efi
}

41
BeagleBoardPkg/ConfigurationHeader.dat Normal file
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PRM_CLKSRC_CTRL=0x00000080
PRM_CLKSEL=0x00000003
CM_CLKSEL1_EMU=0x03020A50
CM_CLKSEL_CORE=0x0000030A
CM_CLKSEL_WKUP=0x00000015
CM_CLKEN_PLL_DPLL3=0x00370037
CM_AUTOIDLE_PLL_DPLL3=0x00000000
CM_CLKSEL1_PLL=0x094C0C00
CM_CLKEN_PLL_DPLL4=0x00370037
CM_AUTOIDLE_PLL_DPLL4=0x00000000
CM_CLKSEL2_PLL=0x0001B00C
CM_CLKSEL3_PLL=0x00000009
CM_CLKEN_PLL_MPU=0x00000037
CM_AUTOIDLE_PLL_MPU=0x00000000
CM_CLKSEL1_PLL_MPU=0x0011F40C
CM_CLKSEL2_PLL_MPU=0x00000001
CM_CLKSTCTRL_MPU=0x00000000
SDRC_SYSCONFIG_LSB=0x0000
SDRC_CS_CFG_LSB=0x0001
SDRC_SHARING_LSB=0x0100
SDRC_ERR_TYPE_LSB=0x0000
SDRC_DLLA_CTRL=0x0000000A
SDRC_POWER=0x00000081
MEMORY_TYPE_CS0=0x0003
SDRC_MCFG_0=0x02D04011
SDRC_MR_0_LSB=0x0032
SDRC_EMR1_0_LSB=0x0000
SDRC_EMR2_0_LSB=0x0000
SDRC_EMR3_0_LSB=0x0000
SDRC_ACTIM_CTRLA_0=0xBA9DC4C6
SDRC_ACTIM_CTRLB_0=0x00012522
SDRC_RFRCTRL_0=0x0004E201
MEMORY_TYPE_CS1=0x0003
SDRC_MCFG_1=0x02D04011
SDRC_MR_1_LSB=0x0032
SDRC_EMR1_1_LSB=0x0000
SDRC_EMR2_1_LSB=0x0000
SDRC_EMR3_1_LSB=0x0000
SDRC_ACTIM_CTRLA_1=0xBA9DC4C6
SDRC_ACTIM_CTRLB_1=0x00012522
SDRC_RFRCTRL_1=0x0004E201

21
BeagleBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc Normal file
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//
// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
error = continue
unload
error = abort
setreg @CP15_CONTROL = 0x0005107E
setreg @pc=0x80008208
setreg @cpsr=0x000000D3
dis/D
readfile,raw,nowarn "ZZZZZZ/FV/BEAGLEBOARD_EFI.fd"=0x80008000

23
BeagleBoardPkg/Debugger_scripts/rvi_convert_symbols.sh Executable file
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@@ -0,0 +1,23 @@
#!/bin/sh
#
# Copyright (c) 2008-2009, Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http:#opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
IN=`/usr/bin/cygpath -u $1`
OUT=`/usr/bin/cygpath -u $2`
/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \
-e 's:\\:/:g' \
-e "s/^/load\/a\/ni\/np \"/g" \
-e "s/dll /dll\" \&/g" \
$IN | /usr/bin/sort.exe --key=3 --output=$OUT

BIN
BeagleBoardPkg/Debugger_scripts/rvi_dummy.axf Executable file
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Binary file not shown.

67
BeagleBoardPkg/Debugger_scripts/rvi_hw_setup.inc Normal file
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//
// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
error = continue
unload
error = abort
setreg @CP15_CONTROL = 0x0005107E
setreg @cpsr=0x000000D3
; General clock settings.
setmem /32 0x48307270=0x00000080
setmem /32 0x48306D40=0x00000003
setmem /32 0x48005140=0x03020A50
;Clock configuration
setmem /32 0x48004A40=0x0000030A
setmem /32 0x48004C40=0x00000015
;DPLL3 (Core) settings
setmem /32 0x48004D00=0x00370037
setmem /32 0x48004D30=0x00000000
setmem /32 0x48004D40=0x094C0C00
;DPLL4 (Peripheral) settings
setmem /32 0x48004D00=0x00370037
setmem /32 0x48004D30=0x00000000
setmem /32 0x48004D44=0x0001B00C
setmem /32 0x48004D48=0x00000009
;DPLL1 (MPU) settings
setmem /32 0x48004904=0x00000037
setmem /32 0x48004934=0x00000000
setmem /32 0x48004940=0x0011F40C
setmem /32 0x48004944=0x00000001
setmem /32 0x48004948=0x00000000
;RAM setup.
setmem /16 0x6D000010=0x0000
setmem /16 0x6D000040=0x0001
setmem /16 0x6D000044=0x0100
setmem /16 0x6D000048=0x0000
setmem /32 0x6D000060=0x0000000A
setmem /32 0x6D000070=0x00000081
setmem /16 0x6D000040=0x0003
setmem /32 0x6D000080=0x02D04011
setmem /16 0x6D000084=0x0032
setmem /16 0x6D00008C=0x0000
setmem /32 0x6D00009C=0xBA9DC4C6
setmem /32 0x6D0000A0=0x00012522
setmem /32 0x6D0000A4=0x0004E201
setmem /16 0x6D000040=0x0003
setmem /32 0x6D0000B0=0x02D04011
setmem /16 0x6D0000B4=0x0032
setmem /16 0x6D0000BC=0x0000
setmem /32 0x6D0000C4=0xBA9DC4C6
setmem /32 0x6D0000C8=0x00012522
setmem /32 0x6D0000D4=0x0004E201

23
BeagleBoardPkg/Debugger_scripts/rvi_load_symbols.inc Normal file
View File

@@ -0,0 +1,23 @@
//
// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
include 'ZZZZZZ/rvi_symbols_macros.inc'
macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000)
host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc"
include 'ZZZZZZ/rvi_symbols.inc'
load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata
unload rvi_dummy.axf
delfile rvi_dummy.axf

194
BeagleBoardPkg/Debugger_scripts/rvi_symbols_macros.inc Executable file
View File

@@ -0,0 +1,194 @@
//
// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
define /R int compare_guid(guid1, guid2)
unsigned char *guid1;
unsigned char *guid2;
{
return strncmp(guid1, guid2, 16);
}
.
define /R unsigned char * find_system_table(mem_start, mem_size)
unsigned char *mem_start;
unsigned long mem_size;
{
unsigned char *mem_ptr;
mem_ptr = mem_start + mem_size;
do
{
mem_ptr -= 0x400000; // 4 MB
if (strncmp(mem_ptr, "IBI SYST", 8) == 0)
{
return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase
}
} while (mem_ptr > mem_start);
return 0;
}
.
define /R unsigned char * find_debug_info_table_header(system_table)
unsigned char *system_table;
{
unsigned long configuration_table_entries;
unsigned char *configuration_table;
unsigned long index;
unsigned char debug_table_guid[16];
// Fill in the debug table's guid
debug_table_guid[ 0] = 0x77;
debug_table_guid[ 1] = 0x2E;
debug_table_guid[ 2] = 0x15;
debug_table_guid[ 3] = 0x49;
debug_table_guid[ 4] = 0xDA;
debug_table_guid[ 5] = 0x1A;
debug_table_guid[ 6] = 0x64;
debug_table_guid[ 7] = 0x47;
debug_table_guid[ 8] = 0xB7;
debug_table_guid[ 9] = 0xA2;
debug_table_guid[10] = 0x7A;
debug_table_guid[11] = 0xFE;
debug_table_guid[12] = 0xFE;
debug_table_guid[13] = 0xD9;
debug_table_guid[14] = 0x5E;
debug_table_guid[15] = 0x8B;
configuration_table_entries = *(unsigned long *)(system_table + 64);
configuration_table = *(unsigned long *)(system_table + 68);
for (index = 0; index < configuration_table_entries; index++)
{
if (compare_guid(configuration_table, debug_table_guid) == 0)
{
return *(unsigned long *)(configuration_table + 16);
}
configuration_table += 20;
}
return 0;
}
.
define /R int valid_pe_header(header)
unsigned char *header;
{
if ((header[0x00] == 'M') &&
(header[0x01] == 'Z') &&
(header[0x80] == 'P') &&
(header[0x81] == 'E'))
{
return 1;
}
return 0;
}
.
define /R unsigned long pe_headersize(header)
unsigned char *header;
{
unsigned long *size;
size = header + 0x00AC;
return *size;
}
.
define /R unsigned char *pe_filename(header)
unsigned char *header;
{
unsigned long *debugOffset;
unsigned char *stringOffset;
if (valid_pe_header(header))
{
debugOffset = header + 0x0128;
stringOffset = header + *debugOffset + 0x002C;
return stringOffset;
}
return 0;
}
.
define /R int char_is_valid(c)
unsigned char c;
{
if (c >= 32 && c < 127)
return 1;
return 0;
}
.
define /R write_symbols_file(filename, mem_start, mem_size)
unsigned char *filename;
unsigned char *mem_start;
unsigned long mem_size;
{
unsigned char *system_table;
unsigned char *debug_info_table_header;
unsigned char *debug_info_table;
unsigned long debug_info_table_size;
unsigned long index;
unsigned char *debug_image_info;
unsigned char *loaded_image_protocol;
unsigned char *image_base;
unsigned char *debug_filename;
unsigned long header_size;
int status;
system_table = find_system_table(mem_start, mem_size);
if (system_table == 0)
{
return;
}
status = fopen(88, filename, "w");
debug_info_table_header = find_debug_info_table_header(system_table);
debug_info_table = *(unsigned long *)(debug_info_table_header + 8);
debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4);
for (index = 0; index < (debug_info_table_size * 4); index += 4)
{
debug_image_info = *(unsigned long *)(debug_info_table + index);
if (debug_image_info == 0)
{
break;
}
loaded_image_protocol = *(unsigned long *)(debug_image_info + 4);
image_base = *(unsigned long *)(loaded_image_protocol + 32);
debug_filename = pe_filename(image_base);
header_size = pe_headersize(image_base);
$fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$;
}
fclose(88);
}
.

118
BeagleBoardPkg/Debugger_scripts/rvi_unload_symbols.inc Executable file
View File

@@ -0,0 +1,118 @@
//
// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
error = continue
unload
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
delfile 1
error = abort

211
BeagleBoardPkg/Debugger_scripts/trace32_load_symbols.cmm Normal file
View File

@@ -0,0 +1,211 @@
//
// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
ENTRY &ram_start &ram_size
;If system is running then stop the execution so we can load symbols.
break
;Reset all windows
WINPAGE.RESET
;Create AREA to display the symbols we are loading.
AREA.Reset
AREA.Create SYMBOL 300. 100.
AREA.View SYMBOL
AREA.Select SYMBOL
SYS.Option BE OFF
;Added based on suggestion from Lauterbach support.
MMU.TABLEWALK ON
MMU.ON
;Load symbols.
GOSUB load_symbols &ram_start &ram_size
;Open some windows and enable semihosting.
TOOLBAR ON
STATUSBAR ON
WINPAGE.RESET
WINCLEAR
WINPOS 0.0 17.0 72. 13. 0. 0. W000
SYStem
WINPOS 0.0 0.0 110. 55. 13. 1. W001
WINTABS 10. 10. 25. 62.
Data.List
WINPAGE.SELECT P000
//Enable semihosting
System.Option.BigEndian OFF
tronchip.set swi on // ARM9/10/11 variant
// configure and open semihosting channel
winpos 50% 50% 50% 50%
term.heapinfo 0 0x20000 0x30000 0x20000
term.method armswi
term.mode string
term.gate
WINPOS 115.0 0. 70. 35. 0. 1. W002
Var.Local %HEX
WINPOS 115.10 45. 48. 9. 0. 0. W003
Register
END
find_system_table:
ENTRY &mem_start &mem_size
&mem_ptr=&mem_start+&mem_size
RPT
(
&mem_ptr=&mem_ptr-0x400000 // 4 MB
&word1=Data.LONG(D:&mem_ptr)
&word2=Data.LONG(D:&mem_ptr+0x04)
IF &word1==0x20494249
(
IF &word2==0x54535953
(
&result=Data.LONG(D:&mem_ptr+0x08)
RETURN &result
)
)
)
WHILE &mem_ptr>&mem_start
&result=0
RETURN &result
compare_guid:
ENTRY &guid
IF Data.LONG(D:&guid)==0x49152E77
(
IF Data.LONG(D:&guid+0x04)==0x47641ADA
(
IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7
(
IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE
(
RETURN 0
)
)
)
)
RETURN 1
find_debug_info_table_header:
ENTRY &system_table
&config_table_entries=Data.LONG(D:&system_table+0x40)
&config_table_pointer=Data.LONG(D:&system_table+0x44)
RPT &config_table_entries
(
GOSUB compare_guid &config_table_pointer
ENTRY &result
IF &result==0
(
&result=Data.LONG(D:&config_table_pointer+0x10)
RETURN &result
)
&config_table_pointer=&config_table_pointer+0x14
)
RETURN 0;
valid_pe_header:
ENTRY &header
IF Data.BYTE(D:&header+0x00)==0x4D
(
IF Data.BYTE(D:&header+0x01)==0x5A
(
IF Data.BYTE(D:&header+0x80)==0x50
(
IF Data.BYTE(D:&header+0x81)==0x45
(
RETURN 1
)
)
)
)
RETURN 0
get_file_string:
ENTRY &stringOffset
local &string
&more_string=data.string(d:&stringOffset)
if (string.len("&more_string")>=128.)
(
&string="&string"+"&more_string"
&stringOffset=&stringOffset+string.len("&more_string")
//Get remaining file string
GOSUB get_file_string &stringOffset
ENTRY &more_string
&string="&string"+"&more_string"
)
else
(
&string="&string"+"&more_string"
&more_string=""
)
RETURN &string
load_symbol_file:
ENTRY &header &load_address
GOSUB valid_pe_header &header
ENTRY &result
IF &result==1
(
&debugOffset=Data.LONG(D:&header+0x0128)
&stringOffset=&header+&debugOffset+0x002C
GOSUB get_file_string &stringOffset
ENTRY &filestring
PRINT "&filestring 0x" &load_address
TDIAG Data.load.elf &filestring &load_address /nocode /noclear
)
RETURN
pe_headersize:
ENTRY &header;
RETURN Data.LONG(D:&header+0x00AC)
load_symbols:
ENTRY &mem_start &mem_size
GOSUB find_system_table &mem_start &mem_size
ENTRY &system_table
GOSUB find_debug_info_table_header &system_table
ENTRY &debug_info_table_header
&debug_info_table=Data.LONG(D:&debug_info_table_header+0x08)
&debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04)
&index=0
RPT &debug_info_table_size
(
&debug_image_info=Data.LONG(D:&debug_info_table+&index)
IF &debug_image_info==0
RETURN
&loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04);
&image_base=Data.LONG(D:&loaded_image_protocol+0x20);
GOSUB pe_headersize &image_base
ENTRY &header_size
&image_load_address=&image_base+&header_size
GOSUB load_symbol_file &image_base &image_load_address
&index=&index+0x4
)
RETURN

188
BeagleBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm Normal file
View File

@@ -0,0 +1,188 @@
//
// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
ENTRY &ram_start &ram_size
;If system is running then stop the execution so we can load symbols.
break
;Reset all windows
WINPAGE.RESET
AREA.Reset
AREA.Create SYMBOL 300. 100.
AREA.View SYMBOL
AREA.Select SYMBOL
SYS.Option BE OFF
; Added based on suggestion from Lauterbach support.
MMU.TABLEWALK ON
MMU.ON
GOSUB load_symbols &ram_start &ram_size
;Open some windows.
WINPOS 83.125 29.063 48. 9. 0. 0. W003
Register
WINPOS 83.25 10. 48. 9. 0. 1. W002
Var.Local
END
find_system_table:
ENTRY &mem_start &mem_size
&mem_ptr=&mem_start+&mem_size
RPT
(
&mem_ptr=&mem_ptr-0x400000 // 4 MB
&word1=Data.LONG(D:&mem_ptr)
&word2=Data.LONG(D:&mem_ptr+0x04)
IF &word1==0x20494249
(
IF &word2==0x54535953
(
&result=Data.LONG(D:&mem_ptr+0x08)
RETURN &result
)
)
)
WHILE &mem_ptr>&mem_start
&result=0
RETURN &result
compare_guid:
ENTRY &guid
IF Data.LONG(D:&guid)==0x49152E77
(
IF Data.LONG(D:&guid+0x04)==0x47641ADA
(
IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7
(
IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE
(
RETURN 0
)
)
)
)
RETURN 1
find_debug_info_table_header:
ENTRY &system_table
&config_table_entries=Data.LONG(D:&system_table+0x40)
&config_table_pointer=Data.LONG(D:&system_table+0x44)
RPT &config_table_entries
(
GOSUB compare_guid &config_table_pointer
ENTRY &result
IF &result==0
(
&result=Data.LONG(D:&config_table_pointer+0x10)
RETURN &result
)
&config_table_pointer=&config_table_pointer+0x14
)
RETURN 0;
valid_pe_header:
ENTRY &header
IF Data.BYTE(D:&header+0x00)==0x4D
(
IF Data.BYTE(D:&header+0x01)==0x5A
(
IF Data.BYTE(D:&header+0x80)==0x50
(
IF Data.BYTE(D:&header+0x81)==0x45
(
RETURN 1
)
)
)
)
RETURN 0
get_file_string:
ENTRY &stringOffset
local &string
&more_string=data.string(d:&stringOffset)
if (string.len("&more_string")>=128.)
(
&string="&string"+"&more_string"
&stringOffset=&stringOffset+string.len("&more_string")
//Get remaining file string
GOSUB get_file_string &stringOffset
ENTRY &more_string
&string="&string"+"&more_string"
)
else
(
&string="&string"+"&more_string"
&more_string=""
)
RETURN &string
load_symbol_file:
ENTRY &header &load_address
GOSUB valid_pe_header &header
ENTRY &result
IF &result==1
(
&debugOffset=Data.LONG(D:&header+0x0128)
&stringOffset=&header+&debugOffset+0x002C
&stringOffset=&stringOffset+11.
GOSUB get_file_string &stringOffset
ENTRY &filestring
&filestring="c:"+"&filestring"
PRINT "&filestring 0x" &load_address
Data.load.elf &filestring &load_address /nocode /noclear
)
RETURN
pe_headersize:
ENTRY &header;
RETURN Data.LONG(D:&header+0x00AC)
load_symbols:
ENTRY &mem_start &mem_size
GOSUB find_system_table &mem_start &mem_size
ENTRY &system_table
GOSUB find_debug_info_table_header &system_table
ENTRY &debug_info_table_header
&debug_info_table=Data.LONG(D:&debug_info_table_header+0x08)
&debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04)
&index=0
RPT &debug_info_table_size
(
&debug_image_info=Data.LONG(D:&debug_info_table+&index)
IF &debug_image_info==0
RETURN
&loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04);
&image_base=Data.LONG(D:&loaded_image_protocol+0x20);
GOSUB pe_headersize &image_base
ENTRY &header_size
&image_load_address=&image_base+&header_size
GOSUB load_symbol_file &image_base &image_load_address
&index=&index+0x4
)
RETURN

748
BeagleBoardPkg/Flash/Flash.c Normal file
View File

@@ -0,0 +1,748 @@
/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "Flash.h"
NAND_PART_INFO_TABLE gNandPartInfoTable[1] = {
{ 0x2C, 0xBA, 17, 11 }
};
NAND_FLASH_INFO *gNandFlashInfo = NULL;
UINT8 *gEccCode;
UINTN gNum512BytesChunks = 0;
//
// Device path for SemiHosting. It contains our autogened Caller ID GUID.
//
typedef struct {
VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End;
} FLASH_DEVICE_PATH;
FLASH_DEVICE_PATH gDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
EFI_CALLER_ID_GUID
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
};
//Actual page address = Column address + Page address + Block address.
UINTN
GetActualPageAddressInBytes (
UINTN BlockIndex,
UINTN PageIndex
)
{
//BlockAddressStart = Start of the Block address in actual NAND
//PageAddressStart = Start of the Page address in actual NAND
return ((BlockIndex << gNandFlashInfo->BlockAddressStart) + (PageIndex << gNandFlashInfo->PageAddressStart));
}
VOID
NandSendCommand (
UINT8 Command
)
{
MmioWrite16(GPMC_NAND_COMMAND_0, Command);
}
VOID
NandSendAddress (
UINT8 Address
)
{
MmioWrite16(GPMC_NAND_ADDRESS_0, Address);
}
UINT16
NandReadStatus (
VOID
)
{
//Send READ STATUS command
NandSendCommand(READ_STATUS_CMD);
//Read status.
return MmioRead16(GPMC_NAND_DATA_0);
}
VOID
NandSendAddressCycles (
UINTN Address
)
{
//Column address
NandSendAddress(Address & 0xff);
Address >>= 8;
//Column address
NandSendAddress(Address & 0x07);
Address >>= 3;
//Page and Block address
NandSendAddress(Address & 0xff);
Address >>= 8;
//Block address
NandSendAddress(Address & 0xff);
Address >>= 8;
//Block address
NandSendAddress(Address & 0x01);
}
VOID
GpmcInit (
VOID
)
{
//Enable Smart-idle mode.
MmioWrite32(GPMC_SYSCONFIG, SMARTIDLEMODE);
//Set IRQSTATUS and IRQENABLE to the reset value
MmioWrite32(GPMC_IRQSTATUS, 0x0);
MmioWrite32(GPMC_IRQENABLE, 0x0);
//Disable GPMC timeout control.
MmioWrite32(GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
//Set WRITEPROTECT bit to enable write access.
MmioWrite32(GPMC_CONFIG, WRITEPROTECT_HIGH);
//NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
MmioWrite32(GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
MmioWrite32(GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
MmioWrite32(GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
MmioWrite32(GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
MmioWrite32(GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
MmioWrite32(GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
MmioWrite32(GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
}
EFI_STATUS
NandDetectPart (
VOID
)
{
UINT8 NandInfo = 0;
UINT8 PartInfo[5];
UINTN Index;
BOOLEAN Found = FALSE;
//Send READ ID command
NandSendCommand(READ_ID_CMD);
//Send one address cycle.
NandSendAddress(0);
//Read 5-bytes to idenfity code programmed into the NAND flash devices.
//BYTE 0 = Manufacture ID
//Byte 1 = Device ID
//Byte 2, 3, 4 = Nand part specific information (Page size, Block size etc)
for (Index = 0; Index < sizeof(PartInfo); Index++) {
PartInfo[Index] = MmioRead16(GPMC_NAND_DATA_0);
}
//Check if the ManufactureId and DeviceId are part of the currently supported nand parts.
for (Index = 0; Index < sizeof(gNandPartInfoTable)/sizeof(NAND_PART_INFO_TABLE); Index++) {
if (gNandPartInfoTable[Index].ManufactureId == PartInfo[0] && gNandPartInfoTable[Index].DeviceId == PartInfo[1]) {
gNandFlashInfo->BlockAddressStart = gNandPartInfoTable[Index].BlockAddressStart;
gNandFlashInfo->PageAddressStart = gNandPartInfoTable[Index].PageAddressStart;
Found = TRUE;
break;
}
}
if (Found == FALSE) {
DEBUG ((EFI_D_ERROR, "Nand part is not currently supported. Manufacture id: %x, Device id: %x\n", PartInfo[0], PartInfo[1]));
return EFI_NOT_FOUND;
}
//Populate NAND_FLASH_INFO based on the result of READ ID command.
gNandFlashInfo->ManufactureId = PartInfo[0];
gNandFlashInfo->DeviceId = PartInfo[1];
NandInfo = PartInfo[3];
if (PAGE_SIZE(NandInfo) == PAGE_SIZE_2K_VAL) {
gNandFlashInfo->PageSize = PAGE_SIZE_2K;
} else {
DEBUG ((EFI_D_ERROR, "Unknown Page size.\n"));
return EFI_DEVICE_ERROR;
}
if (SPARE_AREA_SIZE(NandInfo) == SPARE_AREA_SIZE_64B_VAL) {
gNandFlashInfo->SparePageSize = SPARE_AREA_SIZE_64B;
} else {
DEBUG ((EFI_D_ERROR, "Unknown Spare area size.\n"));
return EFI_DEVICE_ERROR;
}
if (BLOCK_SIZE(NandInfo) == BLOCK_SIZE_128K_VAL) {
gNandFlashInfo->BlockSize = BLOCK_SIZE_128K;
} else {
DEBUG ((EFI_D_ERROR, "Unknown Block size.\n"));
return EFI_DEVICE_ERROR;
}
if (ORGANIZATION(NandInfo) == ORGANIZATION_X8) {
gNandFlashInfo->Organization = 0;
} else if (ORGANIZATION(NandInfo) == ORGANIZATION_X16) {
gNandFlashInfo->Organization = 1;
}
//Calculate total number of blocks.
gNandFlashInfo->NumPagesPerBlock = DivU64x32(gNandFlashInfo->BlockSize, gNandFlashInfo->PageSize);
return EFI_SUCCESS;
}
VOID
NandConfigureEcc (
VOID
)
{
//Define ECC size 0 and size 1 to 512 bytes
MmioWrite32(GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
}
VOID
NandEnableEcc (
VOID
)
{
//Clear all the ECC result registers and select ECC result register 1
MmioWrite32(GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
//Enable ECC engine on CS0
MmioWrite32(GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
}
VOID
NandDisableEcc (
VOID
)
{
//Turn off ECC engine.
MmioWrite32(GPMC_ECC_CONFIG, ECCDISABLE);
}
VOID
NandCalculateEcc (
VOID
)
{
UINTN Index;
UINTN EccResultRegister;
UINTN EccResult;
//Capture 32-bit ECC result for each 512-bytes chunk.
//In our case PageSize is 2K so read ECC1-ECC4 result registers and
//generate total of 12-bytes of ECC code for the particular page.
EccResultRegister = GPMC_ECC1_RESULT;
for (Index = 0; Index < gNum512BytesChunks; Index++) {
EccResult = MmioRead32(EccResultRegister);
//Calculate ECC code from 32-bit ECC result value.
//NOTE: Following calculation is not part of TRM. We got this information
//from Beagleboard mailing list.
gEccCode[Index * 3] = EccResult & 0xFF;
gEccCode[(Index * 3) + 1] = (EccResult >> 16) & 0xFF;
gEccCode[(Index * 3) + 2] = (((EccResult >> 20) & 0xF0) | ((EccResult >> 8) & 0x0F));
//Point to next ECC result register.
EccResultRegister += 4;
}
}
EFI_STATUS
NandReadPage (
IN UINTN BlockIndex,
IN UINTN PageIndex,
OUT VOID *Buffer,
OUT UINT8 *SpareBuffer
)
{
UINTN Address;
UINTN Index;
UINTN NumMainAreaWords = (gNandFlashInfo->PageSize/2);
UINTN NumSpareAreaWords = (gNandFlashInfo->SparePageSize/2);
UINT16 *MainAreaWordBuffer = Buffer;
UINT16 *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
UINTN Timeout = MAX_RETRY_COUNT;
//Generate device address in bytes to access specific block and page index
Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
//Send READ command
NandSendCommand(PAGE_READ_CMD);
//Send 5 Address cycles to access specific device address
NandSendAddressCycles(Address);
//Send READ CONFIRM command
NandSendCommand(PAGE_READ_CONFIRM_CMD);
//Poll till device is busy.
while (Timeout) {
if ((NandReadStatus() & NAND_READY) == NAND_READY) {
break;
}
Timeout--;
}
if (Timeout == 0) {
DEBUG ((EFI_D_ERROR, "Read page timed out.\n"));
return EFI_TIMEOUT;
}
//Reissue READ command
NandSendCommand(PAGE_READ_CMD);
//Enable ECC engine.
NandEnableEcc();
//Read data into the buffer.
for (Index = 0; Index < NumMainAreaWords; Index++) {
*MainAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
}
//Read spare area into the buffer.
for (Index = 0; Index < NumSpareAreaWords; Index++) {
*SpareAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
}
//Calculate ECC.
NandCalculateEcc();
//Turn off ECC engine.
NandDisableEcc();
//Perform ECC correction.
//Need to implement..
return EFI_SUCCESS;
}
EFI_STATUS
NandWritePage (
IN UINTN BlockIndex,
IN UINTN PageIndex,
OUT VOID *Buffer,
IN UINT8 *SpareBuffer
)
{
UINTN Address;
UINT16 *MainAreaWordBuffer = Buffer;
UINT16 *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
UINTN Index;
UINTN NandStatus;
UINTN Timeout = MAX_RETRY_COUNT;
//Generate device address in bytes to access specific block and page index
Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
//Send SERIAL DATA INPUT command
NandSendCommand(PROGRAM_PAGE_CMD);
//Send 5 Address cycles to access specific device address
NandSendAddressCycles(Address);
//Enable ECC engine.
NandEnableEcc();
//Data input from Buffer
for (Index = 0; Index < (gNandFlashInfo->PageSize/2); Index++) {
MmioWrite16(GPMC_NAND_DATA_0, *MainAreaWordBuffer++);
//After each write access, device has to wait to accept data.
//Currently we may not be programming proper timing parameters to
//the GPMC_CONFIGi_0 registers and we would need to figure that out.
//Without following delay, page programming fails.
gBS->Stall(1);
}
//Calculate ECC.
NandCalculateEcc();
//Turn off ECC engine.
NandDisableEcc();
//Prepare Spare area buffer with ECC codes.
SetMem(SpareBuffer, gNandFlashInfo->SparePageSize, 0xFF);
CopyMem(&SpareBuffer[ECC_POSITION], gEccCode, gNum512BytesChunks * 3);
//Program spare area with calculated ECC.
for (Index = 0; Index < (gNandFlashInfo->SparePageSize/2); Index++) {
MmioWrite16(GPMC_NAND_DATA_0, *SpareAreaWordBuffer++);
}
//Send PROGRAM command
NandSendCommand(PROGRAM_PAGE_CONFIRM_CMD);
//Poll till device is busy.
while (Timeout) {
NandStatus = NandReadStatus();
if ((NandStatus & NAND_READY) == NAND_READY) {
break;
}
Timeout--;
}
if (Timeout == 0) {
DEBUG ((EFI_D_ERROR, "Program page timed out.\n"));
return EFI_TIMEOUT;
}
//Bit0 indicates Pass/Fail status
if (NandStatus & NAND_FAILURE) {
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
EFI_STATUS
NandEraseBlock (
IN UINTN BlockIndex
)
{
UINTN Address;
UINTN NandStatus;
UINTN Timeout = MAX_RETRY_COUNT;
//Generate device address in bytes to access specific block and page index
Address = GetActualPageAddressInBytes(BlockIndex, 0);
//Send ERASE SETUP command
NandSendCommand(BLOCK_ERASE_CMD);
//Send 3 address cycles to device to access Page address and Block address
Address >>= 11; //Ignore column addresses
NandSendAddress(Address & 0xff);
Address >>= 8;
NandSendAddress(Address & 0xff);
Address >>= 8;
NandSendAddress(Address & 0xff);
//Send ERASE CONFIRM command
NandSendCommand(BLOCK_ERASE_CONFIRM_CMD);
//Poll till device is busy.
while (Timeout) {
NandStatus = NandReadStatus();
if ((NandStatus & NAND_READY) == NAND_READY) {
break;
}
Timeout--;
gBS->Stall(1);
}
if (Timeout == 0) {
DEBUG ((EFI_D_ERROR, "Erase block timed out for Block: %d.\n", BlockIndex));
return EFI_TIMEOUT;
}
//Bit0 indicates Pass/Fail status
if (NandStatus & NAND_FAILURE) {
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
EFI_STATUS
NandReadBlock (
IN UINTN StartBlockIndex,
IN UINTN EndBlockIndex,
OUT VOID *Buffer,
OUT VOID *SpareBuffer
)
{
UINTN BlockIndex;
UINTN PageIndex;
EFI_STATUS Status = EFI_SUCCESS;
for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
//For each block read number of pages
for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
Status = NandReadPage(BlockIndex, PageIndex, Buffer, SpareBuffer);
if (EFI_ERROR(Status)) {
return Status;
}
Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
}
}
return Status;
}
EFI_STATUS
NandWriteBlock (
IN UINTN StartBlockIndex,
IN UINTN EndBlockIndex,
OUT VOID *Buffer,
OUT VOID *SpareBuffer
)
{
UINTN BlockIndex;
UINTN PageIndex;
EFI_STATUS Status = EFI_SUCCESS;
for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
//Page programming.
for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
Status = NandWritePage(BlockIndex, PageIndex, Buffer, SpareBuffer);
if (EFI_ERROR(Status)) {
return Status;
}
Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
}
}
return Status;
}
EFI_STATUS
EFIAPI
NandFlashReset (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN BOOLEAN ExtendedVerification
)
{
UINTN BusyStall = 50; // microSeconds
UINTN ResetBusyTimeout = (1000000 / BusyStall); // 1 Second
//Send RESET command to device.
NandSendCommand(RESET_CMD);
//Wait for 1ms before we check status register.
gBS->Stall(1000);
//Check BIT#5 & BIT#6 in Status register to make sure RESET is done.
while ((NandReadStatus() & NAND_RESET_STATUS) != NAND_RESET_STATUS) {
//In case of extended verification, wait for extended amount of time
//to make sure device is reset.
if (ExtendedVerification) {
if (ResetBusyTimeout == 0) {
return EFI_DEVICE_ERROR;
}
gBS->Stall(BusyStall);
ResetBusyTimeout--;
}
}
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
NandFlashReadBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN UINTN BufferSize,
OUT VOID *Buffer
)
{
UINTN NumBlocks;
UINTN EndBlockIndex;
EFI_STATUS Status;
UINT8 *SpareBuffer = NULL;
if (Buffer == NULL) {
Status = EFI_INVALID_PARAMETER;
goto exit;
}
if (Lba > LAST_BLOCK) {
Status = EFI_INVALID_PARAMETER;
goto exit;
}
if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
Status = EFI_BAD_BUFFER_SIZE;
goto exit;
}
NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
if (SpareBuffer == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto exit;
}
//Read block
Status = NandReadBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Read block fails: %x\n", Status));
goto exit;
}
exit:
if (SpareBuffer != NULL) {
FreePool (SpareBuffer);
}
return Status;
}
EFI_STATUS
EFIAPI
NandFlashWriteBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINT32 MediaId,
IN EFI_LBA Lba,
IN UINTN BufferSize,
IN VOID *Buffer
)
{
UINTN BlockIndex;
UINTN NumBlocks;
UINTN EndBlockIndex;
EFI_STATUS Status;
UINT8 *SpareBuffer = NULL;
if (Buffer == NULL) {
Status = EFI_INVALID_PARAMETER;
goto exit;
}
if (Lba > LAST_BLOCK) {
Status = EFI_INVALID_PARAMETER;
goto exit;
}
if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
Status = EFI_BAD_BUFFER_SIZE;
goto exit;
}
NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
if (SpareBuffer == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto exit;
}
// Erase block
for (BlockIndex = (UINTN)Lba; BlockIndex <= EndBlockIndex; BlockIndex++) {
Status = NandEraseBlock(BlockIndex);
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Erase block failed. Status: %x\n", Status));
goto exit;
}
}
// Program data
Status = NandWriteBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Block write fails: %x\n", Status));
goto exit;
}
exit:
if (SpareBuffer != NULL) {
FreePool (SpareBuffer);
}
return Status;
}
EFI_STATUS
EFIAPI
NandFlashFlushBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This
)
{
return EFI_SUCCESS;
}
EFI_BLOCK_IO_PROTOCOL BlockIo =
{
EFI_BLOCK_IO_INTERFACE_REVISION, // Revision
&NandFlashMedia, // *Media
NandFlashReset, // Reset
NandFlashReadBlocks, // ReadBlocks
NandFlashWriteBlocks, // WriteBlocks
NandFlashFlushBlocks // FlushBlocks
};
EFI_STATUS
NandFlashInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
gNandFlashInfo = (NAND_FLASH_INFO *)AllocateZeroPool(sizeof(NAND_FLASH_INFO));
//Initialize GPMC module.
GpmcInit();
//Reset NAND part
NandFlashReset(&BlockIo, FALSE);
//Detect NAND part and populate gNandFlashInfo structure
Status = NandDetectPart();
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "Nand part id detection failure: Status: %x\n", Status));
return Status;
}
//Count total number of 512Bytes chunk based on the page size.
if (gNandFlashInfo->PageSize == PAGE_SIZE_512B) {
gNum512BytesChunks = 1;
} else if (gNandFlashInfo->PageSize == PAGE_SIZE_2K) {
gNum512BytesChunks = 4;
} else if (gNandFlashInfo->PageSize == PAGE_SIZE_4K) {
gNum512BytesChunks = 8;
}
gEccCode = (UINT8 *)AllocatePool(gNum512BytesChunks * 3);
if (gEccCode == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//Configure ECC
NandConfigureEcc();
//Patch EFI_BLOCK_IO_MEDIA structure.
NandFlashMedia.BlockSize = gNandFlashInfo->BlockSize;
NandFlashMedia.LastBlock = LAST_BLOCK;
//Publish BlockIO.
Status = gBS->InstallMultipleProtocolInterfaces (
&ImageHandle,
&gEfiBlockIoProtocolGuid, &BlockIo,
&gEfiDevicePathProtocolGuid, &gDevicePath,
NULL
);
return Status;
}

118
BeagleBoardPkg/Flash/Flash.h Normal file
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@@ -0,0 +1,118 @@
/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef FLASH_H
#define FLASH_H
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/IoLib.h>
#include <Protocol/BlockIo.h>
#include <Protocol/Cpu.h>
#include <Omap3530/Omap3530.h>
#define PAGE_SIZE(x) ((x) & 0x01)
#define PAGE_SIZE_2K_VAL (0x01UL)
#define SPARE_AREA_SIZE(x) (((x) >> 2) & 0x01)
#define SPARE_AREA_SIZE_64B_VAL (0x1UL)
#define BLOCK_SIZE(x) (((x) >> 4) & 0x01)
#define BLOCK_SIZE_128K_VAL (0x01UL)
#define ORGANIZATION(x) (((x) >> 6) & 0x01)
#define ORGANIZATION_X8 (0x0UL)
#define ORGANIZATION_X16 (0x1UL)
#define PAGE_SIZE_512B (512)
#define PAGE_SIZE_2K (2048)
#define PAGE_SIZE_4K (4096)
#define SPARE_AREA_SIZE_16B (16)
#define SPARE_AREA_SIZE_64B (64)
#define BLOCK_SIZE_16K (16*1024)
#define BLOCK_SIZE_128K (128*1024)
#define BLOCK_COUNT (2048)
#define LAST_BLOCK (BLOCK_COUNT - 1)
#define ECC_POSITION 2
//List of commands.
#define RESET_CMD 0xFF
#define READ_ID_CMD 0x90
#define READ_STATUS_CMD 0x70
#define PAGE_READ_CMD 0x00
#define PAGE_READ_CONFIRM_CMD 0x30
#define BLOCK_ERASE_CMD 0x60
#define BLOCK_ERASE_CONFIRM_CMD 0xD0
#define PROGRAM_PAGE_CMD 0x80
#define PROGRAM_PAGE_CONFIRM_CMD 0x10
//Nand status register bit definition
#define NAND_SUCCESS (0x0UL << 0)
#define NAND_FAILURE (0x1UL << 0)
#define NAND_BUSY (0x0UL << 6)
#define NAND_READY (0x1UL << 6)
#define NAND_RESET_STATUS (0x60UL << 0)
#define MAX_RETRY_COUNT 1500
EFI_BLOCK_IO_MEDIA NandFlashMedia = {
SIGNATURE_32('n','a','n','d'), // MediaId
FALSE, // RemovableMedia
TRUE, // MediaPresent
TRUE, // LogicalPartition
FALSE, // ReadOnly
FALSE, // WriteCaching
0, // BlockSize
2, // IoAlign
0, // Pad
0 // LastBlock
};
typedef struct {
UINT8 ManufactureId;
UINT8 DeviceId;
UINT8 BlockAddressStart; //Start of the Block address in actual NAND
UINT8 PageAddressStart; //Start of the Page address in actual NAND
} NAND_PART_INFO_TABLE;
typedef struct {
UINT8 ManufactureId;
UINT8 DeviceId;
UINT8 Organization; //x8 or x16
UINT32 PageSize;
UINT32 SparePageSize;
UINT32 BlockSize;
UINT32 NumPagesPerBlock;
UINT8 BlockAddressStart; //Start of the Block address in actual NAND
UINT8 PageAddressStart; //Start of the Page address in actual NAND
} NAND_FLASH_INFO;
#endif //FLASH_H

36
BeagleBoardPkg/Flash/Flash.inf Normal file
View File

@@ -0,0 +1,36 @@
#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = NandFlash
FILE_GUID = 4d00ef14-c4e0-426b-81b7-30a00a14aad6
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = NandFlashInitialize
[Sources.common]
Flash.c
[Packages]
MdePkg/MdePkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
IoLib
[Guids]
[Protocols]
gEfiBlockIoProtocolGuid
gEfiCpuArchProtocolGuid
[Pcd]
gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset
[depex]
TRUE

135
BeagleBoardPkg/Gpio/Gpio.c Normal file
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@@ -0,0 +1,135 @@
/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Uefi.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/EmbeddedGpio.h>
#include <Omap3530/Omap3530.h>
EFI_STATUS
Get (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
OUT UINTN *Value
)
{
UINTN Port;
UINTN Pin;
UINT32 DataInRegister;
if (Value == NULL)
{
return EFI_UNSUPPORTED;
}
Port = GPIO_PORT(Gpio);
Pin = GPIO_PIN(Gpio);
DataInRegister = GpioBase(Port) + GPIO_DATAIN;
if (MmioRead32(DataInRegister) & GPIO_DATAIN_MASK(Pin)) {
*Value = 1;
} else {
*Value = 0;
}
return EFI_SUCCESS;
}
EFI_STATUS
Set (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
IN EMBEDDED_GPIO_MODE Mode
)
{
UINTN Port;
UINTN Pin;
UINT32 OutputEnableRegister;
UINT32 SetDataOutRegister;
UINT32 ClearDataOutRegister;
Port = GPIO_PORT(Gpio);
Pin = GPIO_PIN(Gpio);
OutputEnableRegister = GpioBase(Port) + GPIO_OE;
SetDataOutRegister = GpioBase(Port) + GPIO_SETDATAOUT;
ClearDataOutRegister = GpioBase(Port) + GPIO_CLEARDATAOUT;
switch (Mode)
{
case GPIO_MODE_INPUT:
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin));
break;
case GPIO_MODE_OUTPUT_0:
MmioWrite32(ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break;
case GPIO_MODE_OUTPUT_1:
MmioWrite32(SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break;
default:
return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
}
EFI_STATUS
GetMode (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
OUT EMBEDDED_GPIO_MODE *Mode
)
{
return EFI_UNSUPPORTED;
}
EFI_STATUS
SetPull (
IN EMBEDDED_GPIO *This,
IN EMBEDDED_GPIO_PIN Gpio,
IN EMBEDDED_GPIO_PULL Direction
)
{
return EFI_UNSUPPORTED;
}
EMBEDDED_GPIO Gpio = {
Get,
Set,
GetMode,
SetPull
};
EFI_STATUS
GpioInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedGpioProtocolGuid, &Gpio, NULL);
return Status;
}

33
BeagleBoardPkg/Gpio/Gpio.inf Normal file
View File

@@ -0,0 +1,33 @@
#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Gpio
FILE_GUID = E7D9CAE1-6930-46E3-BDF9-0027446E7DF2
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = GpioInitialize
[Sources.common]
Gpio.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
IoLib
UefiDriverEntryPoint
OmapLib
[Guids]
[Protocols]
gEmbeddedGpioProtocolGuid
[Pcd]
[depex]
TRUE

36
BeagleBoardPkg/Include/Library/BeagleBoardSystemLib.h Normal file
View File

@@ -0,0 +1,36 @@
/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __BEAGLEBOARD_YSTEMLIB_H__
#define __BEAGLEBOARD_YSTEMLIB_H__
VOID
EFIAPI
GoLittleEndian (
UINTN ImageAddress
);
VOID
EFIAPI
ResetSystem (
IN EFI_RESET_TYPE ResetType
);
VOID
EFIAPI
ShutdownEfi (
VOID
);
#endif // __BEAGLEBOARD_YSTEMLIB_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAPLIB_H__
#define __OMAPLIB_H__
UINT32
GpioBase (
IN UINTN Port
);
UINT32
TimerBase (
IN UINTN Timer
);
UINTN
InterruptVectorForTimer (
IN UINTN TImer
);
UINT32
UartBase (
IN UINTN Uart
);
#endif // __OMAPLIB_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530_H__
#define __OMAP3530_H__
#include "Omap3530Gpio.h"
#include "Omap3530Interrupt.h"
#include "Omap3530Prcm.h"
#include "Omap3530Timer.h"
#include "Omap3530Uart.h"
#include "Omap3530Usb.h"
#include "Omap3530MMCHS.h"
#include "Omap3530I2c.h"
#include "Omap3530PadConfiguration.h"
#include "Omap3530Gpmc.h"
//CONTROL_PBIAS_LITE
#define CONTROL_PBIAS_LITE 0x48002520
#define PBIASLITEVMODE0 (0x1UL << 0)
#define PBIASLITEPWRDNZ0 (0x1UL << 1)
#define PBIASSPEEDCTRL0 (0x1UL << 2)
#define PBIASLITEVMODE1 (0x1UL << 8)
#define PBIASLITEWRDNZ1 (0x1UL << 9)
#endif // __OMAP3530_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530GPIO_H__
#define __OMAP3530GPIO_H__
#define GPIO1_BASE (0x48310000)
#define GPIO2_BASE (0x49050000)
#define GPIO3_BASE (0x49052000)
#define GPIO4_BASE (0x49054000)
#define GPIO5_BASE (0x49056000)
#define GPIO6_BASE (0x49058000)
#define GPIO_SYSCONFIG (0x0010)
#define GPIO_SYSSTATUS (0x0014)
#define GPIO_IRQSTATUS1 (0x0018)
#define GPIO_IRQENABLE1 (0x001C)
#define GPIO_WAKEUPENABLE (0x0020)
#define GPIO_IRQSTATUS2 (0x0028)
#define GPIO_IRQENABLE2 (0x002C)
#define GPIO_CTRL (0x0030)
#define GPIO_OE (0x0034)
#define GPIO_DATAIN (0x0038)
#define GPIO_DATAOUT (0x003C)
#define GPIO_LEVELDETECT0 (0x0040)
#define GPIO_LEVELDETECT1 (0x0044)
#define GPIO_RISINGDETECT (0x0048)
#define GPIO_FALLINGDETECT (0x004C)
#define GPIO_DEBOUNCENABLE (0x0050)
#define GPIO_DEBOUNCINGTIME (0x0054)
#define GPIO_CLEARIRQENABLE1 (0x0060)
#define GPIO_SETIRQENABLE1 (0x0064)
#define GPIO_CLEARIRQENABLE2 (0x0070)
#define GPIO_SETIRQENABLE2 (0x0074)
#define GPIO_CLEARWKUENA (0x0080)
#define GPIO_SETWKUENA (0x0084)
#define GPIO_CLEARDATAOUT (0x0090)
#define GPIO_SETDATAOUT (0x0094)
#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_NONE (1UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
#define GPIO_SYSCONFIG_ENAWAKEUP_MASK (1UL << 2)
#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2)
#define GPIO_SYSCONFIG_SOFTRESET_MASK (1UL << 1)
#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
#define GPIO_SYSCONFIG_SOFTRESET_RESET (1UL << 1)
#define GPIO_SYSCONFIG_AUTOIDLE_MASK (1UL << 0)
#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
#define GPIO_SYSCONFIG_AUTOIDLE_ON (1UL << 0)
#define GPIO_SYSSTATUS_RESETDONE_MASK (1UL << 0)
#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE (1UL << 0)
#define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
#define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x))
#define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x))
#define GPIO_IRQENABLE_MASK(x) (1UL << (x))
#define GPIO_IRQENABLE_DISABLE(x) (0UL << (x))
#define GPIO_IRQENABLE_ENABLE(x) (1UL << (x))
#define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x))
#define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x))
#define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x))
#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_2 (1UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
#define GPIO_CTRL_DISABLEMODULE_MASK (1UL << 0)
#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
#define GPIO_CTRL_DISABLEMODULE_DISABLE (1UL << 0)
#define GPIO_OE_MASK(x) (1UL << (x))
#define GPIO_OE_OUTPUT(x) (0UL << (x))
#define GPIO_OE_INPUT(x) (1UL << (x))
#define GPIO_DATAIN_MASK(x) (1UL << (x))
#define GPIO_DATAOUT_MASK(x) (1UL << (x))
#define GPIO_LEVELDETECT_MASK(x) (1UL << (x))
#define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x))
#define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x))
#define GPIO_RISINGDETECT_MASK(x) (1UL << (x))
#define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x))
#define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x))
#define GPIO_FALLINGDETECT_MASK(x) (1UL << (x))
#define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x))
#define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x))
#define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x))
#define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x))
#define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x))
#define GPIO_DEBOUNCINGTIME_MASK (0xFF)
#define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)
#define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x))
#define GPIO_SETIRQENABLE_BIT(x) (1UL << (x))
#define GPIO_CLEARWKUENA_BIT(x) (1UL << (x))
#define GPIO_SETWKUENA_BIT(x) (1UL << (x))
#define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x))
#define GPIO_SETDATAOUT_BIT(x) (1UL << (x))
#endif // __OMAP3530GPIO_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530GPMC_H__
#define __OMAP3530GPMC_H__
#define GPMC_BASE (0x6E000000)
//GPMC NAND definitions.
#define GPMC_SYSCONFIG (GPMC_BASE + 0x10)
#define SMARTIDLEMODE (0x2UL << 3)
#define GPMC_SYSSTATUS (GPMC_BASE + 0x14)
#define GPMC_IRQSTATUS (GPMC_BASE + 0x18)
#define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
#define TIMEOUTENABLE (0x1UL << 0)
#define TIMEOUTDISABLE (0x0UL << 0)
#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
#define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
#define GPMC_CONFIG (GPMC_BASE + 0x50)
#define WRITEPROTECT_HIGH (0x1UL << 4)
#define WRITEPROTECT_LOW (0x0UL << 4)
#define GPMC_STATUS (GPMC_BASE + 0x54)
#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)
#define DEVICETYPE_NOR (0x0UL << 10)
#define DEVICETYPE_NAND (0x2UL << 10)
#define DEVICESIZE_X8 (0x0UL << 12)
#define DEVICESIZE_X16 (0x1UL << 12)
#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
#define CSONTIME (0x0UL << 0)
#define CSRDOFFTIME (0x14UL << 8)
#define CSWROFFTIME (0x14UL << 16)
#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)
#define ADVRDOFFTIME (0x14UL << 8)
#define ADVWROFFTIME (0x14UL << 16)
#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
#define OEONTIME (0x1UL << 0)
#define OEOFFTIME (0xFUL << 8)
#define WEONTIME (0x1UL << 16)
#define WEOFFTIME (0xFUL << 24)
#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
#define RDCYCLETIME (0x14UL << 0)
#define WRCYCLETIME (0x14UL << 8)
#define RDACCESSTIME (0xCUL << 16)
#define PAGEBURSTACCESSTIME (0x1UL << 24)
#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
#define CYCLE2CYCLESAMECSEN (0x1UL << 7)
#define CYCLE2CYCLEDELAY (0xAUL << 8)
#define WRDATAONADMUXBUS (0xFUL << 16)
#define WRACCESSTIME (0x1FUL << 24)
#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
#define BASEADDRESS (0x30UL << 0)
#define CSVALID (0x1UL << 6)
#define MASKADDRESS_128MB (0x8UL << 8)
#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)
#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
#define ECCENABLE (0x1UL << 0)
#define ECCDISABLE (0x0UL << 0)
#define ECCCS_0 (0x0UL << 1)
#define ECC16B (0x1UL << 7)
#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
#define ECCPOINTER_REG1 (0x1UL << 0)
#define ECCCLEAR (0x1UL << 8)
#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
#define ECCSIZE0_512BYTES (0xFFUL << 12)
#define ECCSIZE1_512BYTES (0xFFUL << 22)
#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)
#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)
#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)
#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)
#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)
#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)
#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)
#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)
#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)
#endif //__OMAP3530GPMC_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530I2C_H__
#define __OMAP3530I2C_H__
//I2C register definitions.
#define I2C1BASE 0x48070000
#define I2C_IE (I2C1BASE + 0x4)
#define XRDY_IE (0x1UL << 4)
#define RRDY_IE (0x1UL << 3)
#define ARDY_IE (0x1UL << 2)
#define NACK_IE (0x1UL << 1)
#define I2C_STAT (I2C1BASE + 0x8)
#define BB (0x1UL << 12)
#define XRDY (0x1UL << 4)
#define RRDY (0x1UL << 3)
#define ARDY (0x1UL << 2)
#define NACK (0x1UL << 1)
#define I2C_WE (I2C1BASE + 0xC)
#define I2C_SYSS (I2C1BASE + 0x10)
#define I2C_BUF (I2C1BASE + 0x14)
#define I2C_CNT (I2C1BASE + 0x18)
#define I2C_DATA (I2C1BASE + 0x1C)
#define I2C_SYSC (I2C1BASE + 0x20)
#define I2C_CON (I2C1BASE + 0x24)
#define STT (0x1UL << 0)
#define STP (0x1UL << 1)
#define XSA (0x1UL << 8)
#define TRX (0x1UL << 9)
#define MST (0x1UL << 10)
#define I2C_EN (0x1UL << 15)
#define I2C_OA0 (I2C1BASE + 0x28)
#define I2C_SA (I2C1BASE + 0x2C)
#define I2C_PSC (I2C1BASE + 0x30)
#define I2C_SCLL (I2C1BASE + 0x34)
#define I2C_SCLH (I2C1BASE + 0x38)
#define I2C_SYSTEST (I2C1BASE + 0x3C)
#define I2C_BUFSTAT (I2C1BASE + 0x40)
#define I2C_OA1 (I2C1BASE + 0x44)
#define I2C_OA2 (I2C1BASE + 0x48)
#define I2C_OA3 (I2C1BASE + 0x4C)
#define I2C_ACTOA (I2C1BASE + 0x50)
#define I2C_SBLOCK (I2C1BASE + 0x54)
#endif //__OMAP3530I2C_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530INTERRUPT_H__
#define __OMAP3530INTERRUPT_H__
#define INTERRUPT_BASE (0x48200000)
#define INT_NROF_VECTORS (96)
#define MAX_VECTOR (INT_NROF_VECTORS - 1)
#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)
#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)
#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)
#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)
#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)
#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)
#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)
#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)
#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)
#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)
#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))
#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))
#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))
#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))
#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))
#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))
#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))
#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
#define INTCPS_SIR_IRQ_MASK (0x7F)
#define INTCPS_CONTROL_NEWIRQAGR (1UL << 0)
#endif // __OMAP3530INTERRUPT_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530SDIO_H__
#define __OMAP3530SDIO_H__
//MMC/SD/SDIO1 register definitions.
#define MMCHS1BASE 0x4809C000
#define MMC_REFERENCE_CLK (96000000)
#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
#define SOFTRESET (0x1UL << 1)
#define ENAWAKEUP (0x1UL << 2)
#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
#define RESETDONE_MASK (0x1UL << 0)
#define RESETDONE (0x1UL << 0)
#define MMCHS_CSRE (MMCHS1BASE + 0x24)
#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
#define MMCHS_CON (MMCHS1BASE + 0x2C)
#define OD (0x1UL << 0)
#define NOINIT (0x0UL << 1)
#define INIT (0x1UL << 1)
#define HR (0x1UL << 2)
#define STR (0x1UL << 3)
#define MODE (0x1UL << 4)
#define DW8_1_4_BIT (0x0UL << 5)
#define DW8_8_BIT (0x1UL << 5)
#define MIT (0x1UL << 6)
#define CDP (0x1UL << 7)
#define WPP (0x1UL << 8)
#define CTPL (0x1UL << 11)
#define CEATA_OFF (0x0UL << 12)
#define CEATA_ON (0x1UL << 12)
#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
#define MMCHS_BLK (MMCHS1BASE + 0x104)
#define BLEN_512BYTES (0x200UL << 0)
#define MMCHS_ARG (MMCHS1BASE + 0x108)
#define MMCHS_CMD (MMCHS1BASE + 0x10C)
#define DE_ENABLE (0x1UL << 0)
#define BCE_ENABLE (0x1UL << 1)
#define ACEN_ENABLE (0x1UL << 2)
#define DDIR_READ (0x1UL << 4)
#define DDIR_WRITE (0x0UL << 4)
#define MSBS_SGLEBLK (0x0UL << 5)
#define MSBS_MULTBLK (0x1UL << 5)
#define RSP_TYPE_MASK (0x3UL << 16)
#define RSP_TYPE_136BITS (0x1UL << 16)
#define RSP_TYPE_48BITS (0x2UL << 16)
#define CCCE_ENABLE (0x1UL << 19)
#define CICE_ENABLE (0x1UL << 20)
#define DP_ENABLE (0x1UL << 21)
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
#define MMCHS_RSP32 (MMCHS1BASE + 0x114)
#define MMCHS_RSP54 (MMCHS1BASE + 0x118)
#define MMCHS_RSP76 (MMCHS1BASE + 0x11C)
#define MMCHS_DATA (MMCHS1BASE + 0x120)
#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
#define CMDI_MASK (0x1UL << 0)
#define CMDI_ALLOWED (0x0UL << 0)
#define CMDI_NOT_ALLOWED (0x1UL << 0)
#define DATI_MASK (0x1UL << 1)
#define DATI_ALLOWED (0x0UL << 1)
#define DATI_NOT_ALLOWED (0x1UL << 1)
#define MMCHS_HCTL (MMCHS1BASE + 0x128)
#define DTW_1_BIT (0x0UL << 1)
#define DTW_4_BIT (0x1UL << 1)
#define SDBP_MASK (0x1UL << 8)
#define SDBP_OFF (0x0UL << 8)
#define SDBP_ON (0x1UL << 8)
#define SDVS_1_8_V (0x5UL << 9)
#define SDVS_3_0_V (0x6UL << 9)
#define IWE (0x1UL << 24)
#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
#define ICE (0x1UL << 0)
#define ICS_MASK (0x1UL << 1)
#define ICS (0x1UL << 1)
#define CEN (0x1UL << 2)
#define CLKD_MASK (0x3FFUL << 6)
#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
#define CLKD_400KHZ (0xF0UL)
#define DTO_MASK (0xFUL << 16)
#define DTO_VAL (0xEUL << 16)
#define SRA (0x1UL << 24)
#define SRC_MASK (0x1UL << 25)
#define SRC (0x1UL << 25)
#define SRD (0x1UL << 26)
#define MMCHS_STAT (MMCHS1BASE + 0x130)
#define CC (0x1UL << 0)
#define TC (0x1UL << 1)
#define BWR (0x1UL << 4)
#define BRR (0x1UL << 5)
#define ERRI (0x1UL << 15)
#define CTO (0x1UL << 16)
#define DTO (0x1UL << 20)
#define DCRC (0x1UL << 21)
#define DEB (0x1UL << 22)
#define MMCHS_IE (MMCHS1BASE + 0x134)
#define CC_EN (0x1UL << 0)
#define TC_EN (0x1UL << 1)
#define BWR_EN (0x1UL << 4)
#define BRR_EN (0x1UL << 5)
#define CTO_EN (0x1UL << 16)
#define CCRC_EN (0x1UL << 17)
#define CEB_EN (0x1UL << 18)
#define CIE_EN (0x1UL << 19)
#define DTO_EN (0x1UL << 20)
#define DCRC_EN (0x1UL << 21)
#define DEB_EN (0x1UL << 22)
#define CERR_EN (0x1UL << 28)
#define BADA_EN (0x1UL << 29)
#define MMCHS_ISE (MMCHS1BASE + 0x138)
#define CC_SIGEN (0x1UL << 0)
#define TC_SIGEN (0x1UL << 1)
#define BWR_SIGEN (0x1UL << 4)
#define BRR_SIGEN (0x1UL << 5)
#define CTO_SIGEN (0x1UL << 16)
#define CCRC_SIGEN (0x1UL << 17)
#define CEB_SIGEN (0x1UL << 18)
#define CIE_SIGEN (0x1UL << 19)
#define DTO_SIGEN (0x1UL << 20)
#define DCRC_SIGEN (0x1UL << 21)
#define DEB_SIGEN (0x1UL << 22)
#define CERR_SIGEN (0x1UL << 28)
#define BADA_SIGEN (0x1UL << 29)
#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
#define MMCHS_CAPA (MMCHS1BASE + 0x140)
#define VS30 (0x1UL << 25)
#define VS18 (0x1UL << 26)
#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
#define MMCHS_REV (MMCHS1BASE + 0x1FC)
#define CMD0 INDX(0)
#define CMD0_INT_EN (CC_EN | CEB_EN)
#define CMD1 (INDX(1) | RSP_TYPE_48BITS)
#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN)
#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD5 (INDX(5) | RSP_TYPE_48BITS)
#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN)
#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
#define CMD8_ARG (0x0UL << 12 | 0x1UL << 8 | 0xCEUL << 0)
#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define ACMD41 (INDX(41) | RSP_TYPE_48BITS)
#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#endif //__OMAP3530SDIO_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530_PAD_CONFIGURATION_H__
#define __OMAP3530_PAD_CONFIGURATION_H__
#define SYSTEM_CONTROL_MODULE_BASE 0x48002000
//Pin definition
#define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)
#define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)
#define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)
#define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)
#define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)
#define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
#define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
#define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
#define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)
#define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)
#define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)
#define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)
#define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)
#define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
#define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
#define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
#define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)
#define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)
#define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)
#define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)
#define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)
#define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
#define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
#define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
#define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)
#define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)
#define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)
#define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)
#define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)
#define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
#define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
#define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
#define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)
#define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)
#define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)
#define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)
#define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)
#define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)
#define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)
#define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
#define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
#define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
#define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)
#define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)
#define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)
#define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)
#define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)
#define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
#define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
#define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
#define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)
#define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)
#define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)
#define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)
#define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)
#define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
#define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
#define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
#define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
#define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
#define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
#define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
#define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
#define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
#define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
#define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
#define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
#define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
#define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
#define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
#define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
#define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
#define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
#define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
#define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
#define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
#define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
#define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
#define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
#define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
#define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
#define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
#define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
#define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
#define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
#define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
#define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
#define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
#define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
#define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
#define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
#define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
#define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
#define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
#define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
#define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
#define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
#define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
#define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
#define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
#define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
#define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
#define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
#define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
#define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
#define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
#define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)
#define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)
#define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)
#define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)
#define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)
#define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
#define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
#define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
#define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)
#define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)
#define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)
#define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)
#define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)
#define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
#define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
#define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
#define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)
#define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)
#define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)
#define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)
#define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)
#define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
#define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
#define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
#define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)
#define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)
#define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)
#define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)
#define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)
#define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
#define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
#define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
#define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)
#define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)
#define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)
#define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)
#define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)
#define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
#define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
#define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
#define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)
#define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)
#define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)
#define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)
#define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)
#define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
#define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
#define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
#define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)
#define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)
#define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)
#define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)
#define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)
#define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
#define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
#define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
#define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)
#define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)
#define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)
#define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)
#define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)
#define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
#define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
#define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
#define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)
#define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)
#define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)
#define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)
#define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)
#define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
#define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
#define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
#define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)
#define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)
#define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)
#define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)
#define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)
#define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
#define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
#define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
#define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
#define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
#define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
#define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
#define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
#define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
#define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
#define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
#define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
#define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
#define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
#define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
#define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
#define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
#define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
#define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
#define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
#define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
#define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
#define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
#define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
#define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
#define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
#define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
#define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
#define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
#define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
#define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
#define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
#define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
#define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
#define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
#define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
#define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
#define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
#define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
#define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
#define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
#define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
#define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
#define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
#define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
#define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
#define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
#define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
#define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
#define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
#define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
#define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
#define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
#define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
#define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
//Mux modes
#define MUXMODE0 (0x0UL)
#define MUXMODE1 (0x1UL)
#define MUXMODE2 (0x2UL)
#define MUXMODE3 (0x3UL)
#define MUXMODE4 (0x4UL)
#define MUXMODE5 (0x5UL)
#define MUXMODE6 (0x6UL)
#define MUXMODE7 (0x7UL)
//Pad configuration register.
#define PAD_CONFIG_MASK (0xFFFFUL)
#define MUXMODE_OFFSET 0
#define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)
#define PULL_CONFIG_OFFSET 3
#define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)
#define INPUTENABLE_OFFSET 8
#define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)
#define OFFMODE_VALUE_OFFSET 9
#define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)
#define WAKEUP_OFFSET 14
#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
#define PULLUDDISABLE (0x0UL << 0)
#define PULLUDENABLE (0x1UL << 0)
#define PULLTYPENOSELECT (0x0UL << 1)
#define PULLTYPESELECT (0x1UL << 1)
#define OUTPUT (0x0UL) //Pin is configured in output only mode.
#define INPUT (0x1UL) //Pin is configured in bi-directional mode.
typedef struct {
UINTN Pin;
UINTN MuxMode;
UINTN PullConfig;
UINTN InputEnable;
} PAD_CONFIGURATION;
#endif //__OMAP3530_PAD_CONFIGURATION_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530PRCM_H__
#define __OMAP3530PRCM_H__
#define CM_FCLKEN1_CORE (0x48004A00)
#define CM_FCLKEN3_CORE (0x48004A08)
#define CM_ICLKEN1_CORE (0x48004A10)
#define CM_ICLKEN3_CORE (0x48004A18)
#define CM_CLKEN2_PLL (0x48004D04)
#define CM_CLKSEL4_PLL (0x48004D4C)
#define CM_CLKSEL5_PLL (0x48004D50)
#define CM_FCLKEN_USBHOST (0x48005400)
#define CM_ICLKEN_USBHOST (0x48005410)
//Wakeup clock defintion
#define CM_FCLKEN_WKUP (0x48004C00)
#define CM_ICLKEN_WKUP (0x48004C10)
//Peripheral clock definition
#define CM_FCLKEN_PER (0x48005000)
#define CM_ICLKEN_PER (0x48005010)
#define CM_CLKSEL_PER (0x48005040)
//Reset management definition
#define PRM_RSTCTRL (0x48307250)
#define PRM_RSTST (0x48307258)
//CORE clock
#define CM_FCLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
#define CM_ICLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
#define CM_FCLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
#define CM_FCLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
#define CM_ICLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
#define CM_ICLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
#define CM_CLKEN_ENABLE (7UL << 0)
#define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
#define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK (1UL << 1)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE (1UL << 1)
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK (1UL << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE (1UL << 0)
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK (1UL << 0)
#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE (1UL << 0)
//Wakeup functional clock
#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
//Wakeup interface clock
#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
//Peripheral functional clock
#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
#define CM_FCLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
#define CM_FCLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
#define CM_FCLKEN_PER_EN_UART3_ENABLE (1UL << 11)
#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
#define CM_FCLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
#define CM_FCLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
#define CM_FCLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
#define CM_FCLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
#define CM_FCLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
//Peripheral interface clock
#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
#define CM_ICLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
#define CM_ICLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
#define CM_ICLKEN_PER_EN_UART3_ENABLE (1UL << 11)
#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
#define CM_ICLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
#define CM_ICLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
#define CM_ICLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
#define CM_ICLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
#define CM_ICLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
//Timer source clock selection
#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS (1UL << 1)
#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS (1UL << 2)
//Reset management (Global and Cold reset)
#define RST_GS (0x1UL << 1)
#define RST_DPLL3 (0x1UL << 2)
#define GLOBAL_SW_RST (0x1UL << 1)
#define GLOBAL_COLD_RST (0x0UL << 0)
#endif // __OMAP3530PRCM_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530TIMER_H__
#define __OMAP3530TIMER_H__
#define GPTIMER1_BASE (0x48313000)
#define GPTIMER2_BASE (0x49032000)
#define GPTIMER3_BASE (0x49034000)
#define GPTIMER4_BASE (0x49036000)
#define GPTIMER5_BASE (0x49038000)
#define GPTIMER6_BASE (0x4903A000)
#define GPTIMER7_BASE (0x4903C000)
#define GPTIMER8_BASE (0x4903E000)
#define GPTIMER9_BASE (0x49040000)
#define GPTIMER10_BASE (0x48086000)
#define GPTIMER11_BASE (0x48088000)
#define GPTIMER12_BASE (0x48304000)
#define WDTIMER2_BASE (0x48314000)
#define GPTIMER_TIOCP_CFG (0x0010)
#define GPTIMER_TISTAT (0x0014)
#define GPTIMER_TISR (0x0018)
#define GPTIMER_TIER (0x001C)
#define GPTIMER_TWER (0x0020)
#define GPTIMER_TCLR (0x0024)
#define GPTIMER_TCRR (0x0028)
#define GPTIMER_TLDR (0x002C)
#define GPTIMER_TTGR (0x0030)
#define GPTIMER_TWPS (0x0034)
#define GPTIMER_TMAR (0x0038)
#define GPTIMER_TCAR1 (0x003C)
#define GPTIMER_TSICR (0x0040)
#define GPTIMER_TCAR2 (0x0044)
#define GPTIMER_TPIR (0x0048)
#define GPTIMER_TNIR (0x004C)
#define GPTIMER_TCVR (0x0050)
#define GPTIMER_TOCR (0x0054)
#define GPTIMER_TOWR (0x0058)
#define WSPR (0x048)
#define TISR_TCAR_IT_FLAG_MASK (1UL << 2)
#define TISR_OVF_IT_FLAG_MASK (1UL << 1)
#define TISR_MAT_IT_FLAG_MASK (1UL << 0)
#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
#define TISR_OVF_IT_FLAG_NOT_PENDING (0UL << 1)
#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
#define TISR_TCAR_IT_FLAG_CLEAR (1UL << 2)
#define TISR_OVF_IT_FLAG_CLEAR (1UL << 1)
#define TISR_MAT_IT_FLAG_CLEAR (1UL << 0)
#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
#define TCLR_AR_AUTORELOAD (1UL << 1)
#define TCLR_AR_ONESHOT (0UL << 1)
#define TCLR_ST_ON (1UL << 0)
#define TCLR_ST_OFF (0UL << 0)
#define TIER_TCAR_IT_ENABLE (1UL << 2)
#define TIER_TCAR_IT_DISABLE (0UL << 2)
#define TIER_OVF_IT_ENABLE (1UL << 1)
#define TIER_OVF_IT_DISABLE (0UL << 1)
#define TIER_MAT_IT_ENABLE (1UL << 0)
#define TIER_MAT_IT_DISABLE (0UL << 0)
#endif // __OMAP3530TIMER_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530UART_H__
#define __OMAP3530UART_H__
#define UART1_BASE (0x4806A000)
#define UART2_BASE (0x4806C000)
#define UART3_BASE (0x49020000)
#define UART_DLL_REG (0x0000)
#define UART_RBR_REG (0x0000)
#define UART_THR_REG (0x0000)
#define UART_DLH_REG (0x0004)
#define UART_FCR_REG (0x0008)
#define UART_LCR_REG (0x000C)
#define UART_MCR_REG (0x0010)
#define UART_LSR_REG (0x0014)
#define UART_MDR1_REG (0x0020)
#define UART_FCR_TX_FIFO_CLEAR (1UL << 3)
#define UART_FCR_RX_FIFO_CLEAR (1UL << 3)
#define UART_FCR_FIFO_ENABLE (1UL << 3)
#define UART_LCR_DIV_EN_ENABLE (1UL << 7)
#define UART_LCR_DIV_EN_DISABLE (0UL << 7)
#define UART_LCR_CHAR_LENGTH_8 (3UL << 0)
#define UART_MCR_RTS_FORCE_ACTIVE (1UL << 1)
#define UART_MCR_DTR_FORCE_ACTIVE (1UL << 0)
#define UART_LSR_TX_FIFO_E_MASK (1UL << 5)
#define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5)
#define UART_LSR_TX_FIFO_E_EMPTY (1UL << 5)
#define UART_LSR_RX_FIFO_E_MASK (1UL << 0)
#define UART_LSR_RX_FIFO_E_NOT_EMPTY (1UL << 0)
#define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0)
#define UART_MDR1_MODE_SELECT_DISABLE (7UL << 0)
#define UART_MDR1_MODE_SELECT_UART_16X (0UL << 0)
#endif // __OMAP3530UART_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP3530USB_H__
#define __OMAP3530USB_H__
#define USB_BASE (0x48060000)
#define UHH_SYSCONFIG (USB_BASE + 0x4010)
#define UHH_HOSTCONFIG (USB_BASE + 0x4040)
#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY (1UL << 12)
#define UHH_SYSCONFIG_CLOCKACTIVITY_ON (1UL << 8)
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY (1UL << 3)
#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2)
#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9)
#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8)
#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5)
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE (1UL << 4)
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE (1UL << 3)
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE (1UL << 2)
#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1)
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0)
#endif // __OMAP3530USB_H__

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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __TPS65950_H__
#define __TPS65950_H__
#define EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(x) (((x) >> 8) & 0xFF)
#define EXTERNAL_DEVICE_REGISTER_TO_REGISTER(x) ((x) & 0xFF)
#define EXTERNAL_DEVICE_REGISTER(SlaveAddress, Register) (((SlaveAddress) & 0xFF) << 8 | ((Register) & 0xFF))
//I2C Address group
#define I2C_ADDR_GRP_ID1 0x48
#define I2C_ADDR_GRP_ID2 0x49
#define I2C_ADDR_GRP_ID3 0x4A
#define I2C_ADDR_GRP_ID4 0x4B
#define I2C_ADDR_GRP_ID5 0x12
//MMC definitions.
#define VMMC1_DEV_GRP 0x82
#define DEV_GRP_P1 (0x01UL << 5)
#define VMMC1_DEDICATED_REG 0x85
#define VSEL_1_85V 0x0
#define VSEL_2_85V 0x1
#define VSEL_3_00V 0x2
#define VSEL_3_15V 0x3
//LEDEN register
#define LEDEN 0xEE
#define LEDAON (0x1UL << 0)
#define LEDBON (0x1UL << 1)
#define LEDAPWM (0x1UL << 4)
#define LEDBPWM (0x1UL << 5)
#endif //__TPS65950_H__

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/** @file
Template for Metronome Architecture Protocol driver of the ARM flavor
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Protocol/Cpu.h>
#include <Protocol/HardwareInterrupt.h>
#include <Omap3530/Omap3530.h>
//
// Notifications
//
VOID *CpuProtocolNotificationToken = NULL;
EFI_EVENT CpuProtocolNotificationEvent = (EFI_EVENT)NULL;
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[INT_NROF_VECTORS];
/**
Shutdown our hardware
DXE Core will disable interrupts and turn off the timer and disable interrupts
after all the event handlers have run.
@param[in] Event The Event that is being processed
@param[in] Context Event Context
**/
VOID
EFIAPI
ExitBootServicesEvent (
IN EFI_EVENT Event,
IN VOID *Context
)
{
// Disable all interrupts
MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);
MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);
MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
}
/**
Register Handler for the specified interrupt source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@param Handler Callback for interrupt. NULL to unregister
@retval EFI_SUCCESS Source was updated to support Handler.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
RegisterInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN HARDWARE_INTERRUPT_HANDLER Handler
)
{
if (Source > MAX_VECTOR) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
return EFI_ALREADY_STARTED;
}
gRegisteredInterruptHandlers[Source] = Handler;
return This->EnableInterruptSource(This, Source);
}
/**
Enable interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt enabled.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
EnableInterruptSource (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
UINTN Bank;
UINTN Bit;
if (Source > MAX_VECTOR) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
Bank = Source / 32;
Bit = 1UL << (Source % 32);
MmioWrite32(INTCPS_MIR_CLEAR(Bank), Bit);
return EFI_SUCCESS;
}
/**
Disable interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt disabled.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
DisableInterruptSource(
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
UINTN Bank;
UINTN Bit;
if (Source > MAX_VECTOR) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
Bank = Source / 32;
Bit = 1UL << (Source % 32);
MmioWrite32(INTCPS_MIR_SET(Bank), Bit);
return EFI_SUCCESS;
}
/**
Return current state of interrupt source Source.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@param InterruptState TRUE: source enabled, FALSE: source disabled.
@retval EFI_SUCCESS InterruptState is valid
@retval EFI_DEVICE_ERROR InterruptState is not valid
**/
EFI_STATUS
EFIAPI
GetInterruptSourceState (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source,
IN BOOLEAN *InterruptState
)
{
UINTN Bank;
UINTN Bit;
if (InterruptState == NULL) {
return EFI_INVALID_PARAMETER;
}
if (Source > MAX_VECTOR) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
Bank = Source / 32;
Bit = 1UL << (Source % 32);
if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {
*InterruptState = FALSE;
} else {
*InterruptState = TRUE;
}
return EFI_SUCCESS;
}
/**
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
@param InterruptType Defines the type of interrupt or exception that
occurred on the processor.This parameter is processor architecture specific.
@param SystemContext A pointer to the processor context when
the interrupt occurred on the processor.
@return None
**/
VOID
EFIAPI
IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 Vector;
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
InterruptHandler = gRegisteredInterruptHandlers[Vector];
if (InterruptHandler != NULL) {
// Call the registered interrupt handler.
InterruptHandler(Vector, SystemContext);
}
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
}
//
// Making this global saves a few bytes in image size
//
EFI_HANDLE gHardwareInterruptHandle = NULL;
//
// The protocol instance produced by this driver
//
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
RegisterInterruptSource,
EnableInterruptSource,
DisableInterruptSource,
GetInterruptSourceState
};
//
// Notification routines
//
VOID
CpuProtocolInstalledNotification (
IN EFI_EVENT Event,
IN VOID *Context
)
{
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
//
// Get the cpu protocol that this driver requires.
//
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
//
// Unregister the default exception handler.
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
ASSERT_EFI_ERROR(Status);
//
// Register to receive interrupts
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
ASSERT_EFI_ERROR(Status);
}
/**
Initialize the state information for the CPU Architectural Protocol
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
// Make sure all interrupts are disabled by default.
MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);
MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);
MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
NULL);
ASSERT_EFI_ERROR(Status);
// Set up to be notified when the Cpu protocol is installed.
Status = gBS->CreateEvent(EVT_NOTIFY_SIGNAL, TPL_CALLBACK, CpuProtocolInstalledNotification, NULL, &CpuProtocolNotificationEvent);
ASSERT_EFI_ERROR(Status);
Status = gBS->RegisterProtocolNotify(&gEfiCpuArchProtocolGuid, CpuProtocolNotificationEvent, (VOID *)&CpuProtocolNotificationToken);
ASSERT_EFI_ERROR(Status);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
ASSERT_EFI_ERROR(Status);
return Status;
}

56
BeagleBoardPkg/InterruptDxe/InterruptDxe.inf Normal file
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@@ -0,0 +1,56 @@
#%HEADER%
#/** @file
#
# Interrupt DXE driver
#
# Copyright (c) 2009, Apple, Inc <BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardInterruptDxe
FILE_GUID = 23eed05d-1b93-4a1a-8e1b-931d69e37952
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InterruptDxeInitialize
[Sources.common]
HardwareInterrupt.c
[Packages]
BeagleBoardPkg/BeagleBoardPkg.dec
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
BaseLib
UefiLib
UefiBootServicesTableLib
DebugLib
PrintLib
UefiDriverEntryPoint
IoLib
[Guids]
[Protocols]
gHardwareInterruptProtocolGuid
gEfiCpuArchProtocolGuid
[FixedPcd.common]
gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress
[depex]
TRUE

110
BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Uefi.h>
#include <Library/ArmLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/BeagleBoardSystemLib.h>
#include <Omap3530/Omap3530.h>
VOID
ResetSystem (
IN EFI_RESET_TYPE ResetType
)
{
switch (ResetType) {
case EfiResetWarm:
//Perform warm reset of the system.
GoLittleEndian(PcdGet32(PcdFlashFvMainBase));
break;
case EfiResetCold:
case EfiResetShutdown:
default:
//Perform cold reset of the system.
MmioOr32(PRM_RSTCTRL, RST_DPLL3);
while ((MmioRead32(PRM_RSTST) & GLOBAL_COLD_RST) != 0x1);
break;
}
//Should never come here.
ASSERT(FALSE);
}
VOID
ShutdownEfi (
VOID
)
{
EFI_STATUS Status;
UINTN MemoryMapSize;
EFI_MEMORY_DESCRIPTOR *MemoryMap;
UINTN MapKey;
UINTN DescriptorSize;
UINTN DescriptorVersion;
UINTN Pages;
MemoryMap = NULL;
MemoryMapSize = 0;
do {
Status = gBS->GetMemoryMap (
&MemoryMapSize,
MemoryMap,
&MapKey,
&DescriptorSize,
&DescriptorVersion
);
if (Status == EFI_BUFFER_TOO_SMALL) {
Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
MemoryMap = AllocatePages (Pages);
//
// Get System MemoryMap
//
Status = gBS->GetMemoryMap (
&MemoryMapSize,
MemoryMap,
&MapKey,
&DescriptorSize,
&DescriptorVersion
);
// Don't do anything between the GetMemoryMap() and ExitBootServices()
if (!EFI_ERROR (Status)) {
Status = gBS->ExitBootServices (gImageHandle, MapKey);
if (EFI_ERROR (Status)) {
FreePages (MemoryMap, Pages);
MemoryMap = NULL;
MemoryMapSize = 0;
}
}
}
} while (EFI_ERROR (Status));
//Clean and invalidate caches.
WriteBackInvalidateDataCache();
InvalidateInstructionCache();
//Turning off Caches and MMU
ArmDisableDataCache();
ArmDisableInstructionCache();
ArmDisableMmu();
}

45
BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf Normal file
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@@ -0,0 +1,45 @@
#%HEADER%
#/** @file
# Support for Airport libraries.
#
# Copyright (c) 2009, Apple Inc.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardSystemLib
FILE_GUID = b15a2640-fef2-447c-98e1-9ce22cfa529c
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = BeagleBoardSystemLib
[Sources.ARM]
BeagleBoardSystemLib.c
GoLittleEndian.asm | RVCT
GoLittleEndian.S | GCC
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
ArmLib
CacheMaintenanceLib
MemoryAllocationLib
UefiRuntimeServicesTableLib
TimerLib
UefiLib
[Pcd]
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase

27
BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.S Normal file
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@@ -0,0 +1,27 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 3
.globl ASM_PFX(GoLittleEndian)
// r0 is target address
ASM_PFX(GoLittleEndian):
// Switch to SVC Mode
mov r2,#0xD3 // SVC mode
msr CPSR_c,r2 // Switch modes
bx r0

27
BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.asm Executable file
View File

@@ -0,0 +1,27 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT GoLittleEndian
PRESERVE8
AREA Ebl, CODE, READONLY
// r0 is target address
GoLittleEndian
// Switch to SVC Mode
mov r2,#0xD3 // SVC mode
msr CPSR_c,r2 // Switch modes
bx r0
END

46
BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf Normal file
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@@ -0,0 +1,46 @@
#%HEADER%
#/** @file
# Timer library implementation
#
# A non-functional instance of the Timer Library that can be used as a template
# for the implementation of a functional timer library instance. This library instance can
# also be used to test build DXE, Runtime, DXE SAL, and DXE SMM modules that require timer
# services as well as EBC modules that require timer services
# Copyright (c) 2007, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardTimerLib
FILE_GUID = fe1d7183-9abb-42ce-9a3b-36d7c6a8959f
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = TimerLib
[Sources.common]
TimerLib.c
[Packages]
BeagleBoardPkg/BeagleBoardPkg.dec
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
DebugLib
OmapLib
IoLib
[Pcd]
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFreqencyInHz
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds
gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer

102
BeagleBoardPkg/Library/BeagleBoardTimerLib/TimerLib.c Executable file
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@@ -0,0 +1,102 @@
/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/TimerLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Omap3530/Omap3530.h>
UINTN
EFIAPI
MicroSecondDelay (
IN UINTN MicroSeconds
)
{
UINT64 NanoSeconds;
NanoSeconds = MultU64x32(MicroSeconds, 1000);
while (NanoSeconds > (UINTN)-1) {
NanoSecondDelay((UINTN)-1);
NanoSeconds -= (UINTN)-1;
}
NanoSecondDelay(NanoSeconds);
return MicroSeconds;
}
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
)
{
UINT32 Delay;
UINT32 StartTime;
UINT32 CurrentTime;
UINT32 ElapsedTime;
UINT32 TimerCountRegister;
Delay = (NanoSeconds / PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds)) + 1;
TimerCountRegister = TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TCRR;
StartTime = MmioRead32(TimerCountRegister);
do
{
CurrentTime = MmioRead32(TimerCountRegister);
ElapsedTime = CurrentTime - StartTime;
} while (ElapsedTime < Delay);
NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds);
return NanoSeconds;
}
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return (UINT64)MmioRead32(TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TCRR);
}
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
// Timer starts with the reload value
*StartValue = (UINT64)MmioRead32(TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TLDR);
}
if (EndValue != NULL) {
// Timer counts up to 0xFFFFFFFF
*EndValue = 0xFFFFFFFF;
}
return PcdGet64(PcdEmbeddedPerformanceCounterFreqencyInHz);
}

42
BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.c Normal file
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@@ -0,0 +1,42 @@
/** @file
Add custom commands for BeagleBoard development.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/ArmLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/EblCmdLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/EfiFileLib.h>
GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] =
{
};
VOID
EblInitializeExternalCmd (
VOID
)
{
EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE));
return;
}

49
BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf Normal file
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@@ -0,0 +1,49 @@
#%HEADER%
#/** @file
# Component description file for the entry point to a EFIDXE Drivers
#
# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification
# Copyright (c) 2007 - 2007, Intel Corporation
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardEblCmdLib
FILE_GUID = ea62bdc3-1063-425f-8851-98cb47f213a8
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources.common]
EblCmdLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
DebugLib
[Protocols]
[Guids]
[Pcd]

103
BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.c Normal file
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@@ -0,0 +1,103 @@
/** @file
Basic serial IO abstaction for GDB
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Uefi.h>
#include <Library/GdbSerialLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/OmapLib.h>
#include <Omap3530/Omap3530.h>
RETURN_STATUS
EFIAPI
GdbSerialLibConstructor (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
return RETURN_SUCCESS;
}
RETURN_STATUS
EFIAPI
GdbSerialInit (
IN UINT64 BaudRate,
IN UINT8 Parity,
IN UINT8 DataBits,
IN UINT8 StopBits
)
{
return RETURN_SUCCESS;
}
BOOLEAN
EFIAPI
GdbIsCharAvailable (
VOID
)
{
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
return TRUE;
} else {
return FALSE;
}
}
CHAR8
EFIAPI
GdbGetChar (
VOID
)
{
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
UINT32 RBR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_RBR_REG;
CHAR8 Char;
while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
Char = MmioRead8(RBR);
return Char;
}
VOID
EFIAPI
GdbPutChar (
IN CHAR8 Char
)
{
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
UINT32 THR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_THR_REG;
while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
MmioWrite8(THR, Char);
}
VOID
GdbPutString (
IN CHAR8 *String
)
{
while (*String != '\0') {
GdbPutChar (*String);
String++;
}
}

29
BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf Normal file
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@@ -0,0 +1,29 @@
#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = GdbSerialLib
FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = GdbSerialLib
CONSTRUCTOR = GdbSerialLibConstructor
[Sources.common]
GdbSerialLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
DebugLib
IoLib
OmapLib
[FixedPcd]
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart

83
BeagleBoardPkg/Library/OmapLib/OmapLib.c Normal file
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@@ -0,0 +1,83 @@
/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/OmapLib.h>
#include <Omap3530/Omap3530.h>
UINT32
GpioBase (
IN UINTN Port
)
{
switch (Port) {
case 1: return GPIO1_BASE;
case 2: return GPIO2_BASE;
case 3: return GPIO3_BASE;
case 4: return GPIO4_BASE;
case 5: return GPIO5_BASE;
case 6: return GPIO6_BASE;
default: ASSERT(FALSE); return 0;
}
}
UINT32
TimerBase (
IN UINTN Timer
)
{
switch (Timer) {
case 1: return GPTIMER1_BASE;
case 2: return GPTIMER2_BASE;
case 3: return GPTIMER3_BASE;
case 4: return GPTIMER4_BASE;
case 5: return GPTIMER5_BASE;
case 6: return GPTIMER6_BASE;
case 7: return GPTIMER7_BASE;
case 8: return GPTIMER8_BASE;
case 9: return GPTIMER9_BASE;
case 10: return GPTIMER10_BASE;
case 11: return GPTIMER11_BASE;
case 12: return GPTIMER12_BASE;
default: return 0;
}
}
UINTN
InterruptVectorForTimer (
IN UINTN Timer
)
{
if ((Timer < 1) || (Timer > 12)) {
ASSERT(FALSE);
return 0xFFFFFFFF;
}
return 36 + Timer;
}
UINT32
UartBase (
IN UINTN Uart
)
{
switch (Uart) {
case 1: return UART1_BASE;
case 2: return UART2_BASE;
case 3: return UART3_BASE;
default: ASSERT(FALSE); return 0;
}
}

25
BeagleBoardPkg/Library/OmapLib/OmapLib.inf Normal file
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@@ -0,0 +1,25 @@
#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = OmapLib
FILE_GUID = d035f5c2-1b92-4746-9f6c-5ff6202970df
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = OmapLib
[Sources.common]
OmapLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
DebugLib
[Protocols]
[Guids]
[Pcd]

84
BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.c Normal file
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@@ -0,0 +1,84 @@
/** @file
Template library implementation to support ResetSystem Runtime call.
Fill in the templates with what ever makes you system reset.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/PcdLib.h>
#include <Library/ArmLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/DebugLib.h>
#include <Library/EfiResetSystemLib.h>
#include <Library/BeagleBoardSystemLib.h>
/**
Resets the entire platform.
@param ResetType The type of reset to perform.
@param ResetStatus The status code for the reset.
@param DataSize The size, in bytes, of WatchdogData.
@param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
EfiResetShutdown the data buffer starts with a Null-terminated
Unicode string, optionally followed by additional binary data.
**/
EFI_STATUS
EFIAPI
LibResetSystem (
IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus,
IN UINTN DataSize,
IN CHAR16 *ResetData OPTIONAL
)
{
if (ResetData != NULL) {
DEBUG((EFI_D_ERROR, "%s", ResetData));
}
//Shutdown EFI services.
ShutdownEfi();
//Reset the sytem.
ResetSystem(ResetType);
// If the reset didn't work, return an error.
return EFI_DEVICE_ERROR;
}
/**
Initialize any infrastructure required for LibResetSystem () to function.
@param ImageHandle The firmware allocated handle for the EFI image.
@param SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
**/
EFI_STATUS
EFIAPI
LibInitializeResetSystem (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
return EFI_SUCCESS;
}

41
BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf Normal file
View File

@@ -0,0 +1,41 @@
#%HEADER%
#/** @file
# Reset System lib to make it easy to port new platforms
#
# Copyright (c) 2008, Apple Inc.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardResetSystemLib
FILE_GUID = 781371a2-3fdd-41d4-96a1-7b34cbc9e895
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = EfiResetSystemLib
[Sources.common]
ResetSystemLib.c
[Packages]
BeagleBoardPkg/BeagleBoardPkg.dec
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[Pcd.common]
gArmTokenSpaceGuid.PcdCpuResetAddress
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
[LibraryClasses]
DebugLib
BeagleBoardSystemLib

124
BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.c Normal file
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/** @file
Serial I/O Port library functions with no library constructor/destructor
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/SerialPortLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Omap3530/Omap3530.h>
/*
Programmed hardware of Serial port.
@return Always return EFI_UNSUPPORTED.
**/
RETURN_STATUS
EFIAPI
SerialPortInitialize (
VOID
)
{
// assume assembly code at reset vector has setup UART
return RETURN_SUCCESS;
}
/**
Write data to serial device.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed.
@retval !0 Actual number of bytes writed to serial device.
**/
UINTN
EFIAPI
SerialPortWrite (
IN UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
UINT32 THR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_THR_REG;
UINTN Count;
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
MmioWrite8(THR, *Buffer);
}
return NumberOfBytes;
}
/**
Read data from serial device and save the datas in buffer.
@param Buffer Point of data buffer which need to be writed.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.
@retval !0 Aactual number of bytes read from serial device.
**/
UINTN
EFIAPI
SerialPortRead (
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes
)
{
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
UINT32 RBR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_RBR_REG;
UINTN Count;
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
*Buffer = MmioRead8(RBR);
}
return NumberOfBytes;
}
/**
Check to see if any data is avaiable to be read from the debug device.
@retval EFI_SUCCESS At least one byte of data is avaiable to be read
@retval EFI_NOT_READY No data is avaiable to be read
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
**/
BOOLEAN
EFIAPI
SerialPortPoll (
VOID
)
{
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
return TRUE;
} else {
return FALSE;
}
}

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BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf Normal file
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#%HEADER%
#/** @file
# EDK Serial port lib
#
# Copyright (c) 2009, Apple Inc.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardSerialPortLib
FILE_GUID = 97546cbd-c0ff-4c48-ab0b-e4f58862acd3
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
LIBRARY_CLASS = SerialPortLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
#
[Sources.common]
SerialPortLib.c
[LibraryClasses]
DebugLib
IoLib
OmapLib
[Packages]
MdePkg/MdePkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[FixedPcd]
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart

1018
BeagleBoardPkg/MMCHSDxe/MMCHS.c Normal file
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BeagleBoardPkg/MMCHSDxe/MMCHS.h Executable file
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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _MMCHS_H_
#define _MMCHS_H_
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/BlockIo.h>
#include <Protocol/Cpu.h>
#include <Protocol/DevicePath.h>
#include <Omap3530/Omap3530.h>
#include <TPS65950.h>
#define MAX_RETRY_COUNT 100
#define HCS (0x1UL << 30) //Host capacity support/1 = Supporting high capacity
#define CCS (0x1UL << 30) //Card capacity status/1 = High capacity card
typedef struct {
UINT32 Reserved0: 7; // 0
UINT32 V170_V195: 1; // 1.70V - 1.95V
UINT32 V200_V260: 7; // 2.00V - 2.60V
UINT32 V270_V360: 9; // 2.70V - 3.60V
UINT32 RESERVED_1: 5; // Reserved
UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
}OCR;
typedef struct {
UINT32 NOT_USED; // 1 [0:0]
UINT32 CRC; // CRC7 checksum [7:1]
UINT32 MDT; // Manufacturing date [19:8]
UINT32 RESERVED_1; // Reserved [23:20]
UINT32 PSN; // Product serial number [55:24]
UINT8 PRV; // Product revision [63:56]
UINT8 PNM[5]; // Product name [64:103]
UINT16 OID; // OEM/Application ID [119:104]
UINT8 MID; // Manufacturer ID [127:120]
}CID;
typedef struct {
UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
UINT8 CRC: 7; // CRC [7:1]
UINT8 RESERVED_1: 2; // Reserved [9:8]
UINT8 FILE_FORMAT: 2; // File format [11:10]
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
UINT16 RESERVED_2: 5; // Reserved [20:16]
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
UINT16 RESERVED_3: 2; // Reserved [30:29]
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]
UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]
UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
UINT32 C_SIZELow2: 2; // Device size [73:62]
UINT32 C_SIZEHigh10: 10;// Device size [73:62]
UINT32 RESERVED_4: 2; // Reserved [75:74]
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
UINT32 CCC: 12;// Card command classes [95:84]
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
UINT8 TAAC ; // Data read access-time 1 [119:112]
UINT8 RESERVED_5: 6; // Reserved [125:120]
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
}CSD;
typedef struct {
UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
UINT8 CRC: 7; // CRC [7:1]
UINT8 RESERVED_1: 2; // Reserved [9:8]
UINT8 FILE_FORMAT: 2; // File format [11:10]
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
UINT16 RESERVED_2: 5; // Reserved [20:16]
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
UINT16 RESERVED_3: 2; // Reserved [30:29]
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
UINT16 RESERVED_4: 1; // Reserved [47:47]
UINT32 C_SIZELow16: 16;// Device size [69:48]
UINT32 C_SIZEHigh6: 6; // Device size [69:48]
UINT32 RESERVED_5: 6; // Reserved [75:70]
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
UINT16 CCC: 12;// Card command classes [95:84]
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
UINT8 TAAC ; // Data read access-time 1 [119:112]
UINT8 RESERVED_6: 6; // 0 [125:120]
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
}CSD_SDV2;
typedef enum {
UNKNOWN_CARD,
MMC_CARD, //MMC card
SD_CARD, //SD 1.1 card
SD_CARD_2, //SD 2.0 or above standard card
SD_CARD_2_HIGH //SD 2.0 or above high capacity card
} CARD_TYPE;
typedef enum {
READ,
WRITE
} OPERATION_TYPE;
typedef struct
{
UINT16 RCA;
UINTN BlockSize;
UINTN NumBlocks;
UINTN ClockFrequencySelect;
CARD_TYPE CardType;
OCR OCRData;
CID CIDData;
CSD CSDData;
} CARD_INFO;
#endif

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BeagleBoardPkg/MMCHSDxe/MMCHS.inf Normal file
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#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = MMCHS
FILE_GUID = 100c2cfa-b586-4198-9b4c-1683d195b1da
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = MMCHSInitialize
[Sources.common]
MMCHS.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
IoLib
[Guids]
[Protocols]
gEfiBlockIoProtocolGuid
gEfiCpuArchProtocolGuid
gEfiDevicePathProtocolGuid
gEmbeddedExternalDeviceProtocolGuid
[Pcd]
gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base
[depex]
gEmbeddedExternalDeviceProtocolGuid

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BeagleBoardPkg/PciEmulation/PciEmulation.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PciEmulation.h"
#include <Omap3530/Omap3530.h>
EFI_CPU_ARCH_PROTOCOL *gCpu;
EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
typedef struct {
ACPI_HID_DEVICE_PATH AcpiDevicePath;
PCI_DEVICE_PATH PciDevicePath;
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} EFI_PCI_IO_DEVICE_PATH;
typedef struct {
UINT32 Signature;
EFI_PCI_IO_DEVICE_PATH DevicePath;
EFI_PCI_IO_PROTOCOL PciIoProtocol;
PCI_TYPE00 *ConfigSpace;
PCI_ROOT_BRIDGE RootBridge;
UINTN Segment;
} EFI_PCI_IO_PRIVATE_DATA;
#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
{
{
{ ACPI_DEVICE_PATH, ACPI_DP, sizeof (ACPI_HID_DEVICE_PATH), 0},
EISA_PNP_ID(0x0A03), // HID
0 // UID
},
{
{ HARDWARE_DEVICE_PATH, HW_PCI_DP, sizeof (PCI_DEVICE_PATH), 0},
0,
0
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
};
STATIC
VOID
ConfigureUSBHost (
VOID
)
{
EFI_STATUS Status;
UINT8 Data = 0;
// Take USB host out of force-standby mode
MmioWrite32(UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
MmioWrite32(UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
| UHH_HOSTCONFIG_ENA_INCR16_ENABLE
| UHH_HOSTCONFIG_ENA_INCR8_ENABLE
| UHH_HOSTCONFIG_ENA_INCR4_ENABLE
| UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
| UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
// USB reset (GPIO 147 - Port 5 pin 19) output high
MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
MmioWrite32(GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
// Get the Power IC protocol.
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR(Status);
//Enable power to the USB host.
Status = gTPS65950->Read(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
ASSERT_EFI_ERROR(Status);
//LEDAON & LEDAPWM control the power to the USB host so enable those bits.
Data |= (LEDAON | LEDAPWM);
Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
ASSERT_EFI_ERROR(Status);
}
EFI_STATUS
PciIoPollMem (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoPollIo (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoMemRead (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
Count,
Buffer
);
}
EFI_STATUS
PciIoMemWrite (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
Count,
Buffer
);
}
EFI_STATUS
PciIoIoRead (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoIoWrite (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 BarIndex,
IN UINT64 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoPciRead (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Count,
TRUE,
(PTR)(UINTN)Buffer,
TRUE,
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)
);
}
EFI_STATUS
PciIoPciWrite (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT32 Offset,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Count,
TRUE,
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
TRUE,
(PTR)(UINTN)Buffer
);
}
EFI_STATUS
PciIoCopyMem (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
IN UINT8 DestBarIndex,
IN UINT64 DestOffset,
IN UINT8 SrcBarIndex,
IN UINT64 SrcOffset,
IN UINTN Count
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoMap (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
)
{
MAP_INFO_INSTANCE *Map;
EFI_STATUS Status;
if ( HostAddress == NULL || NumberOfBytes == NULL ||
DeviceAddress == NULL || Mapping == NULL ) {
return EFI_INVALID_PARAMETER;
}
if (Operation >= EfiPciOperationMaximum) {
return EFI_INVALID_PARAMETER;
}
*DeviceAddress = ConvertToPhysicalAddress (HostAddress);
// Data cache flush (HostAddress, NumberOfBytes);
// Remember range so we can flush on the other side
Status = gBS->AllocatePool (EfiBootServicesData, sizeof (PCI_DMA_MAP), (VOID **) &Map);
if (EFI_ERROR(Status)) {
return EFI_OUT_OF_RESOURCES;
}
*Mapping = Map;
Map->HostAddress = (UINTN)HostAddress;
Map->DeviceAddress = *DeviceAddress;
Map->NumberOfBytes = *NumberOfBytes;
Map->Operation = Operation;
// EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
return EFI_SUCCESS;
}
EFI_STATUS
PciIoUnmap (
IN EFI_PCI_IO_PROTOCOL *This,
IN VOID *Mapping
)
{
PCI_DMA_MAP *Map;
if (Mapping == NULL) {
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
}
Map = (PCI_DMA_MAP *)Mapping;
if (Map->Operation == EfiPciOperationBusMasterWrite) {
//
// Make sure we read buffer from uncached memory and not the cache
//
gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
} else if (Map->Operation == EfiPciOperationBusMasterCommonBuffer) {
//
// CPU was using uncached address, so anything in the cached range is bogus
//
gCpu->FlushDataCache (gCpu, Map->DeviceAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
}
FreePool (Map);
return EFI_SUCCESS;
}
EFI_STATUS
PciIoAllocateBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress,
IN UINT64 Attributes
)
{
if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
return EFI_UNSUPPORTED;
}
if (HostAddress == NULL) {
return EFI_INVALID_PARAMETER;
}
//
// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
//
// We used uncached memory to keep coherency
//
if (MemoryType == EfiBootServicesData) {
*HostAddress = UncachedAllocatePages (Pages);
} else if (MemoryType != EfiRuntimeServicesData) {
*HostAddress = UncachedAllocateRuntimePages (Pages);
} else {
return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
}
EFI_STATUS
PciIoFreeBuffer (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINTN Pages,
IN VOID *HostAddress
)
{
if (HostAddress == NULL) {
return EFI_INVALID_PARAMETER;
}
UncachedFreePages (HostAddress, Pages);
return EFI_SUCCESS;
}
EFI_STATUS
PciIoFlush (
IN EFI_PCI_IO_PROTOCOL *This
)
{
return EFI_SUCCESS;
}
EFI_STATUS
PciIoGetLocation (
IN EFI_PCI_IO_PROTOCOL *This,
OUT UINTN *SegmentNumber,
OUT UINTN *BusNumber,
OUT UINTN *DeviceNumber,
OUT UINTN *FunctionNumber
)
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
if (SegmentNumber != NULL) {
*SegmentNumber = Private->Segment;
}
if (BusNumber != NULL) {
*BusNumber = 0xff;
}
if (DeviceNumber != NULL) {
*DeviceNumber = 0;
}
if (FunctionNumber != NULL) {
*FunctionNumber = 0;
}
return EFI_SUCCESS;
}
EFI_STATUS
PciIoAttributes (
IN EFI_PCI_IO_PROTOCOL *This,
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
IN UINT64 Attributes,
OUT UINT64 *Result OPTIONAL
)
{
switch (Operation) {
case EfiPciIoAttributeOperationGet:
case EfiPciIoAttributeOperationSupported:
if (Result == NULL) {
return EFI_INVALID_PARAMETER;
}
// We are not a real PCI device so just say things we kind of do
*Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE;
break;
case EfiPciIoAttributeOperationSet:
case EfiPciIoAttributeOperationEnable:
case EfiPciIoAttributeOperationDisable:
// Since we are not a real PCI device no enable/set or disable operations exist.
return EFI_SUCCESS;
break;
default:
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
};
return EFI_SUCCESS;
}
EFI_STATUS
PciIoGetBarAttributes (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT8 BarIndex,
OUT UINT64 *Supports, OPTIONAL
OUT VOID **Resources OPTIONAL
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_STATUS
PciIoSetBarAttributes (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN UINT8 BarIndex,
IN OUT UINT64 *Offset,
IN OUT UINT64 *Length
)
{
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
EFI_PCI_IO_PROTOCOL PciIoTemplate =
{
PciIoPollMem,
PciIoPollIo,
PciIoMemRead,
PciIoMemWrite,
PciIoIoRead,
PciIoIoWrite,
PciIoPciRead,
PciIoPciWrite,
PciIoCopyMem,
PciIoMap,
PciIoUnmap,
PciIoAllocateBuffer,
PciIoFreeBuffer,
PciIoFlush,
PciIoGetLocation,
PciIoAttributes,
PciIoGetBarAttributes,
PciIoSetBarAttributes,
0,
0
};
EFI_STATUS
EFIAPI
PciEmulationEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
EFI_PCI_IO_PRIVATE_DATA *Private;
UINT8 CapabilityLength;
UINT8 PhysicalPorts;
UINTN Count;
// Get the Cpu protocol for later use
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
ASSERT_EFI_ERROR(Status);
//Configure USB host for OMAP3530.
ConfigureUSBHost();
// Create a private structure
Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));
if (Private == NULL) {
Status = EFI_OUT_OF_RESOURCES;
return Status;
}
Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE; // Get the USB capability register base
Private->Segment = 0; // Default to segment zero
// Find out the capability register length and number of physical ports.
CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);
PhysicalPorts = (MmioRead32(Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
// Calculate the total size of the USB registers.
Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
// Enable Port Power bit in Port status and control registers in EHCI register space.
// Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
// host controller implementation includes port power control.
for (Count = 0; Count < PhysicalPorts; Count++) {
MmioOr32((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
}
// Create fake PCI config space.
Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));
if (Private->ConfigSpace == NULL) {
Status = EFI_OUT_OF_RESOURCES;
FreePool(Private);
return Status;
}
// Configure PCI config space
Private->ConfigSpace->Hdr.VendorId = 0x3530;
Private->ConfigSpace->Hdr.DeviceId = 0x3530;
Private->ConfigSpace->Hdr.ClassCode[0] = 0x20;
Private->ConfigSpace->Hdr.ClassCode[1] = 0x03;
Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C;
Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;
Handle = NULL;
// Unique device path.
CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));
Private->DevicePath.AcpiDevicePath.UID = 0;
// Copy protocol structure
CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));
Status = gBS->InstallMultipleProtocolInterfaces(&Handle,
&gEfiPciIoProtocolGuid, &Private->PciIoProtocol,
&gEfiDevicePathProtocolGuid, &Private->DevicePath,
NULL);
if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));
}
return Status;
}

305
BeagleBoardPkg/PciEmulation/PciEmulation.h Normal file
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/** @file
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PCI_ROOT_BRIDGE_H_
#define _PCI_ROOT_BRIDGE_H_
#include <PiDxe.h>
#include <TPS65950.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PciLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UncachedMemoryAllocationLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/Cpu.h>
#include <Protocol/DevicePath.h>
#include <Protocol/PciIo.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <IndustryStandard/Pci22.h>
#include <IndustryStandard/Acpi.h>
extern EFI_CPU_ARCH_PROTOCOL *gCpu;
#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL
typedef struct {
ACPI_HID_DEVICE_PATH AcpiDevicePath;
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
#define ACPI_CONFIG_IO 0
#define ACPI_CONFIG_MMIO 1
#define ACPI_CONFIG_BUS 2
typedef struct {
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];
EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
} ACPI_CONFIG_INFO;
#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')
typedef struct {
UINT32 Signature;
EFI_HANDLE Handle;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
UINT8 StartBus;
UINT8 EndBus;
UINT16 Type;
UINT32 MemoryStart;
UINT32 MemorySize;
UINTN IoOffset;
UINT32 IoStart;
UINT32 IoSize;
UINT64 PciAttributes;
ACPI_CONFIG_INFO *Config;
} PCI_ROOT_BRIDGE;
#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
typedef union {
UINT8 volatile *buf;
UINT8 volatile *ui8;
UINT16 volatile *ui16;
UINT32 volatile *ui32;
UINT64 volatile *ui64;
UINTN volatile ui;
} PTR;
typedef struct {
EFI_PHYSICAL_ADDRESS HostAddress;
EFI_PHYSICAL_ADDRESS DeviceAddress;
UINTN NumberOfBytes;
EFI_PCI_IO_PROTOCOL_OPERATION Operation;
} MAP_INFO_INSTANCE;
typedef struct {
EFI_PHYSICAL_ADDRESS HostAddress;
EFI_PHYSICAL_ADDRESS DeviceAddress;
UINTN NumberOfBytes;
EFI_PCI_IO_PROTOCOL_OPERATION Operation;
} PCI_DMA_MAP;
EFI_STATUS
EFIAPI
PciRootBridgeIoPollMem (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
);
EFI_STATUS
EFIAPI
PciRootBridgeIoPollIo (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINT64 Mask,
IN UINT64 Value,
IN UINT64 Delay,
OUT UINT64 *Result
);
EFI_STATUS
EFIAPI
PciRootBridgeIoMemRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoMemWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoIoRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 UserAddress,
IN UINTN Count,
IN OUT VOID *UserBuffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoIoWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 UserAddress,
IN UINTN Count,
IN OUT VOID *UserBuffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoCopyMem (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 DestAddress,
IN UINT64 SrcAddress,
IN UINTN Count
);
EFI_STATUS
EFIAPI
PciRootBridgeIoPciRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoPciWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
);
EFI_STATUS
EFIAPI
PciRootBridgeIoMap (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
EFI_STATUS
EFIAPI
PciRootBridgeIoUnmap (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN VOID *Mapping
);
EFI_STATUS
EFIAPI
PciRootBridgeIoAllocateBuffer (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_ALLOCATE_TYPE Type,
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress,
IN UINT64 Attributes
);
EFI_STATUS
EFIAPI
PciRootBridgeIoFreeBuffer (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN UINTN Pages,
OUT VOID *HostAddress
);
EFI_STATUS
EFIAPI
PciRootBridgeIoFlush (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
);
EFI_STATUS
EFIAPI
PciRootBridgeIoGetAttributes (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
OUT UINT64 *Supported,
OUT UINT64 *Attributes
);
EFI_STATUS
EFIAPI
PciRootBridgeIoSetAttributes (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN OUT UINT64 *ResourceBase,
IN OUT UINT64 *ResourceLength
);
EFI_STATUS
EFIAPI
PciRootBridgeIoConfiguration (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
OUT VOID **Resources
);
//
// Private Function Prototypes
//
EFI_STATUS
EFIAPI
PciRootBridgeIoMemRW (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINTN Count,
IN BOOLEAN InStrideFlag,
IN PTR In,
IN BOOLEAN OutStrideFlag,
OUT PTR Out
);
BOOLEAN
PciIoMemAddressValid (
IN EFI_PCI_IO_PROTOCOL *This,
IN UINT64 Address
);
EFI_STATUS
EmulatePciIoForEhci (
INTN MvPciIfMaxIf
);
#endif

58
BeagleBoardPkg/PciEmulation/PciEmulation.inf Normal file
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#%HEADER%
/** @file
Copyright (c) 2009 Apple, Inc. All rights reserved.
This document is the property of Apple, Inc.
It is considered confidential and proprietary.
This document may not be reproduced or transmitted in any form,
in whole or in part, without the express written permission of
Apple, Inc.
**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardPciEmulation
FILE_GUID = feaa2e2b-53ac-4d5e-ae10-1efd5da4a2ba
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = PciEmulationEntryPoint
[Sources.common]
PciRootBridgeIo.c
PciEmulation.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
ArmPkg/ArmPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
BaseLib
DxeServicesTableLib
UefiLib
UefiBootServicesTableLib
UefiDriverEntryPoint
UefiRuntimeServicesTableLib
UncachedMemoryAllocationLib
IoLib
[Protocols]
gEfiPciRootBridgeIoProtocolGuid
gEfiDevicePathProtocolGuid
gEfiPciHostBridgeResourceAllocationProtocolGuid
gEfiCpuArchProtocolGuid
gEfiPciIoProtocolGuid
gEmbeddedExternalDeviceProtocolGuid
[Depex]
gEfiMetronomeArchProtocolGuid AND
gEfiCpuArchProtocolGuid AND
gEmbeddedExternalDeviceProtocolGuid

306
BeagleBoardPkg/PciEmulation/PciRootBridgeIo.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PciEmulation.h"
BOOLEAN
PciRootBridgeMemAddressValid (
IN PCI_ROOT_BRIDGE *Private,
IN UINT64 Address
)
{
if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {
return TRUE;
}
return FALSE;
}
EFI_STATUS
PciRootBridgeIoMemRW (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINTN Count,
IN BOOLEAN InStrideFlag,
IN PTR In,
IN BOOLEAN OutStrideFlag,
OUT PTR Out
)
{
UINTN Stride;
UINTN InStride;
UINTN OutStride;
Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
Stride = (UINTN)1 << Width;
InStride = InStrideFlag ? Stride : 0;
OutStride = OutStrideFlag ? Stride : 0;
//
// Loop for each iteration and move the data
//
switch (Width) {
case EfiPciWidthUint8:
for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
*In.ui8 = *Out.ui8;
}
break;
case EfiPciWidthUint16:
for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
*In.ui16 = *Out.ui16;
}
break;
case EfiPciWidthUint32:
for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
*In.ui32 = *Out.ui32;
}
break;
default:
return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
}
EFI_STATUS
PciRootBridgeIoPciRW (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN BOOLEAN Write,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 UserAddress,
IN UINTN Count,
IN OUT VOID *UserBuffer
)
{
return EFI_SUCCESS;
}
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoMemRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
PCI_ROOT_BRIDGE *Private;
UINTN AlignMask;
PTR In;
PTR Out;
if ( Buffer == NULL ) {
return EFI_INVALID_PARAMETER;
}
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
if (!PciRootBridgeMemAddressValid (Private, Address)) {
return EFI_INVALID_PARAMETER;
}
AlignMask = (1 << (Width & 0x03)) - 1;
if (Address & AlignMask) {
return EFI_INVALID_PARAMETER;
}
In.buf = Buffer;
Out.buf = (VOID *)(UINTN) Address;
switch (Width) {
case EfiPciWidthUint8:
case EfiPciWidthUint16:
case EfiPciWidthUint32:
case EfiPciWidthUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
case EfiPciWidthFifoUint8:
case EfiPciWidthFifoUint16:
case EfiPciWidthFifoUint32:
case EfiPciWidthFifoUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
case EfiPciWidthFillUint8:
case EfiPciWidthFillUint16:
case EfiPciWidthFillUint32:
case EfiPciWidthFillUint64:
return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
default:
break;
}
return EFI_INVALID_PARAMETER;
}
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoMemWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
PCI_ROOT_BRIDGE *Private;
UINTN AlignMask;
PTR In;
PTR Out;
if ( Buffer == NULL ) {
return EFI_INVALID_PARAMETER;
}
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
if (!PciRootBridgeMemAddressValid (Private, Address)) {
return EFI_INVALID_PARAMETER;
}
AlignMask = (1 << (Width & 0x03)) - 1;
if (Address & AlignMask) {
return EFI_INVALID_PARAMETER;
}
In.buf = (VOID *)(UINTN) Address;
Out.buf = Buffer;
switch (Width) {
case EfiPciWidthUint8:
case EfiPciWidthUint16:
case EfiPciWidthUint32:
case EfiPciWidthUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
case EfiPciWidthFifoUint8:
case EfiPciWidthFifoUint16:
case EfiPciWidthFifoUint32:
case EfiPciWidthFifoUint64:
return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
case EfiPciWidthFillUint8:
case EfiPciWidthFillUint16:
case EfiPciWidthFillUint32:
case EfiPciWidthFillUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
default:
break;
}
return EFI_INVALID_PARAMETER;
}
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoPciRead (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
}
return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
}
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
PciRootBridgeIoPciWrite (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
IN OUT VOID *Buffer
)
{
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
}
return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
}

67
BeagleBoardPkg/Sec/Arm/Macro.inc Executable file
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//%HEADER%
MACRO
MmioWrite32Macro $Address, $Data
ldr r1, = ($Address)
ldr r0, = ($Data)
str r0, [r1]
MEND
MACRO
MmioOr32Macro $Address, $OrData
ldr r1, =($Address)
ldr r2, =($OrData)
ldr r0, [r1]
orr r0, r0, r2
str r0, [r1]
MEND
MACRO
MmioAnd32Macro $Address, $AndData
ldr r1, =($Address)
ldr r2, =($AndData)
ldr r0, [r1]
and r0, r0, r2
str r0, [r1]
MEND
MACRO
MmioAndThenOr32Macro $Address, $AndData, $OrData
ldr r1, =($Address)
ldr r0, [r1]
ldr r2, =($AndData)
and r0, r0, r2
ldr r2, =($OrData)
orr r0, r0, r2
str r0, [r1]
MEND
MACRO
MmioWriteFromReg32Macro $Address, $Reg
ldr r1, =($Address)
str $Reg, [r1]
MEND
MACRO
MmioRead32Macro $Address
ldr r1, =($Address)
ldr r0, [r1]
MEND
MACRO
MmioReadToReg32Macro $Address, $Reg
ldr r1, =($Address)
ldr $Reg, [r1]
MEND
MACRO
LoadConstantMacro $Data
ldr r0, =($Data)
MEND
MACRO
LoadConstantToRegMacro $Data, $Reg
ldr $Reg, =($Data)
MEND
END

93
BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S Executable file
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#------------------------------------------------------------------------------
#
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
#include <Library/PcdLib.h>
.text
.align 3
.globl ASM_PFX(CEntryPoint)
.globl ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
//Disable L2 cache
mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
bic r0, r0, #0x00000002 // disable L2 cache
mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
//Enable Strict alignment checking & Instruction cache
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
mcr p15, 0, r0, c1, c0, 0
// Set CPU vectors to start of DRAM
mov r0, #0x80000000
mcr p15, 0, r0, c12, c0, 0
/* before we call C code, lets setup the stack pointer */
stack_pointer_setup:
//
// Set stack based on PCD values. Need to do it this way to make C code work
// when it runs from FLASH.
//
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */
add r4, r2, r3
//Enter IRQ mode and set up IRQ stack pointer
mov r0,#0x12|0x80|0x40
msr CPSR_c,r0
mov r13,r4
//Enter Abort mode and set up Abort stack pointer
mov r0,#0x17|0x80|0x40
msr CPSR_c,r0
sub r4, r4, #0x400
mov r13,r4
//Enter Undefined mode and set up Undefined stack pointer
mov r0,#0x1b|0x80|0x40
msr CPSR_c,r0
sub r4, r4, #0x400
mov r13,r4
//Enter SVC mode and set up SVC stack pointer
mov r0,#0x13|0x80|0x40
msr CPSR_c,r0
sub r4, r4, #0x400
mov r13,r4
//Enter System mode and set up System stack pointer
mov r0,#0x1f|0x80|0x40
msr CPSR_c,r0
sub r4, r4, #0x400
mov r13,r4
// Call C entry point
mov r0, #0x80000000 /* memory base arg0 */
mov r1, #0x10000000 /* memory size arg1 */
bl ASM_PFX(CEntryPoint) /* Assume C code is ARM */
ShouldNeverGetHere:
/* _CEntryPoint should never return */
b ShouldNeverGetHere

95
BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm Executable file
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//------------------------------------------------------------------------------
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
#include <Library/PcdLib.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
IMPORT CEntryPoint
EXPORT _ModuleEntryPoint
PRESERVE8
AREA ModuleEntryPoint, CODE, READONLY
_ModuleEntryPoint
//Disable L2 cache
mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
bic r0, r0, #0x00000002 // disable L2 cache
mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
//Enable Strict alignment checking & Instruction cache
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
mcr p15, 0, r0, c1, c0, 0
// Set CPU vectors to start of DRAM
mov r0, #0x80000000
mcr p15, 0, r0, c12, c0, 0
/* before we call C code, lets setup the stack pointer in internal RAM*/
stack_pointer_setup
//
// Set stack based on PCD values. Need to do it this way to make C code work
// when it runs from FLASH.
//
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */
add r4, r2, r3
//Enter IRQ mode and set up IRQ stack pointer
mov r0,#0x12|0x80|0x40
msr CPSR_c,r0
mov r13,r4
//Enter Abort mode and set up Abort stack pointer
mov r0,#0x17|0x80|0x40
msr CPSR_c,r0
sub r4, r4, #0x400
mov r13,r4
//Enter Undefined mode and set up Undefined stack pointer
mov r0,#0x1b|0x80|0x40
msr CPSR_c,r0
sub r4, r4, #0x400
mov r13,r4
//Enter SVC mode and set up SVC stack pointer
mov r0,#0x13|0x80|0x40
msr CPSR_c,r0
sub r4, r4, #0x400
mov r13,r4
//Enter System mode and set up System stack pointer
mov r0,#0x1f|0x80|0x40
msr CPSR_c,r0
sub r4, r4, #0x400
mov r13,r4
// Call C entry point
mov r0, #0x80000000 /* memory base arg0 */
mov r1, #0x08000000 /* memory size arg1 */
blx CEntryPoint /* Assume C code is thumb */
ShouldNeverGetHere
/* _CEntryPoint should never return */
b ShouldNeverGetHere
END

88
BeagleBoardPkg/Sec/Cache.c Executable file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiPei.h>
#include <Library/ArmLib.h>
#include <Library/PrePiLib.h>
#include <Library/PcdLib.h>
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
// SoC registers. L3 interconnects
#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000
#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000
#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
// SoC registers. L4 interconnects
#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000
#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000
#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
VOID
InitCache (
IN UINT32 MemoryBase,
IN UINT32 MemoryLength
)
{
UINTN UncachedMemoryMask;
UINT32 CacheAttributes;
ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[5];
VOID *TranslationTableBase;
UINTN TranslationTableSize;
UncachedMemoryMask = PcdGet64(PcdArmUncachedMemoryMask);
if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
CacheAttributes = DDR_ATTRIBUTES_CACHED;
} else {
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
}
// DDR
MemoryTable[0].PhysicalBase = MemoryBase;
MemoryTable[0].VirtualBase = MemoryBase;
MemoryTable[0].Length = MemoryLength;
MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
// Uncached DDR Mirror
MemoryTable[1].PhysicalBase = MemoryBase;
MemoryTable[1].VirtualBase = MemoryBase | UncachedMemoryMask;
MemoryTable[1].Length = MemoryLength;
MemoryTable[1].Attributes = DDR_ATTRIBUTES_UNCACHED;
// SOC Registers. L3 interconnects
MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
MemoryTable[2].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
MemoryTable[2].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
MemoryTable[2].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;
// SOC Registers. L4 interconnects
MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
MemoryTable[3].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
MemoryTable[3].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
MemoryTable[3].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;
// End of Table
MemoryTable[4].PhysicalBase = 0;
MemoryTable[4].VirtualBase = 0;
MemoryTable[4].Length = 0;
MemoryTable[4].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
ArmConfigureMmu(MemoryTable, &TranslationTableBase, &TranslationTableSize);
BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
}

70
BeagleBoardPkg/Sec/Clock.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Omap3530/Omap3530.h>
VOID
ClockInit (
VOID
)
{
//DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.
// Enable PLL5 and set to 120 MHz as a reference clock.
MmioWrite32(CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
MmioWrite32(CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
MmioWrite32(CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
// Turn on functional & interface clocks to the USBHOST power domain
MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
| CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);
MmioOr32(CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);
// Turn on functional & interface clocks to the USBTLL block.
MmioOr32(CM_FCLKEN3_CORE, CM_FCLKEN3_CORE_EN_USBTLL_ENABLE);
MmioOr32(CM_ICLKEN3_CORE, CM_ICLKEN3_CORE_EN_USBTLL_ENABLE);
// Turn on functional & interface clocks to MMC1 and I2C1 modules.
MmioOr32(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_MMC1_ENABLE
| CM_FCLKEN1_CORE_EN_I2C1_ENABLE);
MmioOr32(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_MMC1_ENABLE
| CM_ICLKEN1_CORE_EN_I2C1_ENABLE);
// Turn on functional & interface clocks to various Peripherals.
MmioOr32(CM_FCLKEN_PER, CM_FCLKEN_PER_EN_UART3_ENABLE
| CM_FCLKEN_PER_EN_GPT3_ENABLE
| CM_FCLKEN_PER_EN_GPT4_ENABLE
| CM_FCLKEN_PER_EN_GPIO2_ENABLE
| CM_FCLKEN_PER_EN_GPIO3_ENABLE
| CM_FCLKEN_PER_EN_GPIO4_ENABLE
| CM_FCLKEN_PER_EN_GPIO5_ENABLE
| CM_FCLKEN_PER_EN_GPIO6_ENABLE);
MmioOr32(CM_ICLKEN_PER, CM_ICLKEN_PER_EN_UART3_ENABLE
| CM_ICLKEN_PER_EN_GPT3_ENABLE
| CM_ICLKEN_PER_EN_GPT4_ENABLE
| CM_ICLKEN_PER_EN_GPIO2_ENABLE
| CM_ICLKEN_PER_EN_GPIO3_ENABLE
| CM_ICLKEN_PER_EN_GPIO4_ENABLE
| CM_ICLKEN_PER_EN_GPIO5_ENABLE
| CM_ICLKEN_PER_EN_GPIO6_ENABLE);
// Turn on functional & inteface clocks to various wakeup modules.
MmioOr32(CM_FCLKEN_WKUP, CM_FCLKEN_WKUP_EN_GPIO1_ENABLE
| CM_FCLKEN_WKUP_EN_WDT2_ENABLE);
MmioOr32(CM_ICLKEN_WKUP, CM_ICLKEN_WKUP_EN_GPIO1_ENABLE
| CM_ICLKEN_WKUP_EN_WDT2_ENABLE);
}

282
BeagleBoardPkg/Sec/PadConfiguration.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiPei.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Omap3530/Omap3530.h>
#define NUM_PINS 238
PAD_CONFIGURATION PadConfigurationTable[NUM_PINS] = {
//Pin, MuxMode, PullConfig, InputEnable
{ SDRC_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D12, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D13, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D14, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D15, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D16, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D17, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D18, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D19, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D20, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D21, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D22, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D23, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D24, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D25, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D26, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D27, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D28, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D29, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D30, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_D31, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_CLK, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_DQS0, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_CKE0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ SDRC_CKE1, MUXMODE7, PULLTYPENOSELECT, INPUT },
{ SDRC_DQS1, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_DQS2, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ SDRC_DQS3, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_A1, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A2, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A3, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A4, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A6, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A7, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A8, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A9, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_A10, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D12, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D13, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D14, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_D15, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_NCS0, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_NCS1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ GPMC_NCS2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ GPMC_NCS3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ GPMC_NCS4, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ GPMC_NCS5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_NCS6, MUXMODE1, PULLTYPENOSELECT, INPUT },
{ GPMC_NCS7, MUXMODE1, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ GPMC_CLK, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_NADV_ALE, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_NOE, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_NWE, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_NBE0_CLE, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ GPMC_NBE1, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_NWP, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ GPMC_WAIT0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ GPMC_WAIT1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ GPMC_WAIT2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ GPMC_WAIT3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ DSS_PCLK, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_HSYNC, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_PSYNC, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_ACBIAS, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA0, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA1, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA2, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA3, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA4, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA6, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA7, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA8, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA9, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA10, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA11, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA12, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA13, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA14, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA15, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA16, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA17, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA18, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA19, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA20, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA21, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA22, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ DSS_DATA23, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ CAM_HS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ CAM_VS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ CAM_XCLKA, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ CAM_PCLK, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ CAM_FLD, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ CAM_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CAM_XCLKB, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ CAM_WEN, MUXMODE4, PULLTYPENOSELECT, INPUT },
{ CAM_STROBE, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ CSI2_DX0, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CSI2_DY0, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CSI2_DX1, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ CSI2_DY1, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ MCBSP2_FSX, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ MCBSP2_CLKX, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ MCBSP2_DR, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ MCBSP2_DX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ MMC1_CLK, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ MMC1_CMD, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC1_DAT0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC1_DAT1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC1_DAT2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC1_DAT3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC1_DAT4, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC1_DAT5, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC1_DAT6, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC1_DAT7, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_CLK, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_CMD, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_DAT0, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_DAT1, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_DAT2, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_DAT3, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_DAT4, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_DAT5, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_DAT6, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MMC2_DAT7, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MCBSP3_DX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ MCBSP3_DR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ MCBSP3_CLKX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ MCBSP3_FSX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ UART2_CTS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ UART2_RTS, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ UART2_TX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ UART2_RX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ UART1_TX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ UART1_RTS, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ UART1_CTS, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ UART1_RX, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ MCBSP4_CLKX, MUXMODE1, PULLTYPENOSELECT, INPUT },
{ MCBSP4_DR, MUXMODE1, PULLTYPENOSELECT, INPUT },
{ MCBSP4_DX, MUXMODE1, PULLTYPENOSELECT, INPUT },
{ MCBSP4_FSX, MUXMODE1, PULLTYPENOSELECT, INPUT },
{ MCBSP1_CLKR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ MCBSP1_FSR, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ MCBSP1_DX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ MCBSP1_DR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ MCBSP1_CLKS, MUXMODE0, PULLTYPESELECT, INPUT },
{ MCBSP1_FSX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ MCBSP1_CLKX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ UART3_CTS_RCTX,MUXMODE0, PULLUDENABLE, INPUT },
{ UART3_RTS_SD, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ UART3_RX_IRRX, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ UART3_TX_IRTX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
{ HSUSB0_CLK, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_STP, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ HSUSB0_DIR, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_NXT, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_DATA0, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_DATA1, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_DATA2, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_DATA3, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_DATA4, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_DATA5, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_DATA6, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ HSUSB0_DATA7, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ I2C1_SCL, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ I2C1_SDA, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ I2C2_SCL, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ I2C2_SDA, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ I2C3_SCL, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ I2C3_SDA, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ HDQ_SIO, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ MCSPI1_CLK, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MCSPI1_SIMO, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ MCSPI1_SOMI, MUXMODE0, PULLTYPENOSELECT, INPUT },
{ MCSPI1_CS0, MUXMODE0, PULLUDENABLE, INPUT },
{ MCSPI1_CS1, MUXMODE0, PULLUDENABLE, OUTPUT },
{ MCSPI1_CS2, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
{ MCSPI1_CS3, MUXMODE3, PULLTYPESELECT, INPUT },
{ MCSPI2_CLK, MUXMODE3, PULLTYPESELECT, INPUT },
{ MCSPI2_SIMO, MUXMODE3, PULLTYPESELECT, INPUT },
{ MCSPI2_SOMI, MUXMODE3, PULLTYPESELECT, INPUT },
{ MCSPI2_CS0, MUXMODE3, PULLTYPESELECT, INPUT },
{ MCSPI2_CS1, MUXMODE3, PULLTYPESELECT, INPUT },
{ SYS_NIRQ, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ SYS_CLKOUT2, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
{ ETK_CLK, MUXMODE3, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
{ ETK_CTL, MUXMODE3, PULLTYPESELECT, OUTPUT },
{ ETK_D0, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D1, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D2, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D3, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D4, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D5, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D6, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D7, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D8, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D9, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D10, MUXMODE3, PULLTYPESELECT, OUTPUT },
{ ETK_D11, MUXMODE3, PULLTYPESELECT, OUTPUT },
{ ETK_D12, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D13, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D14, MUXMODE3, PULLTYPESELECT, INPUT },
{ ETK_D15, MUXMODE3, PULLTYPESELECT, INPUT }
};
VOID
PadConfiguration (
VOID
)
{
UINTN Index;
UINT16 PadConfiguration;
UINTN NumPinsToConfigure = sizeof(PadConfigurationTable)/sizeof(PAD_CONFIGURATION);
for (Index = 0; Index < NumPinsToConfigure; Index++) {
//Set up Pad configuration for particular pin.
PadConfiguration = (PadConfigurationTable[Index].MuxMode << MUXMODE_OFFSET);
PadConfiguration |= (PadConfigurationTable[Index].PullConfig << PULL_CONFIG_OFFSET);
PadConfiguration |= (PadConfigurationTable[Index].InputEnable << INPUTENABLE_OFFSET);
//Configure the pin with specific Pad configuration.
MmioWrite16(PadConfigurationTable[Index].Pin, PadConfiguration);
}
}

165
BeagleBoardPkg/Sec/Sec.c Executable file
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/** @file
C Entry point for the SEC. First C code after the reset vector.
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/PrePiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Library/ArmLib.h>
#include <Ppi/GuidedSectionExtraction.h>
#include <Omap3530/Omap3530.h>
VOID
PadConfiguration (
VOID
);
VOID
ClockInit (
VOID
);
VOID
TimerInit (
VOID
)
{
UINTN Timer = FixedPcdGet32(PcdBeagleFreeTimer);
UINT32 TimerBaseAddress = TimerBase(Timer);
// Set source clock for GPT3 & GPT4 to SYS_CLK
MmioOr32(CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS
| CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
// Set count & reload registers
MmioWrite32(TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
MmioWrite32(TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
// Disable interrupts
MmioWrite32(TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
// Start Timer
MmioWrite32(TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
//Disable OMAP Watchdog timer (WDT2)
MmioWrite32(WDTIMER2_BASE + WSPR, 0xAAAA);
DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
MmioWrite32(WDTIMER2_BASE + WSPR, 0x5555);
}
VOID
UartInit (
VOID
)
{
UINTN Uart = FixedPcdGet32(PcdBeagleConsoleUart);
UINT32 UartBaseAddress = UartBase(Uart);
// Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.
MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);
// Put device in configuration mode.
MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);
// Programmable divisor N = 48Mhz/16/115200 = 26
MmioWrite32(UartBaseAddress + UART_DLL_REG, 26); // low divisor
MmioWrite32(UartBaseAddress + UART_DLH_REG, 0); // high divisor
// Enter into UART operational mode.
MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);
// Force DTR and RTS output to active
MmioWrite32(UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);
// Clear & enable fifos
MmioWrite32(UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE);
// Restore MODE_SELECT
MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);
}
VOID
InitCache (
IN UINT32 MemoryBase,
IN UINT32 MemoryLength
);
EFI_STATUS
EFIAPI
ExtractGuidedSectionLibConstructor (
VOID
);
EFI_STATUS
EFIAPI
LzmaDecompressLibConstructor (
VOID
);
VOID
CEntryPoint (
IN VOID *MemoryBase,
IN UINTN MemorySize,
IN VOID *StackBase,
IN UINTN StackSize
)
{
VOID *HobBase;
//Set up Pin muxing.
PadConfiguration();
// Set up system clocking
ClockInit();
// Build a basic HOB list
HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));
CreateHobList(MemoryBase, MemorySize, HobBase, StackBase);
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction();
// Initialize CPU cache
InitCache((UINT32)MemoryBase, (UINT32)MemorySize);
// Add memory allocation hob for relocated FD
BuildMemoryAllocationHob(FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);
// Add the FVs to the hob list
BuildFvHob(PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));
// Start talking
UartInit();
DEBUG((EFI_D_ERROR, "UART Test Line\n"));
// Start up a free running time so that the timer lib will work
TimerInit();
// SEC phase needs to run library constructors by hand.
ExtractGuidedSectionLibConstructor();
LzmaDecompressLibConstructor();
// Load the DXE Core and transfer control to it
LoadDxeCoreFromFv(NULL, 0);
// DXE Core should always load and never return
ASSERT(FALSE);
}

66
BeagleBoardPkg/Sec/Sec.inf Executable file
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#%HEADER%
#/** @file
# SEC - Reset vector code that jumps to C and loads DXE core
#
# Copyright (c) 2008, Apple Inc. <BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardSec
FILE_GUID = d959e387-7b91-452c-90e0-a1dbac90ddb8
MODULE_TYPE = SEC
VERSION_STRING = 1.0
[Sources.ARM]
Arm/ModuleEntryPoint.S | GCC
Arm/ModuleEntryPoint.asm | RVCT
[Sources.ARM]
Sec.c
Cache.c
PadConfiguration.c
Clock.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
BaseLib
DebugLib
ArmLib
IoLib
ExtractGuidedSectionLib
LzmaDecompressLib
OmapLib
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd]
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
gEmbeddedTokenSpaceGuid.PcdPrePiStackBase
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart
gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer
gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize

325
BeagleBoardPkg/SmbusDxe/Smbus.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Uefi.h>
#include <Omap3530/Omap3530.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/SmbusHc.h>
#define MAX_RETRY 1000
//
// Internal Functions
//
STATIC
EFI_STATUS
WaitForBusBusy (
VOID
)
{
UINTN Retry = 0;
while (++Retry < MAX_RETRY && (MmioRead16(I2C_STAT) & BB) == 0x1);
if (Retry == MAX_RETRY) {
return EFI_TIMEOUT;
}
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
PollForStatus(
UINT16 StatusBit
)
{
UINTN Retry = 0;
while(Retry < MAX_RETRY) {
if (MmioRead16(I2C_STAT) & StatusBit) {
//Clear particular status bit from Status register.
MmioOr16(I2C_STAT, StatusBit);
break;
}
Retry++;
}
if (Retry == MAX_RETRY) {
return EFI_TIMEOUT;
}
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
ConfigureI2c (
VOID
)
{
//Program prescaler to obtain 12-MHz clock
MmioWrite16(I2C_PSC, 0x0000);
//Program SCLL and SCLH
//NOTE: Following values are the register dump after U-Boot code executed.
//We need to figure out how its calculated based on the I2C functional clock and I2C_PSC.
MmioWrite16(I2C_SCLL, 0x0035);
MmioWrite16(I2C_SCLH, 0x0035);
//Take the I2C controller out of reset.
MmioOr16(I2C_CON, I2C_EN);
//Initialize the I2C controller.
//Set I2C controller in Master mode.
MmioOr16(I2C_CON, MST);
//Enable interrupts for receive/transmit mode.
MmioOr16(I2C_IE, (XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE));
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
I2CReadOneByte (
UINT8 *Data
)
{
EFI_STATUS Status;
//I2C bus status checking
Status = WaitForBusBusy();
if (EFI_ERROR(Status)) {
return Status;
}
//Poll till Receive ready bit is set.
Status = PollForStatus(RRDY);
if (EFI_ERROR(Status)) {
return Status;
}
*Data = MmioRead8(I2C_DATA);
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
I2CWriteOneByte (
UINT8 Data
)
{
EFI_STATUS Status;
//I2C bus status checking
Status = WaitForBusBusy();
if (EFI_ERROR(Status)) {
return Status;
}
//Data transfer
//Poll till Transmit ready bit is set
Status = PollForStatus(XRDY);
if (EFI_ERROR(Status)) {
return Status;
}
MmioWrite8(I2C_DATA, Data);
//Wait and check if the NACK is not set.
gBS->Stall(1000);
if (MmioRead16(I2C_STAT) & NACK) {
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
SmbusBlockRead (
OUT UINT8 *Buffer,
IN UINTN Length
)
{
UINTN Index = 0;
EFI_STATUS Status = EFI_SUCCESS;
//Transfer configuration for receiving data.
MmioWrite16(I2C_CNT, Length);
//Need stop bit before sending data.
MmioWrite16(I2C_CON, (I2C_EN | MST | STP | STT));
while (Index < Length) {
//Read a byte
Status = I2CReadOneByte(&Buffer[Index++]);
if (EFI_ERROR(Status)) {
return Status;
}
}
//Transfer completion
Status = PollForStatus(ARDY);
if (EFI_ERROR(Status)) {
return Status;
}
return Status;
}
STATIC
EFI_STATUS
SmbusBlockWrite (
IN UINT8 *Buffer,
IN UINTN Length
)
{
UINTN Index = 0;
EFI_STATUS Status = EFI_SUCCESS;
//Transfer configuration for transmitting data
MmioWrite16(I2C_CNT, Length);
MmioWrite16(I2C_CON, (I2C_EN | TRX | MST | STT | STP));
while (Index < Length) {
//Send a byte
Status = I2CWriteOneByte(Buffer[Index++]);
if (EFI_ERROR(Status)) {
return Status;
}
}
//Transfer completion
Status = PollForStatus(ARDY);
if (EFI_ERROR(Status)) {
return Status;
}
return Status;
}
//
// Public Functions.
//
EFI_STATUS
EFIAPI
SmbusExecute (
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
IN CONST EFI_SMBUS_DEVICE_COMMAND Command,
IN CONST EFI_SMBUS_OPERATION Operation,
IN CONST BOOLEAN PecCheck,
IN OUT UINTN *Length,
IN OUT VOID *Buffer
)
{
UINT8 *ByteBuffer = Buffer;
EFI_STATUS Status = EFI_SUCCESS;
UINT8 SlaveAddr = (UINT8)(SlaveAddress.SmbusDeviceAddress);
if (PecCheck) {
return EFI_UNSUPPORTED;
}
if ((Operation != EfiSmbusWriteBlock) && (Operation != EfiSmbusReadBlock)) {
return EFI_UNSUPPORTED;
}
//Set the Slave address.
MmioWrite16(I2C_SA, SlaveAddr);
if (Operation == EfiSmbusReadBlock) {
Status = SmbusBlockRead(ByteBuffer, *Length);
} else if (Operation == EfiSmbusWriteBlock) {
Status = SmbusBlockWrite(ByteBuffer, *Length);
}
return Status;
}
EFI_STATUS
EFIAPI
SmbusArpDevice (
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
IN CONST BOOLEAN ArpAll,
IN CONST EFI_SMBUS_UDID *SmbusUdid OPTIONAL,
IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL
)
{
return EFI_UNSUPPORTED;
}
EFI_STATUS
EFIAPI
SmbusGetArpMap (
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
IN OUT UINTN *Length,
IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap
)
{
return EFI_UNSUPPORTED;
}
EFI_STATUS
EFIAPI
SmbusNotify (
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
IN CONST UINTN Data,
IN CONST EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction
)
{
return EFI_UNSUPPORTED;
}
EFI_SMBUS_HC_PROTOCOL SmbusProtocol =
{
SmbusExecute,
SmbusArpDevice,
SmbusGetArpMap,
SmbusNotify
};
EFI_STATUS
InitializeSmbus (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
//Configure I2C controller.
Status = ConfigureI2c();
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "InitializeI2c fails.\n"));
return Status;
}
// Install the SMBUS interface
Status = gBS->InstallMultipleProtocolInterfaces(&Handle, &gEfiSmbusHcProtocolGuid, &SmbusProtocol, NULL);
ASSERT_EFI_ERROR(Status);
return Status;
}

33
BeagleBoardPkg/SmbusDxe/Smbus.inf Normal file
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#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = Smbus
FILE_GUID = d5125e0f-1226-444f-a218-0085996ed5da
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InitializeSmbus
[Sources.common]
Smbus.c
[Packages]
MdePkg/MdePkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
IoLib
[Guids]
[Protocols]
gEfiSmbusHcProtocolGuid
[Pcd]
[depex]
TRUE

116
BeagleBoardPkg/TPS65950Dxe/TPS65950.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Uefi.h>
#include <TPS65950.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/SmbusHc.h>
EFI_SMBUS_HC_PROTOCOL *Smbus;
EFI_STATUS
Read (
IN EMBEDDED_EXTERNAL_DEVICE *This,
IN UINTN Register,
IN UINTN Length,
OUT VOID *Buffer
)
{
EFI_STATUS Status;
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
UINT8 DeviceRegister;
UINTN DeviceRegisterLength = 1;
SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register);
DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register);
//Write DeviceRegister.
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceRegisterLength, &DeviceRegister);
if (EFI_ERROR(Status)) {
return Status;
}
//Read Data
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusReadBlock, FALSE, &Length, Buffer);
return Status;
}
EFI_STATUS
Write (
IN EMBEDDED_EXTERNAL_DEVICE *This,
IN UINTN Register,
IN UINTN Length,
IN VOID *Buffer
)
{
EFI_STATUS Status;
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
UINT8 DeviceRegister;
UINTN DeviceBufferLength = Length + 1;
UINT8 *DeviceBuffer;
SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register);
DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register);
//Prepare buffer for writing
DeviceBuffer = (UINT8 *)AllocatePool(DeviceBufferLength);
if (DeviceBuffer == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto exit;
}
//Set Device register followed by data to write.
DeviceBuffer[0] = DeviceRegister;
CopyMem(&DeviceBuffer[1], Buffer, Length);
//Write Data
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceBufferLength, DeviceBuffer);
if (EFI_ERROR(Status)) {
goto exit;
}
exit:
if (DeviceBuffer) {
FreePool(DeviceBuffer);
}
return Status;
}
EMBEDDED_EXTERNAL_DEVICE ExternalDevice = {
Read,
Write
};
EFI_STATUS
TPS65950Initialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
Status = gBS->LocateProtocol(&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&Smbus);
ASSERT_EFI_ERROR(Status);
Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedExternalDeviceProtocolGuid, &ExternalDevice, NULL);
return Status;
}

36
BeagleBoardPkg/TPS65950Dxe/TPS65950.inf Normal file
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#%HEADER%
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = TPS65950
FILE_GUID = 71fe861a-5450-48b6-bfb0-b93522616f99
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = TPS65950Initialize
[Sources.common]
TPS65950.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
BeagleBoardPkg/BeagleBoardPkg.dec
[LibraryClasses]
BaseMemoryLib
PcdLib
UefiLib
UefiDriverEntryPoint
MemoryAllocationLib
[Guids]
[Protocols]
gEfiSmbusHcProtocolGuid
gEmbeddedExternalDeviceProtocolGuid
[Pcd]
[depex]
gEfiSmbusHcProtocolGuid

239
BeagleBoardPkg/TimerDxe/Timer.c Normal file
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/** @file
Template for Timer Architecture Protocol driver of the ARM flavor
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Protocol/Timer.h>
#include <Protocol/HardwareInterrupt.h>
#include <Protocol/TimerDebugSupport.h>
#include <Omap3530/Omap3530.h>
// The notification function to call on every timer interrupt.
volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
volatile EFI_PERIODIC_CALLBACK mTimerPeriodicCallback = (EFI_PERIODIC_CALLBACK)NULL;
// The current period of the timer interrupt
volatile UINT64 mTimerPeriod = 0;
// Cached copy of the Hardware Interrupt protocol instance
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
// Cached registers
volatile UINT32 TISR;
volatile UINT32 TCLR;
volatile UINT32 TLDR;
volatile UINT32 TCRR;
volatile UINT32 TIER;
// Cached interrupt vector
volatile UINTN gVector;
VOID
EFIAPI
TimerInterruptHandler (
IN HARDWARE_INTERRUPT_SOURCE Source,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
if (mTimerPeriodicCallback) {
mTimerPeriodicCallback(SystemContext);
}
if (mTimerNotifyFunction) {
mTimerNotifyFunction(mTimerPeriod);
}
// Clear all timer interrupts
MmioWrite32(TISR, TISR_CLEAR_ALL);
// Poll interrupt status bits to ensure clearing
while ((MmioRead32(TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
}
EFI_STATUS
EFIAPI
TimerDriverRegisterHandler (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN EFI_TIMER_NOTIFY NotifyFunction
)
{
if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
return EFI_ALREADY_STARTED;
}
mTimerNotifyFunction = NotifyFunction;
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
TimerDriverSetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN UINT64 TimerPeriod
)
{
EFI_STATUS Status;
UINT64 TimerCount;
INT32 LoadValue;
if (TimerPeriod == 0) {
// Turn off GPTIMER3
MmioWrite32(TCLR, TCLR_ST_OFF);
Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector);
} else {
// Calculate required timer count
TimerCount = DivU64x32(TimerPeriod * 100, PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds));
// Set GPTIMER3 Load register
LoadValue = (INT32) -TimerCount;
MmioWrite32(TLDR, LoadValue);
MmioWrite32(TCRR, LoadValue);
// Enable Overflow interrupt
MmioWrite32(TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
// Turn on GPTIMER3, it will reload at overflow
MmioWrite32(TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector);
}
//
// Save the new timer period
//
mTimerPeriod = TimerPeriod;
return Status;
}
EFI_STATUS
EFIAPI
TimerDriverGetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
return EFI_INVALID_PARAMETER;
}
*TimerPeriod = mTimerPeriod;
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
TimerDriverGenerateSoftInterrupt (
IN EFI_TIMER_ARCH_PROTOCOL *This
)
{
return EFI_UNSUPPORTED;
}
EFI_STATUS
EFIAPI
TimerDriverRegisterPeriodicCallback (
IN TIMER_DEBUG_SUPPORT_PROTOCOL *This,
IN EFI_PERIODIC_CALLBACK PeriodicCallback
)
{
if ((PeriodicCallback == NULL) && (mTimerPeriodicCallback == NULL)) {
return EFI_INVALID_PARAMETER;
}
if ((PeriodicCallback != NULL) && (mTimerPeriodicCallback != NULL)) {
return EFI_ALREADY_STARTED;
}
mTimerPeriodicCallback = PeriodicCallback;
return EFI_SUCCESS;
}
EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler,
TimerDriverSetTimerPeriod,
TimerDriverGetTimerPeriod,
TimerDriverGenerateSoftInterrupt
};
TIMER_DEBUG_SUPPORT_PROTOCOL gTimerDebugSupport = {
TimerDriverRegisterPeriodicCallback
};
EFI_STATUS
EFIAPI
TimerInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
UINT32 TimerBaseAddress;
// Find the interrupt controller protocol. ASSERT if not found.
Status = gBS->LocateProtocol(&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
ASSERT_EFI_ERROR (Status);
// Set up the timer registers
TimerBaseAddress = TimerBase(FixedPcdGet32(PcdBeagleArchTimer));
TISR = TimerBaseAddress + GPTIMER_TISR;
TCLR = TimerBaseAddress + GPTIMER_TCLR;
TLDR = TimerBaseAddress + GPTIMER_TLDR;
TCRR = TimerBaseAddress + GPTIMER_TCRR;
TIER = TimerBaseAddress + GPTIMER_TIER;
// Disable the timer
Status = TimerDriverSetTimerPeriod(&gTimer, 0);
ASSERT_EFI_ERROR (Status);
// Install interrupt handler
gVector = InterruptVectorForTimer(FixedPcdGet32(PcdBeagleArchTimer));
Status = gInterrupt->RegisterInterruptSource(gInterrupt, gVector, TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
// Set up default timer
Status = TimerDriverSetTimerPeriod(&gTimer, FixedPcdGet32(PcdTimerPeriod));
ASSERT_EFI_ERROR (Status);
// Install the Timer Architectural Protocol onto a new handle
Status = gBS->InstallMultipleProtocolInterfaces(&Handle,
&gEfiTimerArchProtocolGuid, &gTimer,
&gTimerDebugSupportProtocolGuid, &gTimerDebugSupport,
NULL);
ASSERT_EFI_ERROR(Status);
return Status;
}

60
BeagleBoardPkg/TimerDxe/TimerDxe.inf Normal file
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#%HEADER%
#/** @file
#
# Component discription file for Timer module
#
# Copyright (c) 2009, Apple Inc. <BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BeagleBoardTimerDxe
FILE_GUID = 6ddbf08b-cfc9-43cc-9e81-0784ba312ca0
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = TimerInitialize
[Sources.common]
Timer.c
[Packages]
BeagleBoardPkg/BeagleBoardPkg.dec
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
UefiRuntimeServicesTableLib
PerformanceLib
UefiLib
UefiBootServicesTableLib
BaseMemoryLib
DebugLib
UefiDriverEntryPoint
IoLib
OmapLib
[Guids]
[Protocols]
gEfiTimerArchProtocolGuid
gHardwareInterruptProtocolGuid
gTimerDebugSupportProtocolGuid
[Pcd.common]
gEmbeddedTokenSpaceGuid.PcdTimerPeriod
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds
gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer
[Depex]
gHardwareInterruptProtocolGuid

20
BeagleBoardPkg/Tools/GNUmakefile Normal file
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#
# Copyright (c) 2008-2009, Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
CC = gcc
CFLAGS = -g
generate_image: generate_image.c
$(CC) $(CCFLAGS) $(LDFLAGS) -o generate_image generate_image.c
clean:
rm -f generate_image generate_image.exe

410
BeagleBoardPkg/Tools/generate_image.c Normal file
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/** @file
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
//TOC structure as defined by OMAP35XX TRM.
typedef struct {
unsigned int Start;
unsigned int Size;
unsigned int Reserved1;
unsigned int Reserved2;
unsigned int Reserved3;
unsigned char Filename[12];
} TOC_DATA;
//NOTE: OMAP3430 TRM has CHSETTINGS and CHRAM structures.
typedef struct {
unsigned int SectionKey;
unsigned char Valid;
unsigned char Version;
unsigned short Reserved;
unsigned int Flags;
unsigned int PRM_CLKSRC_CTRL;
unsigned int PRM_CLKSEL;
unsigned int CM_CLKSEL1_EMU;
unsigned int CM_CLKSEL_CORE;
unsigned int CM_CLKSEL_WKUP;
unsigned int CM_CLKEN_PLL_DPLL3;
unsigned int CM_AUTOIDLE_PLL_DPLL3;
unsigned int CM_CLKSEL1_PLL;
unsigned int CM_CLKEN_PLL_DPLL4;
unsigned int CM_AUTOIDLE_PLL_DPLL4;
unsigned int CM_CLKSEL2_PLL;
unsigned int CM_CLKSEL3_PLL;
unsigned int CM_CLKEN_PLL_MPU;
unsigned int CM_AUTOIDLE_PLL_MPU;
unsigned int CM_CLKSEL1_PLL_MPU;
unsigned int CM_CLKSEL2_PLL_MPU;
unsigned int CM_CLKSTCTRL_MPU;
} CHSETTINGS_DATA;
typedef struct {
unsigned int SectionKey;
unsigned char Valid;
unsigned char Reserved1;
unsigned char Reserved2;
unsigned char Reserved3;
unsigned short SDRC_SYSCONFIG_LSB;
unsigned short SDRC_CS_CFG_LSB;
unsigned short SDRC_SHARING_LSB;
unsigned short SDRC_ERR_TYPE_LSB;
unsigned int SDRC_DLLA_CTRL;
unsigned short Reserved4;
unsigned short Reserved5;
unsigned int SDRC_POWER;
unsigned short MEMORY_TYPE_CS0;
unsigned short Reserved6;
unsigned int SDRC_MCFG_0;
unsigned short SDRC_MR_0_LSB;
unsigned short SDRC_EMR1_0_LSB;
unsigned short SDRC_EMR2_0_LSB;
unsigned short SDRC_EMR3_0_LSB;
unsigned int SDRC_ACTIM_CTRLA_0;
unsigned int SDRC_ACTIM_CTRLB_0;
unsigned int SDRC_RFRCTRL_0;
unsigned short MEMORY_TYPE_CS1;
unsigned short Reserved7;
unsigned int SDRC_MCFG_1;
unsigned short SDRC_MR_1_LSB;
unsigned short SDRC_EMR1_1_LSB;
unsigned short SDRC_EMR2_1_LSB;
unsigned short SDRC_EMR3_1_LSB;
unsigned int SDRC_ACTIM_CTRLA_1;
unsigned int SDRC_ACTIM_CTRLB_1;
unsigned int SDRC_RFRCTRL_1;
unsigned int Reserved8;
unsigned short Flags;
unsigned short Reserved9;
} CHRAM_DATA;
#define CHSETTINGS_START 0xA0
#define CHSETTINGS_SIZE 0x50
#define CHRAM_START 0xF0
#define CHRAM_SIZE 0x5C
#define CLOSING_TOC_ITEM_SIZE 4
unsigned char gConfigurationHeader[512];
unsigned int gImageExecutionAddress;
char *gInputImageFile = NULL;
char *gOutputImageFile = NULL;
char *gDataFile = NULL;
static
void
PrintUsage (
void
)
{
printf("Usage..\n");
}
static
void
PopulateCHSETTINGSData (
FILE *DataFile,
CHSETTINGS_DATA *CHSETTINGSData
)
{
unsigned int Value;
CHSETTINGSData->SectionKey = 0xC0C0C0C1;
CHSETTINGSData->Valid = 0x1;
CHSETTINGSData->Version = 0x1;
CHSETTINGSData->Reserved = 0x00;
CHSETTINGSData->Flags = 0x050001FD;
//General clock settings.
fscanf(DataFile, "PRM_CLKSRC_CTRL=0x%08x\n", &Value);
CHSETTINGSData->PRM_CLKSRC_CTRL = Value;
fscanf(DataFile, "PRM_CLKSEL=0x%08x\n", &Value);
CHSETTINGSData->PRM_CLKSEL = Value;
fscanf(DataFile, "CM_CLKSEL1_EMU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL1_EMU = Value;
//Clock configuration
fscanf(DataFile, "CM_CLKSEL_CORE=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL_CORE = Value;
fscanf(DataFile, "CM_CLKSEL_WKUP=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL_WKUP = Value;
//DPLL3 (Core) settings
fscanf(DataFile, "CM_CLKEN_PLL_DPLL3=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKEN_PLL_DPLL3 = Value;
fscanf(DataFile, "CM_AUTOIDLE_PLL_DPLL3=0x%08x\n", &Value);
CHSETTINGSData->CM_AUTOIDLE_PLL_DPLL3 = Value;
fscanf(DataFile, "CM_CLKSEL1_PLL=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL1_PLL = Value;
//DPLL4 (Peripheral) settings
fscanf(DataFile, "CM_CLKEN_PLL_DPLL4=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKEN_PLL_DPLL4 = Value;
fscanf(DataFile, "CM_AUTOIDLE_PLL_DPLL4=0x%08x\n", &Value);
CHSETTINGSData->CM_AUTOIDLE_PLL_DPLL4 = Value;
fscanf(DataFile, "CM_CLKSEL2_PLL=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL2_PLL = Value;
fscanf(DataFile, "CM_CLKSEL3_PLL=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL3_PLL = Value;
//DPLL1 (MPU) settings
fscanf(DataFile, "CM_CLKEN_PLL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKEN_PLL_MPU = Value;
fscanf(DataFile, "CM_AUTOIDLE_PLL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_AUTOIDLE_PLL_MPU = Value;
fscanf(DataFile, "CM_CLKSEL1_PLL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL1_PLL_MPU = Value;
fscanf(DataFile, "CM_CLKSEL2_PLL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSEL2_PLL_MPU = Value;
fscanf(DataFile, "CM_CLKSTCTRL_MPU=0x%08x\n", &Value);
CHSETTINGSData->CM_CLKSTCTRL_MPU = Value;
}
static
void
PopulateCHRAMData (
FILE *DataFile,
CHRAM_DATA *CHRAMData
)
{
unsigned int Value;
CHRAMData->SectionKey = 0xC0C0C0C2;
CHRAMData->Valid = 0x1;
fscanf(DataFile, "SDRC_SYSCONFIG_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_SYSCONFIG_LSB = Value;
fscanf(DataFile, "SDRC_CS_CFG_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_CS_CFG_LSB = Value;
fscanf(DataFile, "SDRC_SHARING_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_SHARING_LSB = Value;
fscanf(DataFile, "SDRC_ERR_TYPE_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_ERR_TYPE_LSB = Value;
fscanf(DataFile, "SDRC_DLLA_CTRL=0x%08x\n", &Value);
CHRAMData->SDRC_DLLA_CTRL = Value;
fscanf(DataFile, "SDRC_POWER=0x%08x\n", &Value);
CHRAMData->SDRC_POWER = Value;
fscanf(DataFile, "MEMORY_TYPE_CS0=0x%04x\n", &Value);
CHRAMData->MEMORY_TYPE_CS0 = Value;
fscanf(DataFile, "SDRC_MCFG_0=0x%08x\n", &Value);
CHRAMData->SDRC_MCFG_0 = Value;
fscanf(DataFile, "SDRC_MR_0_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_MR_0_LSB = Value;
fscanf(DataFile, "SDRC_EMR1_0_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR1_0_LSB = Value;
fscanf(DataFile, "SDRC_EMR2_0_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR2_0_LSB = Value;
fscanf(DataFile, "SDRC_EMR3_0_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR3_0_LSB = Value;
fscanf(DataFile, "SDRC_ACTIM_CTRLA_0=0x%08x\n", &Value);
CHRAMData->SDRC_ACTIM_CTRLA_0 = Value;
fscanf(DataFile, "SDRC_ACTIM_CTRLB_0=0x%08x\n", &Value);
CHRAMData->SDRC_ACTIM_CTRLB_0 = Value;
fscanf(DataFile, "SDRC_RFRCTRL_0=0x%08x\n", &Value);
CHRAMData->SDRC_RFRCTRL_0 = Value;
fscanf(DataFile, "MEMORY_TYPE_CS1=0x%04x\n", &Value);
CHRAMData->MEMORY_TYPE_CS1 = Value;
fscanf(DataFile, "SDRC_MCFG_1=0x%08x\n", &Value);
CHRAMData->SDRC_MCFG_1 = Value;
fscanf(DataFile, "SDRC_MR_1_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_MR_1_LSB = Value;
fscanf(DataFile, "SDRC_EMR1_1_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR1_1_LSB = Value;
fscanf(DataFile, "SDRC_EMR2_1_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR2_1_LSB = Value;
fscanf(DataFile, "SDRC_EMR3_1_LSB=0x%04x\n", &Value);
CHRAMData->SDRC_EMR3_1_LSB = Value;
fscanf(DataFile, "SDRC_ACTIM_CTRLA_1=0x%08x\n", &Value);
CHRAMData->SDRC_ACTIM_CTRLA_1 = Value;
fscanf(DataFile, "SDRC_ACTIM_CTRLB_1=0x%08x\n", &Value);
CHRAMData->SDRC_ACTIM_CTRLB_1 = Value;
fscanf(DataFile, "SDRC_RFRCTRL_1=0x%08x\n", &Value);
CHRAMData->SDRC_RFRCTRL_1 = Value;
CHRAMData->Flags = 0x0003;
}
static
void
PrepareConfigurationHeader (
void
)
{
TOC_DATA Toc;
CHSETTINGS_DATA CHSETTINGSData;
CHRAM_DATA CHRAMData;
unsigned int ConfigurationHdrOffset = 0;
FILE *DataFile;
// Open data file
DataFile = fopen(gDataFile, "rb");
if (DataFile == NULL) {
fprintf(stderr, "Can't open data file %s.\n", gOutputImageFile);
exit(1);
}
//Initialize configuration header.
memset(gConfigurationHeader, 0x00, sizeof(gConfigurationHeader));
//CHSETTINGS TOC
memset(&Toc, 0x00, sizeof(TOC_DATA));
Toc.Start = CHSETTINGS_START;
Toc.Size = CHSETTINGS_SIZE;
strcpy((char *)Toc.Filename, (const char *)"CHSETTINGS");
memcpy(gConfigurationHeader + ConfigurationHdrOffset, &Toc, sizeof(TOC_DATA));
//Populate CHSETTINGS Data
memset(&CHSETTINGSData, 0x00, sizeof(CHSETTINGS_DATA));
PopulateCHSETTINGSData(DataFile, &CHSETTINGSData);
memcpy(gConfigurationHeader + Toc.Start, &CHSETTINGSData, Toc.Size);
//Adjust ConfigurationHdrOffset to point to next TOC
ConfigurationHdrOffset += sizeof(TOC_DATA);
//CHRAM TOC
memset(&Toc, 0x00, sizeof(TOC_DATA));
Toc.Start = CHRAM_START;
Toc.Size = CHRAM_SIZE;
strcpy((char *)Toc.Filename, (const char *)"CHRAM");
memcpy(gConfigurationHeader + ConfigurationHdrOffset, &Toc, sizeof(TOC_DATA));
//Populate CHRAM Data
memset(&CHRAMData, 0x00, sizeof(CHRAM_DATA));
PopulateCHRAMData(DataFile, &CHRAMData);
memcpy(gConfigurationHeader + Toc.Start, &CHRAMData, Toc.Size);
//Adjust ConfigurationHdrOffset to point to next TOC
ConfigurationHdrOffset += sizeof(TOC_DATA);
//Closing TOC item
memset(gConfigurationHeader + ConfigurationHdrOffset, 0xFF, CLOSING_TOC_ITEM_SIZE);
ConfigurationHdrOffset += CLOSING_TOC_ITEM_SIZE;
// Close data file
fclose(DataFile);
}
static
void
ConstructImage (
void
)
{
FILE *InputFile;
FILE *OutputFile;
unsigned int InputImageFileSize;
unsigned int NewImageFileSize;
struct stat FileStat;
char Ch;
unsigned int i;
InputFile = fopen(gInputImageFile, "rb");
if (InputFile == NULL) {
fprintf(stderr, "Can't open input file.\n");
exit(0);
}
//Get the size of the input image.
fstat(fileno(InputFile), &FileStat);
InputImageFileSize = FileStat.st_size;
//Calculate new file size
NewImageFileSize = InputImageFileSize - 520;
OutputFile = fopen(gOutputImageFile, "wb");
if (OutputFile == NULL) {
fprintf(stderr, "Can't open output file %s.\n", gOutputImageFile);
exit(0);
}
//Write Configuration header
fwrite(gConfigurationHeader, 1, sizeof(gConfigurationHeader), OutputFile);
//Write image header (Input image size, execution address)
fwrite(&NewImageFileSize, 1, 4, OutputFile);
fwrite(&gImageExecutionAddress, 1, 4, OutputFile);
//Skip first 0x207 bytes
fseek(InputFile, 520, SEEK_SET);
//Copy input image to the output file.
for (i = 0; i < NewImageFileSize; i++) {
fread(&Ch, 1, 1, InputFile);
fwrite(&Ch, 1, 1, OutputFile);
}
fclose(InputFile);
fclose(OutputFile);
}
int
main (
int argc,
char** argv
)
{
char Ch;
unsigned char *ptr;
if (argc == 1) {
PrintUsage ();
exit(1);
}
while ((Ch = getopt(argc, argv, "D:E:I:O:")) != -1) {
switch (Ch) {
case 'E': /* Image execution address */
gImageExecutionAddress = strtoul (optarg, (char **)&ptr, 16);
break;
case 'I': /* Input image file */
gInputImageFile = optarg;
break;
case 'O': /* Output image file */
gOutputImageFile = optarg;
break;
case 'D': /* Data file */
gDataFile = optarg;
break;
case '?':
if ((optopt == 'E') || (optopt == 'I') || (optopt == 'O')) {
fprintf (stderr, "Option -%c requires an argument.\n", optopt);
} else if (isprint (optopt)) {
fprintf (stderr, "Unknown option `-%c'.\n", optopt);
} else {
fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt);
}
return 1;
default:
abort ();
}
}
//Prepare configuration header
PrepareConfigurationHeader ();
//Build image with configuration header + image header + image
ConstructImage ();
return 0;
}

127
BeagleBoardPkg/build.sh Executable file
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#!/bin/bash
# Copyright (c) 2008 - 2009, Apple, Inc. All rights reserved.
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
set -e
shopt -s nocasematch
function process_debug_scripts {
if [[ -d $1 ]]; then
for filename in `ls $1`
do
sed -e "s@ZZZZZZ@$BUILD_ROOT@g" -e "s@WWWWWW@$WORKSPACE@g" \
"$1/$filename" \
> "$BUILD_ROOT/$filename"
#For ARMCYGWIN, we have to change /cygdrive/c to c:
if [[ $TARGET_TOOLS == RVCT31CYGWIN ]]
then
mv "$BUILD_ROOT/$filename" "$BUILD_ROOT/$filename"_temp
sed -e "s@/cygdrive/\(.\)@\1:@g" \
"$BUILD_ROOT/$filename"_temp \
> "$BUILD_ROOT/$filename"
rm -f "$BUILD_ROOT/$filename"_temp
fi
done
fi
}
#
# Setup workspace if it is not set
#
if [ -z "$WORKSPACE" ]
then
echo Initializing workspace
cd ..
export EDK_TOOLS_PATH=`pwd`/BaseTools
source edksetup.sh BaseTools
else
echo Building from: $WORKSPACE
fi
#
# Pick a default tool type for a given OS
#
case `uname` in
CYGWIN*)
TARGET_TOOLS=RVCT31CYGWIN
;;
Linux*)
# Not tested
TARGET_TOOLS=ELFGCC
;;
Darwin*)
Major=$(uname -r | cut -f 1 -d '.')
if [[ $Major == 9 ]]
then
# Not supported by this open source project
TARGET_TOOLS=XCODE31
else
TARGET_TOOLS=XCODE32
fi
;;
esac
BUILD_ROOT=$WORKSPACE/Build/BeagleBoard/DEBUG_"$TARGET_TOOLS"
GENERATE_IMAGE=$WORKSPACE/BeagleBoardPkg/Tools/generate_image
FLASH_BOOT=$BUILD_ROOT/FV/BeagleBoard_EFI_flashboot.fd
if [[ ! -f `which build` || ! -f `which GenFv` ]];
then
# build the tools if they don't yet exist
echo Building tools
make -C $WORKSPACE/BaseTools
else
echo using prebuilt tools
fi
#
# Build the edk2 BeagleBoard code
#
build -p $WORKSPACE/BeagleBoardPkg/BeagleBoardPkg.dsc -a ARM -t $TARGET_TOOLS $1 $2 $3 $4 $5 $6 $7 $8
for arg in "$@"
do
if [[ $arg == clean ]]; then
# no need to post process if we are doing a clean
exit
elif [[ $arg == cleanall ]]; then
make -C BaseTools/ clean
make -C $WORKSPACE/BeagleBoardPkg/Tools clean
exit
fi
done
#
# Build the tool used to patch the FLASH image to work with the Beagle board ROM
#
if [[ ! -e $GENERATE_IMAGE ]];
then
make -C $WORKSPACE/BeagleBoardPkg/Tools
fi
echo Patching FD to work with BeagleBoard ROM
rm -f $FLASH_BOOT
#
# Ram starts at 0x80000000
# OMAP 3530 TRM defines 0x80008208 as the entry point
# The reset vector is caught by the mask ROM in the OMAP 3530 so that is why this entry
# point looks so strange.
# OMAP 3430 TRM section 26.4.8 has Image header information. (missing in OMAP 3530 TRM)
#
$GENERATE_IMAGE -D $WORKSPACE/BeagleBoardPkg/ConfigurationHeader.dat -E 0x80008208 -I $BUILD_ROOT/FV/BEAGLEBOARD_EFI.fd -O $FLASH_BOOT
echo Creating debugger scripts
process_debug_scripts $WORKSPACE/BeagleBoardPkg/Debugger_scripts

11
BeagleBoardPkg/readme.txt Normal file
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Build:
======
Build requires a bash script.
./build.sh.
FAQ:
====
If you get a build error 000E: File/directory not found FatPkg/EnhancedFat/FatDxe/FatDxe.inf
cd $WORKSPACE
svn checkout https://fat-driver2.tianocore.org/svn/fat-driver2/trunk/FatPkg FatPkg --username username