ArmPkg: Fix Ecc error 8005/8007 in ArmDisassemblerLib
This patch fixes the following Ecc reported error: 8005: Variable name does not follow the rules: 1. First character should be upper case 2. Must contain lower case characters 3. No white space characters 4. Global variable name must start with a 'g' 8007: There should be no use of short (single character) variable names Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
This commit is contained in:
Pierre Gondois
committed by
mergify[bot]
mergify[bot]
parent
60e49aac4e
commit
2f2c0a8b9f
@ -9,6 +9,7 @@
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try to reuse existing case entries if possible.
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@ -451,7 +452,7 @@ SignExtend32 (
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// in the instruction address and you get back the aligned answer
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//
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UINT32
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PCAlign4 (
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PcAlign4 (
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IN UINT32 Data
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)
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{
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@ -486,12 +487,19 @@ DisassembleThumbInstruction (
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UINT32 Index;
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UINT32 Offset;
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UINT16 Rd, Rn, Rm, Rt, Rt2;
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BOOLEAN H1, H2, imod;
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BOOLEAN H1Bit; // H1
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BOOLEAN H2Bit; // H2
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BOOLEAN IMod; // imod
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//BOOLEAN ItFlag;
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UINT32 PC, Target, msbit, lsbit;
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UINT32 Pc, Target, MsBit, LsBit;
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CHAR8 *Cond;
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BOOLEAN S, J1, J2, P, U, W;
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UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
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BOOLEAN Sign; // S
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BOOLEAN J1Bit; // J1
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BOOLEAN J2Bit; // J2
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BOOLEAN Pre; // P
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BOOLEAN UAdd; // U
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BOOLEAN WriteBack; // W
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UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
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UINT32 Mask;
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OpCodePtr = *OpCodePtrPtr;
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@ -504,10 +512,10 @@ DisassembleThumbInstruction (
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Rd = OpCode & 0x7;
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Rn = (OpCode >> 3) & 0x7;
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Rm = (OpCode >> 6) & 0x7;
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H1 = (OpCode & BIT7) != 0;
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H2 = (OpCode & BIT6) != 0;
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imod = (OpCode & BIT4) != 0;
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PC = (UINT32)(UINTN)OpCodePtr;
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H1Bit = (OpCode & BIT7) != 0;
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H2Bit = (OpCode & BIT6) != 0;
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IMod = (OpCode & BIT4) != 0;
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Pc = (UINT32)(UINTN)OpCodePtr;
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// Increment by the minimum instruction size, Thumb2 could be bigger
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*OpCodePtrPtr += 1;
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@ -548,7 +556,7 @@ DisassembleThumbInstruction (
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case LOAD_STORE_FORMAT3:
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// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
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Target = (OpCode & 0xff) << 2;
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
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return;
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case LOAD_STORE_FORMAT4:
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// Rt, [SP, #imm8]
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@ -583,16 +591,16 @@ DisassembleThumbInstruction (
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Cond = gCondition[(OpCode >> 8) & 0xf];
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Buf[Offset-5] = *Cond++;
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Buf[Offset-4] = *Cond;
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
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return;
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case UNCONDITIONAL_BRANCH_SHORT:
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// A6.3.2 B <target_address>
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
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return;
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case BRANCH_EXCHANGE:
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// A6.3.3 BX|BLX <Rm>
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);
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return;
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case DATA_FORMAT1:
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@ -629,12 +637,12 @@ DisassembleThumbInstruction (
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return;
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case DATA_FORMAT8:
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// A6.4.3 <Rd>|<Rn>, <Rm>
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);
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return;
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case CPS_FORMAT:
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// A7.1.24
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AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
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AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
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return;
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case ENDIAN_FORMAT:
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@ -645,13 +653,13 @@ DisassembleThumbInstruction (
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case DATA_CBZ:
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// CB{N}Z <Rn>, <Lable>
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Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
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return;
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case ADR_FORMAT:
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// ADR <Rd>, <Label>
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Target = (OpCode & 0xff) << 2;
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
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return;
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case IT_BLOCK:
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@ -708,32 +716,32 @@ DisassembleThumbInstruction (
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Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
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Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
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Target = SignExtend32 (Target, BIT20);
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
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return;
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case B_T4:
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// S:I1:I2:imm10:imm11:0
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Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
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S = (OpCode32 & BIT26) == BIT26;
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J1 = (OpCode32 & BIT13) == BIT13;
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J2 = (OpCode32 & BIT11) == BIT11;
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Target |= (!(J2 ^ S) ? BIT22 : 0); // I2
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Target |= (!(J1 ^ S) ? BIT23 : 0); // I1
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Target |= (S ? BIT24 : 0); // S
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Sign = (OpCode32 & BIT26) == BIT26;
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J1Bit = (OpCode32 & BIT13) == BIT13;
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J2Bit = (OpCode32 & BIT11) == BIT11;
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Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
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Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
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Target |= (Sign ? BIT24 : 0); // S
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Target = SignExtend32 (Target, BIT24);
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
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return;
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case BL_T2:
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// BLX S:I1:I2:imm10:imm11:0
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Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
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S = (OpCode32 & BIT26) == BIT26;
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J1 = (OpCode32 & BIT13) == BIT13;
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J2 = (OpCode32 & BIT11) == BIT11;
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Target |= (!(J2 ^ S) ? BIT23 : 0); // I2
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Target |= (!(J1 ^ S) ? BIT24 : 0); // I1
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Target |= (S ? BIT25 : 0); // S
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Sign = (OpCode32 & BIT26) == BIT26;
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J1Bit = (OpCode32 & BIT13) == BIT13;
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J2Bit = (OpCode32 & BIT11) == BIT11;
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Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
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Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
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Target |= (Sign ? BIT25 : 0); // S
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Target = SignExtend32 (Target, BIT25);
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
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return;
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case POP_T2:
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@ -748,8 +756,8 @@ DisassembleThumbInstruction (
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case STM_FORMAT:
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// <Rn>{!}, <registers>
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W = (OpCode32 & BIT21) == BIT21;
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
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WriteBack = (OpCode32 & BIT21) == BIT21;
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
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return;
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case LDM_REG_IMM12_SIGNED:
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@ -759,7 +767,7 @@ DisassembleThumbInstruction (
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// U == 0 means subtrack, U == 1 means add
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Target = -Target;
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}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
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return;
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case LDM_REG_INDIRECT_LSL:
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@ -784,36 +792,36 @@ DisassembleThumbInstruction (
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case LDM_REG_IMM8:
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// <rt>, [<rn>, {, #<imm8>}]{!}
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W = (OpCode32 & BIT8) == BIT8;
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U = (OpCode32 & BIT9) == BIT9;
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P = (OpCode32 & BIT10) == BIT10;
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WriteBack = (OpCode32 & BIT8) == BIT8;
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UAdd = (OpCode32 & BIT9) == BIT9;
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Pre = (OpCode32 & BIT10) == BIT10;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
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if (P) {
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if (Pre) {
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if ((OpCode32 & 0xff) == 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");
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AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");
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} else {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":"");
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AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");
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}
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} else {
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AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff);
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AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);
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}
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return;
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case LDRD_REG_IMM8_SIGNED:
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// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
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P = (OpCode32 & BIT24) == BIT24; // index = P
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U = (OpCode32 & BIT23) == BIT23;
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W = (OpCode32 & BIT21) == BIT21;
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Pre = (OpCode32 & BIT24) == BIT24; // index = P
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UAdd = (OpCode32 & BIT23) == BIT23;
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WriteBack = (OpCode32 & BIT21) == BIT21;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
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if (P) {
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if (Pre) {
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if ((OpCode32 & 0xff) == 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, "]");
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} else {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":"");
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AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");
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}
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} else {
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if ((OpCode32 & 0xff) != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2);
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AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);
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}
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}
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return;
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@ -825,7 +833,7 @@ DisassembleThumbInstruction (
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// U == 0 means subtrack, U == 1 means add
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Target = -Target;
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}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
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return;
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case LDREXB:
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@ -840,14 +848,14 @@ DisassembleThumbInstruction (
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case SRS_FORMAT:
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// SP{!}, #<mode>
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W = (OpCode32 & BIT21) == BIT21;
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AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f);
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WriteBack = (OpCode32 & BIT21) == BIT21;
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AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);
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return;
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case RFE_FORMAT:
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// <Rn>{!}
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W = (OpCode32 & BIT21) == BIT21;
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");
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WriteBack = (OpCode32 & BIT21) == BIT21;
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");
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return;
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case ADD_IMM12:
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@ -917,9 +925,9 @@ DisassembleThumbInstruction (
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// ADDR <Rd>, <label>
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Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
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if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
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Target = PCAlign4 (PC) - Target;
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Target = PcAlign4 (Pc) - Target;
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} else {
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Target = PCAlign4 (PC) + Target;
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Target = PcAlign4 (Pc) + Target;
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}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
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return;
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@ -932,52 +940,52 @@ DisassembleThumbInstruction (
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case BFC_THUMB2:
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// BFI <Rd>, <Rn>, #<lsb>, #<width>
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msbit = OpCode32 & 0x1f;
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lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
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MsBit = OpCode32 & 0x1f;
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LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
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if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
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// BFC <Rd>, #<lsb>, #<width>
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
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} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
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} else {
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
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}
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return;
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case CPD_THUMB2:
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// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
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coproc = (OpCode32 >> 8) & 0xf;
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opc1 = (OpCode32 >> 20) & 0xf;
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opc2 = (OpCode32 >> 5) & 0x7;
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Coproc = (OpCode32 >> 8) & 0xf;
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Opc1 = (OpCode32 >> 20) & 0xf;
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Opc2 = (OpCode32 >> 5) & 0x7;
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CRd = (OpCode32 >> 12) & 0xf;
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CRn = (OpCode32 >> 16) & 0xf;
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CRm = OpCode32 & 0xf;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm);
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if (opc2 != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
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if (Opc2 != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
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}
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return;
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case MRC_THUMB2:
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// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
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coproc = (OpCode32 >> 8) & 0xf;
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opc1 = (OpCode32 >> 20) & 0xf;
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opc2 = (OpCode32 >> 5) & 0x7;
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Coproc = (OpCode32 >> 8) & 0xf;
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Opc1 = (OpCode32 >> 20) & 0xf;
|
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Opc2 = (OpCode32 >> 5) & 0x7;
|
||||
CRn = (OpCode32 >> 16) & 0xf;
|
||||
CRm = OpCode32 & 0xf;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);
|
||||
if (opc2 != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
|
||||
if (Opc2 != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
|
||||
}
|
||||
return;
|
||||
|
||||
case MRRC_THUMB2:
|
||||
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
|
||||
coproc = (OpCode32 >> 8) & 0xf;
|
||||
opc1 = (OpCode32 >> 20) & 0xf;
|
||||
Coproc = (OpCode32 >> 8) & 0xf;
|
||||
Opc1 = (OpCode32 >> 20) & 0xf;
|
||||
CRn = (OpCode32 >> 16) & 0xf;
|
||||
CRm = OpCode32 & 0xf;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
|
||||
return;
|
||||
|
||||
case THUMB2_2REGS:
|
||||
|
||||
Reference in New Issue
Block a user