diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h index f660e65aac..ff77b16b25 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -98,17 +98,17 @@ // // Translation Control Register // -#define TCR_T0SZ_MASK 0x3F +#define TCR_T0SZ_MASK 0x3FUL -#define TCR_PS_4GB (0 << 16) -#define TCR_PS_64GB (1 << 16) -#define TCR_PS_1TB (2 << 16) -#define TCR_PS_4TB (3 << 16) -#define TCR_PS_16TB (4 << 16) -#define TCR_PS_256TB (5 << 16) +#define TCR_PS_4GB (0UL << 16) +#define TCR_PS_64GB (1UL << 16) +#define TCR_PS_1TB (2UL << 16) +#define TCR_PS_4TB (3UL << 16) +#define TCR_PS_16TB (4UL << 16) +#define TCR_PS_256TB (5UL << 16) -#define TCR_TG0_4KB (0 << 14) -#define TCR_TG1_4KB (2 << 30) +#define TCR_TG0_4KB (0UL << 14) +#define TCR_TG1_4KB (2UL << 30) #define TCR_IPS_4GB (0ULL << 32) #define TCR_IPS_64GB (1ULL << 32) @@ -117,7 +117,7 @@ #define TCR_IPS_16TB (4ULL << 32) #define TCR_IPS_256TB (5ULL << 32) -#define TCR_EPD1 (1 << 23) +#define TCR_EPD1 (1UL << 23) #define TTBR_ASID_FIELD (48) #define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD) @@ -140,75 +140,59 @@ #define TCR_EL1_AS_FIELD (36) #define TCR_EL1_TBI0_FIELD (37) #define TCR_EL1_TBI1_FIELD (38) -#define TCR_EL1_T0SZ_MASK (0x1F << TCR_EL1_T0SZ_FIELD) -#define TCR_EL1_EPD0_MASK (0x1 << TCR_EL1_EPD0_FIELD) -#define TCR_EL1_IRGN0_MASK (0x3 << TCR_EL1_IRGN0_FIELD) -#define TCR_EL1_ORGN0_MASK (0x3 << TCR_EL1_ORGN0_FIELD) -#define TCR_EL1_SH0_MASK (0x3 << TCR_EL1_SH0_FIELD) -#define TCR_EL1_TG0_MASK (0x1 << TCR_EL1_TG0_FIELD) -#define TCR_EL1_T1SZ_MASK (0x1F << TCR_EL1_T1SZ_FIELD) -#define TCR_EL1_A1_MASK (0x1 << TCR_EL1_A1_FIELD) -#define TCR_EL1_EPD1_MASK (0x1 << TCR_EL1_EPD1_FIELD) -#define TCR_EL1_IRGN1_MASK (0x3 << TCR_EL1_IRGN1_FIELD) -#define TCR_EL1_ORGN1_MASK (0x3 << TCR_EL1_ORGN1_FIELD) -#define TCR_EL1_SH1_MASK (0x3 << TCR_EL1_SH1_FIELD) -#define TCR_EL1_TG1_MASK (0x1 << TCR_EL1_TG1_FIELD) -#define TCR_EL1_IPS_MASK (0x7 << TCR_EL1_IPS_FIELD) -#define TCR_EL1_AS_MASK (0x1 << TCR_EL1_AS_FIELD) -#define TCR_EL1_TBI0_MASK (0x1 << TCR_EL1_TBI0_FIELD) -#define TCR_EL1_TBI1_MASK (0x1 << TCR_EL1_TBI1_FIELD) +#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD) +#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD) +#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD) +#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD) +#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD) +#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD) +#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD) +#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD) +#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD) +#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD) +#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD) +#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD) +#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD) +#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD) +#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD) +#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD) +#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD) -#define VTCR_EL23_T0SZ_FIELD (0) -#define VTCR_EL23_IRGN0_FIELD (8) -#define VTCR_EL23_ORGN0_FIELD (10) -#define VTCR_EL23_SH0_FIELD (12) +#define TCR_EL23_T0SZ_FIELD (0) +#define TCR_EL23_IRGN0_FIELD (8) +#define TCR_EL23_ORGN0_FIELD (10) +#define TCR_EL23_SH0_FIELD (12) #define TCR_EL23_TG0_FIELD (14) -#define VTCR_EL23_PS_FIELD (16) -#define TCR_EL23_T0SZ_MASK (0x1F << VTCR_EL23_T0SZ_FIELD) -#define TCR_EL23_IRGN0_MASK (0x3 << VTCR_EL23_IRGN0_FIELD) -#define TCR_EL23_ORGN0_MASK (0x3 << VTCR_EL23_ORGN0_FIELD) -#define TCR_EL23_SH0_MASK (0x3 << VTCR_EL23_SH0_FIELD) -#define TCR_EL23_TG0_MASK (0x1 << TCR_EL23_TG0_FIELD) -#define TCR_EL23_PS_MASK (0x7 << VTCR_EL23_PS_FIELD) +#define TCR_EL23_PS_FIELD (16) +#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD) +#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD) +#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD) +#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD) +#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD) +#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD) -#define VTCR_EL2_T0SZ_FIELD (0) -#define VTCR_EL2_SL0_FIELD (6) -#define VTCR_EL2_IRGN0_FIELD (8) -#define VTCR_EL2_ORGN0_FIELD (10) -#define VTCR_EL2_SH0_FIELD (12) -#define VTCR_EL2_TG0_FIELD (14) -#define VTCR_EL2_PS_FIELD (16) -#define VTCR_EL2_T0SZ_MASK (0x1F << VTCR_EL2_T0SZ_FIELD) -#define VTCR_EL2_SL0_MASK (0x1F << VTCR_EL2_SL0_FIELD) -#define VTCR_EL2_IRGN0_MASK (0x3 << VTCR_EL2_IRGN0_FIELD) -#define VTCR_EL2_ORGN0_MASK (0x3 << VTCR_EL2_ORGN0_FIELD) -#define VTCR_EL2_SH0_MASK (0x3 << VTCR_EL2_SH0_FIELD) -#define VTCR_EL2_TG0_MASK (0x1 << VTCR_EL2_TG0_FIELD) -#define VTCR_EL2_PS_MASK (0x7 << VTCR_EL2_PS_FIELD) +#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10) +#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10) +#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10) +#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10) +#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8) +#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8) +#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8) +#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8) -#define TCR_RGN_OUTER_NON_CACHEABLE (0x0 << 10) -#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1 << 10) -#define TCR_RGN_OUTER_WRITE_THROUGH (0x2 << 10) -#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3 << 10) +#define TCR_SH_NON_SHAREABLE (0x0UL << 12) +#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12) +#define TCR_SH_INNER_SHAREABLE (0x3UL << 12) -#define TCR_RGN_INNER_NON_CACHEABLE (0x0 << 8) -#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1 << 8) -#define TCR_RGN_INNER_WRITE_THROUGH (0x2 << 8) -#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3 << 8) - -#define TCR_SH_NON_SHAREABLE (0x0 << 12) -#define TCR_SH_OUTER_SHAREABLE (0x2 << 12) -#define TCR_SH_INNER_SHAREABLE (0x3 << 12) - -#define TCR_PASZ_32BITS_4GB (0x0) -#define TCR_PASZ_36BITS_64GB (0x1) -#define TCR_PASZ_40BITS_1TB (0x2) -#define TCR_PASZ_42BITS_4TB (0x3) -#define TCR_PASZ_44BITS_16TB (0x4) -#define TCR_PASZ_48BITS_256TB (0x5) +#define TCR_PASZ_32BITS_4GB (0x0UL) +#define TCR_PASZ_36BITS_64GB (0x1UL) +#define TCR_PASZ_40BITS_1TB (0x2UL) +#define TCR_PASZ_42BITS_4TB (0x3UL) +#define TCR_PASZ_44BITS_16TB (0x4UL) +#define TCR_PASZ_48BITS_256TB (0x5UL) // The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit // Virtual address range for 512GB of virtual space sets T*SZ to 25