ArmPkg/ArmGicLib: Replaced 'ArmGicAcknowledgeSgiFrom' by 'ArmGicAcknowledgeInterrupt'
The function 'ArmGicAcknowledgeSgiFrom' was actually acknowledging Interrupts (and not only SGIs). ArmPkg/ArmGicLib: Introduced the PCD PcdGicPrimaryCoreId This PCD defines the Id of the primary core in the GIC. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13259 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -59,6 +59,13 @@ PrimaryMain (
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ASSERT_EFI_ERROR (Status);
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DEBUG_CODE_END();
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// Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
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DEBUG_CODE_BEGIN();
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if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
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DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
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}
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DEBUG_CODE_END();
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// Enable the GIC Distributor
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ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
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@@ -88,6 +95,7 @@ SecondaryMain (
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UINT32 CoreId;
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VOID (*SecondaryStart)(VOID);
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UINTN SecondaryEntryAddr;
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UINTN AcknowledgedCoreId;
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ClusterId = GET_CLUSTER_ID(MpId);
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CoreId = GET_CORE_ID(MpId);
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@@ -113,12 +121,15 @@ SecondaryMain (
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// Clear Secondary cores MailBox
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MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
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SecondaryEntryAddr = 0;
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while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {
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do {
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ArmCallWFI ();
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// Read the Mailbox
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SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
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}
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ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), &AcknowledgedCoreId, NULL);
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} while ((SecondaryEntryAddr == 0) && (AcknowledgedCoreId != PcdGet32 (PcdGicPrimaryCoreId)));
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// Jump to secondary core entry point.
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SecondaryStart = (VOID (*)())SecondaryEntryAddr;
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