ArmPlatformPkg: PL061 - rewrite the hardware interaction
The PL061 GPIO controller is a bit of an anachronism, and the existing driver does nothing to hide this - leading to it being very tricky to read. Rewrite it to document (in comments and code) what is actually happening, and fix some bugs in the process. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
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@@ -19,6 +19,7 @@
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#include <Protocol/EmbeddedGpio.h>
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// PL061 GPIO Registers
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#define PL061_GPIO_DATA_REG_OFFSET ((UINTN) 0x000)
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#define PL061_GPIO_DATA_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x000)
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#define PL061_GPIO_DIR_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x400)
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#define PL061_GPIO_IS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x404)
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@@ -46,9 +47,5 @@
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// All bits low except one bit high, native bit length
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#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
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// All bits low except one bit high, restricted to 8 bits (i.e. ensures zeros above 8bits)
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#define GPIO_PIN_MASK_HIGH_8BIT(Pin) (GPIO_PIN_MASK(Pin) && 0xFF)
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// All bits high except one bit low, restricted to 8 bits (i.e. ensures zeros above 8bits)
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#define GPIO_PIN_MASK_LOW_8BIT(Pin) ((~GPIO_PIN_MASK(Pin)) && 0xFF)
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#endif // __PL061_GPIO_H__
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