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ARM Packages: Removed trailing spaces

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Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ronald Cron
2014-08-19 13:29:52 +00:00
committed by oliviermartin
parent 62d441fb17
commit 3402aac7d9
554 changed files with 6333 additions and 6345 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c
View File

@@ -2,7 +2,7 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2014, ARM Limited. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -13,7 +13,7 @@
**/
#include "CpuDxe.h"
#include "CpuDxe.h"
//FIXME: Will not compile on non-ARMv7 builds
#include <Chipset/ArmV7.h>
@@ -45,9 +45,9 @@ EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1];
/**
This function registers and enables the handler specified by InterruptHandler for a processor
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
This function registers and enables the handler specified by InterruptHandler for a processor
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
The installed handler is called once for each processor interrupt or exception.
@param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
@@ -102,7 +102,7 @@ CommonCExceptionHandler (
DEBUG ((EFI_D_ERROR, "Unknown exception type %d from %08x\n", ExceptionType, SystemContext.SystemContextArm->PC));
ASSERT (FALSE);
}
if (ExceptionType == EXCEPT_ARM_SOFTWARE_INTERRUPT) {
//
// ARM JTAG debuggers some times use this vector, so it is not an error to get one
@@ -139,8 +139,8 @@ InitializeExceptions (
Cpu->DisableInterrupt (Cpu);
//
// EFI does not use the FIQ, but a debugger might so we must disable
// as we take over the exception vectors.
// EFI does not use the FIQ, but a debugger might so we must disable
// as we take over the exception vectors.
//
FiqEnabled = ArmGetFiqState ();
ArmDisableFiq ();
@@ -224,7 +224,7 @@ InitializeExceptions (
}
if (IrqEnabled) {
//
//
// Restore interrupt state
//
Status = Cpu->EnableInterrupt (Cpu);

74
ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S
View File

@@ -1,4 +1,4 @@
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
#
# Use ARMv6 instruction to operate on a single stack
#
@@ -22,7 +22,7 @@
This is the stack constructed by the exception handler (low address to high address)
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
Reg Offset
=== ======
=== ======
R0 0x00 # stmfd SP!,{R0-R12}
R1 0x04
R2 0x08
@@ -44,14 +44,14 @@ This is the stack constructed by the exception handler (low address to high addr
DFAR 0x48
IFSR 0x4c
IFAR 0x50
LR 0x54 # SVC Link register (we need to restore it)
LR 0x58 # pushed by srsfd
CPSR 0x5c
LR 0x58 # pushed by srsfd
CPSR 0x5c
*/
GCC_ASM_EXPORT(ExceptionHandlersStart)
GCC_ASM_EXPORT(ExceptionHandlersEnd)
@@ -103,7 +103,7 @@ ASM_PFX(ResetEntry):
stmfd SP!,{LR} @ Store the link register for the current mode
sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} @ Store the register state
mov R0,#0 @ ExceptionType
ldr R1,ASM_PFX(CommonExceptionEntry)
bx R1
@@ -200,53 +200,53 @@ ASM_PFX(CommonExceptionEntry):
ASM_PFX(ExceptionHandlersEnd):
//
// This code runs from CpuDxe driver loaded address. It is patched into
// This code runs from CpuDxe driver loaded address. It is patched into
// CommonExceptionEntry.
//
ASM_PFX(AsmCommonExceptionEntry):
mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R3, #0x10 @
cmpne R3, #0x10 @
stmeqed R2, {lr}^ @ save unbanked lr
@ else
@ else
stmneed R2, {lr} @ save SVC lr
ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
@ Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType == 2)) {
cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
addne R5, R5, #2 @ PC += 2;
strne R5,[SP,#0x58] @ Update LR value pushed by srsfd
NoAdjustNeeded:
str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
add R1, SP, #0x60 @ We pushed 0x60 bytes on the stack
str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
@ R0 is ExceptionType
mov R1,SP @ R1 is SystemContext
@ R0 is ExceptionType
mov R1,SP @ R1 is SystemContext
#if (FixedPcdGet32(PcdVFPEnabled))
vpush {d0-d15} @ save vstm registers in case they are used in optimizations
@@ -256,7 +256,7 @@ NoAdjustNeeded:
tst R4, #4
subne SP, SP, #4 @ Adjust SP if not 8-byte aligned
/*
/*
VOID
EFIAPI
CommonCExceptionHandler (
@@ -264,13 +264,13 @@ CommonCExceptionHandler (
IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
)
*/
*/
blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
mov SP, R4 @ Restore SP
#if (FixedPcdGet32(PcdVFPEnabled))
vpop {d0-d15}
vpop {d0-d15}
#endif
ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
@@ -278,26 +278,26 @@ CommonCExceptionHandler (
ldr R1, [SP, #0x44] @ Restore EFI_SYSTEM_CONTEXT_ARM.DFSR
mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R1, R1, #0x1f @ Check to see if User or System Mode
cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R1, #0x10 @
cmpne R1, #0x10 @
ldmeqed R2, {lr}^ @ restore unbanked lr
@ else
ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
ldmfd SP!,{R0-R12} @ Restore general purpose registers
@ Exception handler can not change SP
add SP,SP,#0x20 @ Clear out the remaining stack space
ldmfd SP!,{LR} @ restore the link register for this context
rfefd SP! @ return from exception via srsfd stack slot

78
ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm
View File

@@ -1,4 +1,4 @@
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Use ARMv6 instruction to operate on a single stack
//
@@ -22,7 +22,7 @@
This is the stack constructed by the exception handler (low address to high address)
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
Reg Offset
=== ======
=== ======
R0 0x00 # stmfd SP!,{R0-R12}
R1 0x04
R2 0x08
@@ -44,15 +44,15 @@ This is the stack constructed by the exception handler (low address to high addr
DFAR 0x48
IFSR 0x4c
IFAR 0x50
LR 0x54 # SVC Link register (we need to restore it)
LR 0x58 # pushed by srsfd
CPSR 0x5c
LR 0x58 # pushed by srsfd
CPSR 0x5c
*/
EXPORT ExceptionHandlersStart
EXPORT ExceptionHandlersEnd
EXPORT CommonExceptionEntry
@@ -61,7 +61,7 @@ This is the stack constructed by the exception handler (low address to high addr
PRESERVE8
AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5
//
// This code gets copied to the ARM vector table
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
@@ -98,7 +98,7 @@ ResetEntry
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#0 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
@@ -112,7 +112,7 @@ UndefinedInstructionEntry
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#1 ; ExceptionType
ldr R1,CommonExceptionEntry;
ldr R1,CommonExceptionEntry;
bx R1
SoftwareInterruptEntry
@@ -195,53 +195,53 @@ CommonExceptionEntry
ExceptionHandlersEnd
//
// This code runs from CpuDxe driver loaded address. It is patched into
// This code runs from CpuDxe driver loaded address. It is patched into
// CommonExceptionEntry.
//
AsmCommonExceptionEntry
mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack
ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack
str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R3, R1, #0x1f ; Check CPSR to see if User or System Mode
cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R3, #0x10 ;
cmpne R3, #0x10 ;
stmeqed R2, {lr}^ ; save unbanked lr
; else
; else
stmneed R2, {lr} ; save SVC lr
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
; Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) {
cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb
cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
addne R5, R5, #2 ; PC += 2;
strne R5,[SP,#0x58] ; Update LR value pushed by srsfd
NoAdjustNeeded
str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC
add R1, SP, #0x60 ; We pushed 0x60 bytes on the stack
str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP
; R0 is ExceptionType
mov R1,SP ; R1 is SystemContext
; R0 is ExceptionType
mov R1,SP ; R1 is SystemContext
#if (FixedPcdGet32(PcdVFPEnabled))
vpush {d0-d15} ; save vstm registers in case they are used in optimizations
@@ -251,7 +251,7 @@ NoAdjustNeeded
tst R4, #4
subne SP, SP, #4 ; Adjust SP if not 8-byte aligned
/*
/*
VOID
EFIAPI
CommonCExceptionHandler (
@@ -267,35 +267,35 @@ CommonCExceptionHandler (
#if (FixedPcdGet32(PcdVFPEnabled))
vpop {d0-d15}
#endif
ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
ldr R1, [SP, #0x44] ; Restore EFI_SYSTEM_CONTEXT_ARM.DFSR
mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored
str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored
ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR
str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored
str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored
add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R1, R1, #0x1f ; Check to see if User or System Mode
cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R1, #0x10 ;
cmpne R1, #0x10 ;
ldmeqed R2, {lr}^ ; restore unbanked lr
; else
ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}
ldmfd SP!,{R0-R12} ; Restore general purpose registers
; Exception handler can not change SP
add SP,SP,#0x20 ; Clear out the remaining stack space
ldmfd SP!,{LR} ; restore the link register for this context
rfefd SP! ; return from exception via srsfd stack slot
END

32
ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c
View File

@@ -24,7 +24,7 @@ typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
// Second Level Descriptors
typedef UINT32 ARM_PAGE_TABLE_ENTRY;
EFI_STATUS
EFI_STATUS
SectionToGcdAttributes (
IN UINT32 SectionAttributes,
OUT UINT64 *GcdAttributes
@@ -418,12 +418,12 @@ UpdatePageEntries (
// Calculate number of 4KB page table entries to change
NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
// Iterate for the number of 4KB pages to change
Offset = 0;
for(p = 0; p < NumPageEntries; p++) {
// Calculate index into first level translation table for page table value
FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
@@ -435,9 +435,9 @@ UpdatePageEntries (
Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
if (EFI_ERROR(Status)) {
// Exit for loop
break;
}
break;
}
// Re-read descriptor
Descriptor = FirstLevelTable[FirstLevelIdx];
}
@@ -462,7 +462,7 @@ UpdatePageEntries (
// Make this virtual address point at a physical page
PageTableEntry &= ~VirtualMask;
}
if (CurrentPageTableEntry != PageTableEntry) {
Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {
@@ -471,14 +471,14 @@ UpdatePageEntries (
WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);
}
// Only need to update if we are changing the entry
PageTable[PageTableIndex] = PageTableEntry;
// Only need to update if we are changing the entry
PageTable[PageTableIndex] = PageTableEntry;
ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
}
Status = EFI_SUCCESS;
Offset += TT_DESCRIPTOR_PAGE_SIZE;
} // End first level translation table loop
return Status;
@@ -508,7 +508,7 @@ UpdateSectionEntries (
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
// EntryValue: values at bit positions specified by EntryMask
// Make sure we handle a section range that is unmapped
// Make sure we handle a section range that is unmapped
EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;
EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
@@ -567,7 +567,7 @@ UpdateSectionEntries (
// calculate number of 1MB first level entries this applies to
NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
// iterate through each descriptor
for(i=0; i<NumSections; i++) {
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
@@ -578,7 +578,7 @@ UpdateSectionEntries (
Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);
} else {
// still a section entry
// mask off appropriate fields
Descriptor = CurrentDescriptor & ~EntryMask;
@@ -596,7 +596,7 @@ UpdateSectionEntries (
WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);
}
// Only need to update if we are changing the descriptor
// Only need to update if we are changing the descriptor
FirstLevelTable[FirstLevelIdx + i] = Descriptor;
ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
}
@@ -608,7 +608,7 @@ UpdateSectionEntries (
return Status;
}
EFI_STATUS
EFI_STATUS
ConvertSectionToPages (
IN EFI_PHYSICAL_ADDRESS BaseAddress
)
@@ -673,7 +673,7 @@ SetMemoryAttributes (
)
{
EFI_STATUS Status;
if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
// Is the base and length a multiple of 1 MB?
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));