ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
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62d441fb17
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3402aac7d9
@@ -24,7 +24,7 @@ typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
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// Second Level Descriptors
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typedef UINT32 ARM_PAGE_TABLE_ENTRY;
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EFI_STATUS
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EFI_STATUS
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SectionToGcdAttributes (
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IN UINT32 SectionAttributes,
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OUT UINT64 *GcdAttributes
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@@ -418,12 +418,12 @@ UpdatePageEntries (
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// Calculate number of 4KB page table entries to change
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NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
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// Iterate for the number of 4KB pages to change
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Offset = 0;
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for(p = 0; p < NumPageEntries; p++) {
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// Calculate index into first level translation table for page table value
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FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
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ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
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@@ -435,9 +435,9 @@ UpdatePageEntries (
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Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
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if (EFI_ERROR(Status)) {
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// Exit for loop
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break;
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}
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break;
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}
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// Re-read descriptor
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Descriptor = FirstLevelTable[FirstLevelIdx];
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}
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@@ -462,7 +462,7 @@ UpdatePageEntries (
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// Make this virtual address point at a physical page
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PageTableEntry &= ~VirtualMask;
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}
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if (CurrentPageTableEntry != PageTableEntry) {
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Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
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if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) {
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@@ -471,14 +471,14 @@ UpdatePageEntries (
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WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE);
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}
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// Only need to update if we are changing the entry
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PageTable[PageTableIndex] = PageTableEntry;
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// Only need to update if we are changing the entry
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PageTable[PageTableIndex] = PageTableEntry;
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ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
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}
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Status = EFI_SUCCESS;
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Offset += TT_DESCRIPTOR_PAGE_SIZE;
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} // End first level translation table loop
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return Status;
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@@ -508,7 +508,7 @@ UpdateSectionEntries (
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// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
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// EntryValue: values at bit positions specified by EntryMask
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// Make sure we handle a section range that is unmapped
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// Make sure we handle a section range that is unmapped
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EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK;
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EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
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@@ -567,7 +567,7 @@ UpdateSectionEntries (
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// calculate number of 1MB first level entries this applies to
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NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
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// iterate through each descriptor
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for(i=0; i<NumSections; i++) {
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CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
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@@ -578,7 +578,7 @@ UpdateSectionEntries (
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Status = UpdatePageEntries ((FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT, TT_DESCRIPTOR_SECTION_SIZE, Attributes, VirtualMask);
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} else {
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// still a section entry
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// mask off appropriate fields
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Descriptor = CurrentDescriptor & ~EntryMask;
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@@ -596,7 +596,7 @@ UpdateSectionEntries (
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WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);
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}
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// Only need to update if we are changing the descriptor
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// Only need to update if we are changing the descriptor
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FirstLevelTable[FirstLevelIdx + i] = Descriptor;
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ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
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}
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@@ -608,7 +608,7 @@ UpdateSectionEntries (
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return Status;
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}
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EFI_STATUS
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EFI_STATUS
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ConvertSectionToPages (
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IN EFI_PHYSICAL_ADDRESS BaseAddress
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)
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@@ -673,7 +673,7 @@ SetMemoryAttributes (
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)
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{
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EFI_STATUS Status;
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if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
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// Is the base and length a multiple of 1 MB?
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DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
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