ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ronald Cron
committed by
oliviermartin
oliviermartin
parent
62d441fb17
commit
3402aac7d9
@@ -1,15 +1,15 @@
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/** @file
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Thumb Dissassembler. Still a work in progress.
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Wrong output is a bug, so please fix it.
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Wrong output is a bug, so please fix it.
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Hex output means there is not yet an entry or a decode bug.
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gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit
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16-bit stream of Thumb2 instruction. Then there are big case
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gOpThumb[] are Thumb 16-bit, and gOpThumb2[] work on the 32-bit
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16-bit stream of Thumb2 instruction. Then there are big case
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statements to print everything out. If you are adding instructions
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try to reuse existing case entries if possible.
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@@ -32,13 +32,13 @@ extern CHAR8 *gReg[];
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// Thumb address modes
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#define LOAD_STORE_FORMAT1 1
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#define LOAD_STORE_FORMAT1_H 101
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#define LOAD_STORE_FORMAT1_B 111
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#define LOAD_STORE_FORMAT1_B 111
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#define LOAD_STORE_FORMAT2 2
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#define LOAD_STORE_FORMAT3 3
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#define LOAD_STORE_FORMAT4 4
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#define LOAD_STORE_MULTIPLE_FORMAT1 5
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#define PUSH_FORMAT 6
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#define POP_FORMAT 106
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#define LOAD_STORE_MULTIPLE_FORMAT1 5
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#define PUSH_FORMAT 6
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#define POP_FORMAT 106
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#define IMMED_8 7
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#define CONDITIONAL_BRANCH 8
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#define UNCONDITIONAL_BRANCH 9
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@@ -93,8 +93,8 @@ extern CHAR8 *gReg[];
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#define THUMB2_4REGS 230
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#define ADD_IMM12_1REG 231
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#define THUMB2_IMM16 232
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#define MRC_THUMB2 233
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#define MRRC_THUMB2 234
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#define MRC_THUMB2 233
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#define MRRC_THUMB2 234
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#define THUMB2_MRS 235
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#define THUMB2_MSR 236
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@@ -118,7 +118,7 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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{ "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },
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{ "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
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{ "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },
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{ "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },
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{ "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },
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{ "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },
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{ "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },
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@@ -156,7 +156,7 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
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{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
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{ "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },
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{ "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
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@@ -212,8 +212,8 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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THUMB_INSTRUCTIONS gOpThumb2[] = {
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//Instruct OpCode OpCode Mask Addressig Mode
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{ "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
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{ "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
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{ "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD
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{ "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
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{ "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
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@@ -225,7 +225,7 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>
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{ "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>
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{ "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>
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{ "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
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{ "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>
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@@ -249,11 +249,11 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2
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{ "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>
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{ "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>
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{ "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2
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{ "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>
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{ "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>
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{ "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2
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{ "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>
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{ "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>
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{ "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>
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{ "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>
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@@ -317,19 +317,19 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>
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{ "LDM" , 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>
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{ "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>
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{ "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}
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{ "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}
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{ "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}
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{ "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}
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{ "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}
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{ "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>
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{ "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>
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{ "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>
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{ "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
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{ "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
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{ "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>
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{ "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>
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{ "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>
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{ "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
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{ "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
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{ "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
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{ "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
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{ "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
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@@ -339,25 +339,25 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}
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{ "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}
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{ "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}
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{ "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?
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{ "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?
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{ "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}
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{ "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}
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{ "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}
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{ "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?
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{ "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?
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{ "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}
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{ "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}
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{ "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}
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{ "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
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{ "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>
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{ "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]
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{ "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]
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{ "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]
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{ "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]
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{ "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}
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{ "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]
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{ "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]
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{ "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]
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{ "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]
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{ "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}
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{ "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}
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{ "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}
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{ "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
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{ "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
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{ "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
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@@ -366,15 +366,15 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}
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{ "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}
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{ "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}
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{ "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}
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{ "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}
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{ "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
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{ "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]
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{ "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]
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{ "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]
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{ "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]
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{ "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]
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{ "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]
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{ "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]
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{ "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]
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{ "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
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{ "SRS" , 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
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@@ -399,24 +399,24 @@ ThumbMRegList (
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UINTN Index, Start, End;
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CHAR8 *Str;
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BOOLEAN First;
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Str = mThumbMregListStr;
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*Str = '\0';
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AsciiStrCat (Str, "{");
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for (Index = 0, First = TRUE; Index <= 15; Index++) {
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if ((RegBitMask & (1 << Index)) != 0) {
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Start = End = Index;
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for (Index++; ((RegBitMask & (1 << Index)) != 0) && (Index <= 9); Index++) {
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End = Index;
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}
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if (!First) {
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AsciiStrCat (Str, ",");
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} else {
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First = FALSE;
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}
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if (Start == End) {
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AsciiStrCat (Str, gReg[Start]);
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} else {
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@@ -430,7 +430,7 @@ ThumbMRegList (
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AsciiStrCat (Str, "ERROR");
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}
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AsciiStrCat (Str, "}");
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// BugBug: Make caller pass in buffer it is cleaner
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return mThumbMregListStr;
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}
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@@ -444,17 +444,17 @@ SignExtend32 (
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if (((Data & TopBit) == 0) || (TopBit == BIT31)) {
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return Data;
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}
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do {
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TopBit <<= 1;
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Data |= TopBit;
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Data |= TopBit;
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} while ((TopBit & BIT31) != BIT31);
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return Data;
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}
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//
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// Some instructions specify the PC is always considered aligned
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// Some instructions specify the PC is always considered aligned
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// The PC is after the instruction that is excuting. So you pass
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// in the instruction address and you get back the aligned answer
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//
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@@ -467,17 +467,17 @@ PCAlign4 (
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}
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/**
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Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
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point to next instructin.
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We cheat and only decode instructions that access
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Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
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point to next instructin.
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We cheat and only decode instructions that access
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memory. If the instruction is not found we dump the instruction in hex.
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@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
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@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
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@param Buf Buffer to sprintf disassembly into.
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@param Size Size of Buf in bytes.
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@param Size Size of Buf in bytes.
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@param Extended TRUE dump hex for instruction too.
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**/
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VOID
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DisassembleThumbInstruction (
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@@ -499,12 +499,12 @@ DisassembleThumbInstruction (
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UINT32 PC, Target, msbit, lsbit;
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CHAR8 *Cond;
|
||||
BOOLEAN S, J1, J2, P, U, W;
|
||||
UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
|
||||
UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
|
||||
UINT32 Mask;
|
||||
|
||||
OpCodePtr = *OpCodePtrPtr;
|
||||
OpCode = **OpCodePtrPtr;
|
||||
|
||||
|
||||
// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
|
||||
OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);
|
||||
|
||||
@@ -519,7 +519,7 @@ DisassembleThumbInstruction (
|
||||
|
||||
// Increment by the minimum instruction size, Thumb2 could be bigger
|
||||
*OpCodePtrPtr += 1;
|
||||
|
||||
|
||||
// Manage IT Block ItFlag TRUE means we are in an IT block
|
||||
/*if (*ItBlock != 0) {
|
||||
ItFlag = TRUE;
|
||||
@@ -531,58 +531,58 @@ DisassembleThumbInstruction (
|
||||
for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {
|
||||
if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {
|
||||
if (Extended) {
|
||||
Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode, gOpThumb[Index].Start);
|
||||
Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode, gOpThumb[Index].Start);
|
||||
} else {
|
||||
Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);
|
||||
Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);
|
||||
}
|
||||
switch (gOpThumb[Index].AddressMode) {
|
||||
case LOAD_STORE_FORMAT1:
|
||||
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
|
||||
return;
|
||||
case LOAD_STORE_FORMAT1_H:
|
||||
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);
|
||||
return;
|
||||
case LOAD_STORE_FORMAT1_B:
|
||||
// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);
|
||||
return;
|
||||
|
||||
case LOAD_STORE_FORMAT2:
|
||||
// A6.5.1 <Rd>, [<Rn>, <Rm>]
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
|
||||
return;
|
||||
case LOAD_STORE_FORMAT3:
|
||||
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
|
||||
Target = (OpCode & 0xff) << 2;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
|
||||
return;
|
||||
case LOAD_STORE_FORMAT4:
|
||||
// Rt, [SP, #imm8]
|
||||
Target = (OpCode & 0xff) << 2;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);
|
||||
return;
|
||||
|
||||
|
||||
case LOAD_STORE_MULTIPLE_FORMAT1:
|
||||
// <Rn>!, {r0-r7}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
|
||||
return;
|
||||
|
||||
|
||||
case POP_FORMAT:
|
||||
// POP {r0-r7,pc}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
|
||||
return;
|
||||
|
||||
case PUSH_FORMAT:
|
||||
// PUSH {r0-r7,lr}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
|
||||
return;
|
||||
|
||||
|
||||
|
||||
case IMMED_8:
|
||||
// A6.7 <immed_8>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
|
||||
return;
|
||||
|
||||
case CONDITIONAL_BRANCH:
|
||||
@@ -591,83 +591,83 @@ DisassembleThumbInstruction (
|
||||
Cond = gCondition[(OpCode >> 8) & 0xf];
|
||||
Buf[Offset-5] = *Cond++;
|
||||
Buf[Offset-4] = *Cond;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
|
||||
return;
|
||||
case UNCONDITIONAL_BRANCH_SHORT:
|
||||
// A6.3.2 B <target_address>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
|
||||
return;
|
||||
|
||||
|
||||
case BRANCH_EXCHANGE:
|
||||
// A6.3.3 BX|BLX <Rm>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
|
||||
return;
|
||||
|
||||
case DATA_FORMAT1:
|
||||
// A6.4.3 <Rd>, <Rn>, <Rm>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
|
||||
return;
|
||||
case DATA_FORMAT2:
|
||||
// A6.4.3 <Rd>, <Rn>, #3_bit_immed
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
|
||||
return;
|
||||
case DATA_FORMAT3:
|
||||
// A6.4.3 <Rd>|<Rn>, #imm8
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
|
||||
return;
|
||||
case DATA_FORMAT4:
|
||||
// A6.4.3 <Rd>|<Rm>, #immed_5
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
|
||||
return;
|
||||
case DATA_FORMAT5:
|
||||
// A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
|
||||
return;
|
||||
case DATA_FORMAT6_SP:
|
||||
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
|
||||
return;
|
||||
case DATA_FORMAT6_PC:
|
||||
// A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
|
||||
return;
|
||||
case DATA_FORMAT7:
|
||||
// A6.4.3 SP, SP, #<7_Bit_immed>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
|
||||
return;
|
||||
case DATA_FORMAT8:
|
||||
// A6.4.3 <Rd>|<Rn>, <Rm>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
|
||||
return;
|
||||
|
||||
|
||||
case CPS_FORMAT:
|
||||
// A7.1.24
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
|
||||
return;
|
||||
|
||||
case ENDIAN_FORMAT:
|
||||
// A7.1.24
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
|
||||
return;
|
||||
|
||||
case DATA_CBZ:
|
||||
// CB{N}Z <Rn>, <Lable>
|
||||
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);
|
||||
return;
|
||||
|
||||
case ADR_FORMAT:
|
||||
// ADR <Rd>, <Label>
|
||||
Target = (OpCode & 0xff) << 2;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
|
||||
return;
|
||||
|
||||
case IT_BLOCK:
|
||||
// ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]
|
||||
// ITSTATE[7:5] == cond[3:1]
|
||||
// ITSTATE[4] == 1st Instruction cond[0]
|
||||
// ITSTATE[3] == 2st Instruction cond[0]
|
||||
// ITSTATE[2] == 3st Instruction cond[0]
|
||||
// ITSTATE[4] == 1st Instruction cond[0]
|
||||
// ITSTATE[3] == 2st Instruction cond[0]
|
||||
// ITSTATE[2] == 3st Instruction cond[0]
|
||||
// ITSTATE[1] == 4st Instruction cond[0]
|
||||
// ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions
|
||||
// 1st one in ITSTATE low bits defines the number of instructions
|
||||
@@ -684,13 +684,13 @@ DisassembleThumbInstruction (
|
||||
} else if ((OpCode & 0xf) == 0x8) {
|
||||
*ItBlock = 1;
|
||||
}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
// Thumb2 are 32-bit instructions
|
||||
*OpCodePtrPtr += 1;
|
||||
Rt = (OpCode32 >> 12) & 0xf;
|
||||
@@ -701,9 +701,9 @@ DisassembleThumbInstruction (
|
||||
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
|
||||
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {
|
||||
if (Extended) {
|
||||
Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode32, gOpThumb2[Index].Start);
|
||||
Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode32, gOpThumb2[Index].Start);
|
||||
} else {
|
||||
Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);
|
||||
Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);
|
||||
}
|
||||
switch (gOpThumb2[Index].AddressMode) {
|
||||
case B_T3:
|
||||
@@ -716,7 +716,7 @@ DisassembleThumbInstruction (
|
||||
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
|
||||
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
|
||||
Target = SignExtend32 (Target, BIT20);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
||||
return;
|
||||
case B_T4:
|
||||
// S:I1:I2:imm10:imm11:0
|
||||
@@ -728,7 +728,7 @@ DisassembleThumbInstruction (
|
||||
Target |= (!(J1 ^ S) ? BIT23 : 0); // I1
|
||||
Target |= (S ? BIT24 : 0); // S
|
||||
Target = SignExtend32 (Target, BIT24);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
||||
return;
|
||||
|
||||
case BL_T2:
|
||||
@@ -741,7 +741,7 @@ DisassembleThumbInstruction (
|
||||
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1
|
||||
Target |= (S ? BIT25 : 0); // S
|
||||
Target = SignExtend32 (Target, BIT25);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
|
||||
return;
|
||||
|
||||
case POP_T2:
|
||||
@@ -750,7 +750,7 @@ DisassembleThumbInstruction (
|
||||
return;
|
||||
|
||||
case POP_T3:
|
||||
// <register>
|
||||
// <register>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);
|
||||
return;
|
||||
|
||||
@@ -762,7 +762,7 @@ DisassembleThumbInstruction (
|
||||
|
||||
case LDM_REG_IMM12_SIGNED:
|
||||
// <rt>, <label>
|
||||
Target = OpCode32 & 0xfff;
|
||||
Target = OpCode32 & 0xfff;
|
||||
if ((OpCode32 & BIT23) == 0) {
|
||||
// U == 0 means subtrack, U == 1 means add
|
||||
Target = -Target;
|
||||
@@ -779,7 +779,7 @@ DisassembleThumbInstruction (
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);
|
||||
}
|
||||
return;
|
||||
|
||||
|
||||
case LDM_REG_IMM12:
|
||||
// <rt>, [<rn>, {, #<imm12>]}
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
|
||||
@@ -810,7 +810,7 @@ DisassembleThumbInstruction (
|
||||
case LDRD_REG_IMM8_SIGNED:
|
||||
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
|
||||
P = (OpCode32 & BIT24) == BIT24; // index = P
|
||||
U = (OpCode32 & BIT23) == BIT23;
|
||||
U = (OpCode32 & BIT23) == BIT23;
|
||||
W = (OpCode32 & BIT21) == BIT21;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
|
||||
if (P) {
|
||||
@@ -826,9 +826,9 @@ DisassembleThumbInstruction (
|
||||
}
|
||||
return;
|
||||
|
||||
case LDRD_REG_IMM8:
|
||||
// LDRD <rt>, <rt2>, <label>
|
||||
Target = (OpCode32 & 0xff) << 2;
|
||||
case LDRD_REG_IMM8:
|
||||
// LDRD <rt>, <rt2>, <label>
|
||||
Target = (OpCode32 & 0xff) << 2;
|
||||
if ((OpCode32 & BIT23) == 0) {
|
||||
// U == 0 means subtrack, U == 1 means add
|
||||
Target = -Target;
|
||||
@@ -845,7 +845,7 @@ DisassembleThumbInstruction (
|
||||
// LDREXD <Rt>, <Rt2>, [<Rn>]
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);
|
||||
return;
|
||||
|
||||
|
||||
case SRS_FORMAT:
|
||||
// SP{!}, #<mode>
|
||||
W = (OpCode32 & BIT21) == BIT21;
|
||||
@@ -857,14 +857,14 @@ DisassembleThumbInstruction (
|
||||
W = (OpCode32 & BIT21) == BIT21;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");
|
||||
return;
|
||||
|
||||
|
||||
case ADD_IMM12:
|
||||
// ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8
|
||||
if ((OpCode32 & BIT20) == BIT20) {
|
||||
Buf[Offset - 3] = 'S'; // assume %-6a
|
||||
}
|
||||
Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
|
||||
return;
|
||||
|
||||
case ADD_IMM12_1REG:
|
||||
@@ -873,14 +873,14 @@ DisassembleThumbInstruction (
|
||||
Buf[Offset - 3] = 'S'; // assume %-6a
|
||||
}
|
||||
Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
|
||||
return;
|
||||
|
||||
case THUMB2_IMM16:
|
||||
// MOVW <Rd>, #<const> i:imm3:imm8
|
||||
Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
|
||||
Target |= ((OpCode32 >> 4) & 0xf0000);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
|
||||
return;
|
||||
|
||||
case ADD_IMM5:
|
||||
@@ -889,18 +889,18 @@ DisassembleThumbInstruction (
|
||||
Buf[Offset - 3] = 'S'; // assume %-6a
|
||||
}
|
||||
Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
|
||||
if (Target != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
|
||||
}
|
||||
return;
|
||||
|
||||
case ADD_IMM5_2REG:
|
||||
// CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2
|
||||
Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);
|
||||
if (Target != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
|
||||
}
|
||||
|
||||
|
||||
@@ -910,7 +910,7 @@ DisassembleThumbInstruction (
|
||||
Buf[Offset - 3] = 'S'; // assume %-6a
|
||||
}
|
||||
Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);
|
||||
return;
|
||||
|
||||
case ASR_3REG:
|
||||
@@ -918,7 +918,7 @@ DisassembleThumbInstruction (
|
||||
if ((OpCode32 & BIT20) == BIT20) {
|
||||
Buf[Offset - 3] = 'S'; // assume %-6a
|
||||
}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);
|
||||
return;
|
||||
|
||||
case ADR_THUMB2:
|
||||
@@ -929,13 +929,13 @@ DisassembleThumbInstruction (
|
||||
} else {
|
||||
Target = PCAlign4 (PC) + Target;
|
||||
}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
|
||||
return;
|
||||
|
||||
case CMN_THUMB2:
|
||||
// CMN <Rn>, #<const>}
|
||||
Target = (OpCode32 & 0xff) | ((OpCode >> 4) && 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);
|
||||
return;
|
||||
|
||||
case BFC_THUMB2:
|
||||
@@ -944,11 +944,11 @@ DisassembleThumbInstruction (
|
||||
lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
|
||||
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
|
||||
// BFC <Rd>, #<lsb>, #<width>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
|
||||
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
|
||||
} else {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
|
||||
}
|
||||
return;
|
||||
|
||||
@@ -977,7 +977,7 @@ DisassembleThumbInstruction (
|
||||
if (opc2 != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
|
||||
}
|
||||
return;
|
||||
return;
|
||||
|
||||
case MRRC_THUMB2:
|
||||
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
|
||||
@@ -986,7 +986,7 @@ DisassembleThumbInstruction (
|
||||
CRn = (OpCode32 >> 16) & 0xf;
|
||||
CRm = OpCode32 & 0xf;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);
|
||||
return;
|
||||
return;
|
||||
|
||||
case THUMB2_2REGS:
|
||||
// <Rd>, <Rm>
|
||||
@@ -1002,7 +1002,7 @@ DisassembleThumbInstruction (
|
||||
// MRS <Rd>, CPSR
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);
|
||||
return;
|
||||
|
||||
|
||||
case THUMB2_MSR:
|
||||
// MRS CPSR_<fields>, <Rd>
|
||||
Target = (OpCode32 >> 10) & 3;
|
||||
@@ -1031,19 +1031,19 @@ DisassembleArmInstruction (
|
||||
|
||||
|
||||
/**
|
||||
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
|
||||
point to next instructin.
|
||||
|
||||
We cheat and only decode instructions that access
|
||||
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
|
||||
point to next instructin.
|
||||
|
||||
We cheat and only decode instructions that access
|
||||
memory. If the instruction is not found we dump the instruction in hex.
|
||||
|
||||
@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
|
||||
|
||||
@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
|
||||
@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
|
||||
@param Extended TRUE dump hex for instruction too.
|
||||
@param ItBlock Size of IT Block
|
||||
@param Buf Buffer to sprintf disassembly into.
|
||||
@param Size Size of Buf in bytes.
|
||||
|
||||
@param Size Size of Buf in bytes.
|
||||
|
||||
**/
|
||||
VOID
|
||||
DisassembleInstruction (
|
||||
@@ -1061,4 +1061,4 @@ DisassembleInstruction (
|
||||
DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user