sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM Packages: Removed trailing spaces

Browse Source 
Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ronald Cron
2014-08-19 13:29:52 +00:00
committed by oliviermartin
parent 62d441fb17
commit 3402aac7d9
554 changed files with 6333 additions and 6345 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
View File

@@ -28,7 +28,7 @@
Arm9Support.S | GCC
Arm9Support.asm | RVCT
Arm9Lib.c
Arm9CacheInformation.c
@@ -38,7 +38,7 @@
[LibraryClasses]
MemoryAllocationLib
[Protocols]
gEfiCpuArchProtocolGuid

2
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
View File

@@ -28,7 +28,7 @@
Arm9Support.S | GCC
Arm9Support.asm | RVCT
Arm9Lib.c
Arm9CacheInformation.c

22
ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
View File

@@ -56,7 +56,7 @@ ArmDataCachePresent (
default: return FALSE;
}
}
UINTN
EFIAPI
ArmDataCacheSize (
@@ -65,16 +65,16 @@ ArmDataCacheSize (
{
switch (DATA_CACHE_SIZE (ArmCacheInfo ()))
{
case CACHE_SIZE_4_KB: return 4 * 1024;
case CACHE_SIZE_4_KB: return 4 * 1024;
case CACHE_SIZE_8_KB: return 8 * 1024;
case CACHE_SIZE_16_KB: return 16 * 1024;
case CACHE_SIZE_16_KB: return 16 * 1024;
case CACHE_SIZE_32_KB: return 32 * 1024;
case CACHE_SIZE_64_KB: return 64 * 1024;
case CACHE_SIZE_128_KB: return 128 * 1024;
default: return 0;
}
}
UINTN
EFIAPI
ArmDataCacheAssociativity (
@@ -88,7 +88,7 @@ ArmDataCacheAssociativity (
default: return 0;
}
}
UINTN
EFIAPI
ArmDataCacheLineLength (
@@ -101,7 +101,7 @@ ArmDataCacheLineLength (
default: return 0;
}
}
BOOLEAN
EFIAPI
ArmInstructionCachePresent (
@@ -115,7 +115,7 @@ ArmInstructionCachePresent (
default: return FALSE;
}
}
UINTN
EFIAPI
ArmInstructionCacheSize (
@@ -124,16 +124,16 @@ ArmInstructionCacheSize (
{
switch (INSTRUCTION_CACHE_SIZE (ArmCacheInfo ()))
{
case CACHE_SIZE_4_KB: return 4 * 1024;
case CACHE_SIZE_4_KB: return 4 * 1024;
case CACHE_SIZE_8_KB: return 8 * 1024;
case CACHE_SIZE_16_KB: return 16 * 1024;
case CACHE_SIZE_16_KB: return 16 * 1024;
case CACHE_SIZE_32_KB: return 32 * 1024;
case CACHE_SIZE_64_KB: return 64 * 1024;
case CACHE_SIZE_128_KB: return 128 * 1024;
default: return 0;
}
}
UINTN
EFIAPI
ArmInstructionCacheAssociativity (
@@ -148,7 +148,7 @@ ArmInstructionCacheAssociativity (
default: return 0;
}
}
UINTN
EFIAPI
ArmInstructionCacheLineLength (

16
ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
View File

@@ -2,7 +2,7 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -30,7 +30,7 @@ FillTranslationTable (
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
@@ -49,13 +49,13 @@ FillTranslationTable (
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
break;
}
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
// The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
for (Index = 0; Index < Sections; Index++)
{
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
@@ -83,7 +83,7 @@ ArmConfigureMmu (
if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
@@ -108,7 +108,7 @@ ArmConfigureMmu (
}
ArmSetTTBR0(TranslationTable);
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
@@ -125,7 +125,7 @@ ArmConfigureMmu (
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();

20
ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
View File

@@ -1,4 +1,4 @@
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
#
@@ -41,11 +41,11 @@ GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
#------------------------------------------------------------------------------
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
@@ -58,17 +58,17 @@ ASM_PFX(ArmEnableInstructionCache):
orr r0,r0,r1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
bic r0,r0,r1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmInvalidateInstructionCache):
mov r0,#0
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
@Also flushes the branch target cache.
mov r0,#0
mcr p15,0,r0,c7,c10,4 @Data write buffer
@@ -99,7 +99,7 @@ ASM_PFX(ArmEnableDataCache):
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@@ -113,7 +113,7 @@ ASM_PFX(ArmCleanDataCache):
mov R0,#0
mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmInvalidateDataCache):
mov R0,#0
mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
@@ -138,12 +138,12 @@ ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?

16
ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
View File

@@ -1,4 +1,4 @@
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
@@ -41,12 +41,12 @@ IC_ON EQU ( 0x1:SHL:12 )
ArmInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
BX lr
ArmCleanDataCacheEntryByMVA
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
BX lr
@@ -60,7 +60,7 @@ ArmEnableInstructionCache
ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
@@ -100,7 +100,7 @@ ArmEnableDataCache
ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
@@ -121,7 +121,7 @@ ArmInvalidateDataCache
MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmCleanInvalidateDataCache
MRC p15,0,r15,c7,c14,3
BNE ArmCleanInvalidateDataCache
@@ -139,12 +139,12 @@ ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
bx LR
ASM_PFX(ArmInstructionSynchronizationBarrier):
MOV R0, #0
MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct