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ARM Packages: Removed trailing spaces

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Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ronald Cron
2014-08-19 13:29:52 +00:00
committed by oliviermartin
parent 62d441fb17
commit 3402aac7d9
554 changed files with 6333 additions and 6345 deletions
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28
ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
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@@ -1,6 +1,6 @@
/** @file
PEI Services Table Pointer Library.
This library is used for PEIM which does executed from flash device directly but
executed in memory.
@@ -22,13 +22,13 @@
#include <Library/PcdLib.h>
/**
Caches a pointer PEI Services Table.
Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
Caches a pointer PEI Services Table.
Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
in a platform specific manner.
If PeiServicesTablePointer is NULL, then ASSERT().
@param PeiServicesTablePointer The address of PeiServices pointer.
**/
VOID
@@ -45,10 +45,10 @@ SetPeiServicesTablePointer (
/**
Retrieves the cached value of the PEI Services Table pointer.
Returns the cached value of the PEI Services Table pointer in a CPU specific manner
as specified in the CPU binding section of the Platform Initialization Pre-EFI
Returns the cached value of the PEI Services Table pointer in a CPU specific manner
as specified in the CPU binding section of the Platform Initialization Pre-EFI
Initialization Core Interface Specification.
If the cached PEI Services Table pointer is NULL, then ASSERT().
@return The pointer to PeiServices.
@@ -68,16 +68,16 @@ GetPeiServicesTablePointer (
}
/**
Perform CPU specific actions required to migrate the PEI Services Table
Perform CPU specific actions required to migrate the PEI Services Table
pointer from temporary RAM to permanent RAM.
For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
immediately preceding the Interrupt Descriptor Table (IDT) in memory.
For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
immediately preceding the Interrupt Descriptor Table (IDT) in memory.
For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
a dedicated CPU register. This means that there is no memory storage
associated with storing the PEI Services Table pointer, so no additional
a dedicated CPU register. This means that there is no memory storage
associated with storing the PEI Services Table pointer, so no additional
migration actions are required for Itanium or ARM CPUs.
**/