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ARM Packages: Removed trailing spaces

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Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ronald Cron
2014-08-19 13:29:52 +00:00
committed by oliviermartin
parent 62d441fb17
commit 3402aac7d9
554 changed files with 6333 additions and 6345 deletions
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34
BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm
View File

@@ -1,4 +1,4 @@
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
@@ -16,21 +16,21 @@
#include <Library/PcdLib.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
IMPORT CEntryPoint
EXPORT _ModuleEntryPoint
PRESERVE8
AREA ModuleEntryPoint, CODE, READONLY
_ModuleEntryPoint
//Disable L2 cache
mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
bic r0, r0, #0x00000002 // disable L2 cache
mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
//Enable Strict alignment checking & Instruction cache
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
@@ -38,14 +38,14 @@ _ModuleEntryPoint
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
mcr p15, 0, r0, c1, c0, 0
// Enable NEON register in case folks want to use them for optimizations (CopyMem)
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
mcr p15, 0, r0, c1, c0, 2
mov r0, #0x40000000 // Set EN bit in FPEXC
msr FPEXC,r0
// Set CPU vectors to start of DRAM
LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
mcr p15, 0, r0, c12, c0, 0
@@ -59,16 +59,16 @@ FillVectors
adds r2, r2, #4
cmp r2, #32
bne FillVectors
/* before we call C code, lets setup the stack pointer in internal RAM */
stack_pointer_setup
//
// Set stack based on PCD values. Need to do it this way to make C code work
// when it runs from FLASH.
//
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3
// Set stack based on PCD values. Need to do it this way to make C code work
// when it runs from FLASH.
//
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3
add r4, r2, r3
//Enter SVC mode and set up SVC stack pointer
@@ -77,13 +77,13 @@ stack_pointer_setup
mov r13,r4
// Call C entry point
LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1
LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1
LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory start arg0
blx CEntryPoint // Assume C code is thumb
blx CEntryPoint // Assume C code is thumb
ShouldNeverGetHere
/* _CEntryPoint should never return */
b ShouldNeverGetHere
END