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ARM Packages: Removed trailing spaces

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Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ronald Cron
2014-08-19 13:29:52 +00:00
committed by oliviermartin
parent 62d441fb17
commit 3402aac7d9
554 changed files with 6333 additions and 6345 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
Omap35xxPkg/PciEmulation/PciEmulation.c
View File

@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -36,7 +36,7 @@ typedef struct {
#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
{
{
{ ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },
@@ -82,7 +82,7 @@ ConfigureUSBHost (
// Get the Power IC protocol
Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR (Status);
ASSERT_EFI_ERROR (Status);
// Power the USB PHY
Data = VAUX_DEV_GRP_P1;
@@ -91,7 +91,7 @@ ConfigureUSBHost (
Data = VAUX_DEDICATED_18V;
Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEDICATED), 1, &Data);
ASSERT_EFI_ERROR (Status);
ASSERT_EFI_ERROR (Status);
// Enable power to the USB hub
Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
@@ -150,7 +150,7 @@ PciIoMemRead (
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
Count,
@@ -170,7 +170,7 @@ PciIoMemWrite (
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
Count,
@@ -217,11 +217,11 @@ PciIoPciRead (
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Count,
TRUE,
(PTR)(UINTN)Buffer,
TRUE,
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
Count,
TRUE,
(PTR)(UINTN)Buffer,
TRUE,
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)
);
}
@@ -237,11 +237,11 @@ PciIoPciWrite (
{
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Count,
TRUE,
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
TRUE,
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
Count,
TRUE,
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
TRUE,
(PTR)(UINTN)Buffer
);
}
@@ -385,7 +385,7 @@ PciIoAttributes (
case EfiPciIoAttributeOperationDisable:
// Since we are not a real PCI device no enable/set or disable operations exist.
return EFI_SUCCESS;
default:
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
@@ -418,7 +418,7 @@ PciIoSetBarAttributes (
return EFI_UNSUPPORTED;
}
EFI_PCI_IO_PROTOCOL PciIoTemplate =
EFI_PCI_IO_PROTOCOL PciIoTemplate =
{
PciIoPollMem,
PciIoPollIo,
@@ -463,7 +463,7 @@ PciEmulationEntryPoint (
Status = EFI_OUT_OF_RESOURCES;
return Status;
}
Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE; // Get the USB capability register base
@@ -504,7 +504,7 @@ PciEmulationEntryPoint (
// Unique device path.
CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));
Private->DevicePath.AcpiDevicePath.UID = 0;
// Copy protocol structure
CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));

16
Omap35xxPkg/PciEmulation/PciEmulation.h
View File

@@ -72,7 +72,7 @@ typedef struct {
EFI_HANDLE Handle;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
UINT8 StartBus;
UINT8 EndBus;
UINT16 Type;
@@ -81,7 +81,7 @@ typedef struct {
UINTN IoOffset;
UINT32 IoStart;
UINT32 IoSize;
UINT64 PciAttributes;
UINT64 PciAttributes;
ACPI_CONFIG_INFO *Config;
@@ -104,7 +104,7 @@ typedef union {
EFI_STATUS
EFIAPI
PciRootBridgeIoPollMem (
PciRootBridgeIoPollMem (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
@@ -113,10 +113,10 @@ PciRootBridgeIoPollMem (
IN UINT64 Delay,
OUT UINT64 *Result
);
EFI_STATUS
EFIAPI
PciRootBridgeIoPollIo (
PciRootBridgeIoPollIo (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
@@ -125,7 +125,7 @@ PciRootBridgeIoPollIo (
IN UINT64 Delay,
OUT UINT64 *Result
);
EFI_STATUS
EFIAPI
PciRootBridgeIoMemRead (
@@ -253,8 +253,8 @@ PciRootBridgeIoSetAttributes (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
IN UINT64 Attributes,
IN OUT UINT64 *ResourceBase,
IN OUT UINT64 *ResourceLength
);
IN OUT UINT64 *ResourceLength
);
EFI_STATUS
EFIAPI

5
Omap35xxPkg/PciEmulation/PciEmulation.inf
View File

@@ -1,5 +1,5 @@
/** @file
Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
@@ -52,6 +52,5 @@
gEmbeddedExternalDeviceProtocolGuid
[Depex]
gEfiMetronomeArchProtocolGuid AND
gEfiMetronomeArchProtocolGuid AND
gEmbeddedExternalDeviceProtocolGuid

72
Omap35xxPkg/PciEmulation/PciRootBridgeIo.c
View File

@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -87,20 +87,20 @@ PciRootBridgeIoPciRW (
return EFI_SUCCESS;
}
/**
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
@@ -120,7 +120,7 @@ PciRootBridgeIoMemRead (
if ( Buffer == NULL ) {
return EFI_INVALID_PARAMETER;
}
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
if (!PciRootBridgeMemAddressValid (Private, Address)) {
@@ -153,30 +153,30 @@ PciRootBridgeIoMemRead (
case EfiPciWidthFillUint32:
case EfiPciWidthFillUint64:
return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
default:
break;
}
return EFI_INVALID_PARAMETER;
}
/**
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
@@ -196,7 +196,7 @@ PciRootBridgeIoMemWrite (
if ( Buffer == NULL ) {
return EFI_INVALID_PARAMETER;
}
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
if (!PciRootBridgeMemAddressValid (Private, Address)) {
@@ -217,7 +217,7 @@ PciRootBridgeIoMemWrite (
case EfiPciWidthUint32:
case EfiPciWidthUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
case EfiPciWidthFifoUint8:
case EfiPciWidthFifoUint16:
case EfiPciWidthFifoUint32:
@@ -229,7 +229,7 @@ PciRootBridgeIoMemWrite (
case EfiPciWidthFillUint32:
case EfiPciWidthFillUint64:
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
default:
break;
}
@@ -237,20 +237,20 @@ PciRootBridgeIoMemWrite (
return EFI_INVALID_PARAMETER;
}
/**
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
@@ -271,20 +271,20 @@ PciRootBridgeIoPciRead (
/**
/**
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Width Signifies the width of the memory operations.
@param Address The base address of the memory operations.
@param Address The base address of the memory operations.
@param Count The number of memory operations to perform.
@param Buffer For read operations, the destination buffer to store the results. For write
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
operations, the source buffer to write data from.
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
**/
EFI_STATUS
EFIAPI
@@ -299,7 +299,7 @@ PciRootBridgeIoPciWrite (
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
}
return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
}