UefiCpuPkg:Remove code to wakeup AP and relocate ap
After the code to load mtrr setting, set register table, handle APIC setting and Interrupt after INIT-SIPI-SIPI is moved, the InitializeCpuProcedure() only contains following code logic: 1.Bsp runs ExecuteFirstSmiInit(). 2.Bsp transfers AP to safe hlt-loop During S3 boot, since APs will be relocated to new safe buffer by the callback of gEdkiiEndOfS3ResumeGuid in PeiMpLib, Bsp doesn't need to transfer AP to safe hlt-loop any more. SmmRestoreCpu() in CpuS3 only needs to runs the ExecuteFirstSmiInit() on BSP. So remove code to wakeup AP by INIT-SIPI-SIPI and remove code to relocate ap to safe hlt-loop. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
This commit is contained in:
Dun Tan
mergify[bot]
@@ -1,189 +0,0 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; MpFuncs.nasm
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;
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; Abstract:
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;
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; This is the assembly code for Multi-processor S3 support
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;
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;-------------------------------------------------------------------------------
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%define VacantFlag 0x0
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%define NotVacantFlag 0xff
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%define LockLocation RendezvousFunnelProcEnd - RendezvousFunnelProcStart
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%define StackStartAddressLocation LockLocation + 0x8
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%define StackSizeLocation LockLocation + 0x10
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%define CProcedureLocation LockLocation + 0x18
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%define GdtrLocation LockLocation + 0x20
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%define IdtrLocation LockLocation + 0x2A
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%define BufferStartLocation LockLocation + 0x34
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%define Cr3OffsetLocation LockLocation + 0x38
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%define InitializeFloatingPointUnitsAddress LockLocation + 0x3C
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;-------------------------------------------------------------------------------------
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;RendezvousFunnelProc procedure follows. All APs execute their procedure. This
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;procedure serializes all the AP processors through an Init sequence. It must be
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;noted that APs arrive here very raw...ie: real mode, no stack.
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;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
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;IS IN MACHINE CODE.
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;-------------------------------------------------------------------------------------
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;RendezvousFunnelProc (&WakeUpBuffer,MemAddress);
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;text SEGMENT
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DEFAULT REL
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SECTION .text
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BITS 16
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global ASM_PFX(RendezvousFunnelProc)
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ASM_PFX(RendezvousFunnelProc):
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RendezvousFunnelProcStart:
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; At this point CS = 0x(vv00) and ip= 0x0.
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mov ax, cs
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mov ds, ax
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mov es, ax
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mov ss, ax
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xor ax, ax
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mov fs, ax
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mov gs, ax
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flat32Start:
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mov si, BufferStartLocation
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mov edx,dword [si] ; EDX is keeping the start address of wakeup buffer
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mov si, Cr3OffsetLocation
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mov ecx,dword [si] ; ECX is keeping the value of CR3
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mov si, GdtrLocation
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o32 lgdt [cs:si]
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mov si, IdtrLocation
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o32 lidt [cs:si]
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xor ax, ax
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mov ds, ax
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mov eax, cr0 ; Get control register 0
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or eax, 0x000000001 ; Set PE bit (bit #0)
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mov cr0, eax
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FLAT32_JUMP:
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a32 jmp dword 0x20:0x0
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BITS 32
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PMODE_ENTRY: ; protected mode entry point
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mov ax, 0x18
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o16 mov ds, ax
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o16 mov es, ax
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o16 mov fs, ax
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o16 mov gs, ax
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o16 mov ss, ax ; Flat mode setup.
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mov eax, cr4
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bts eax, 5
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mov cr4, eax
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mov cr3, ecx
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mov esi, edx ; Save wakeup buffer address
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mov ecx, 0xc0000080 ; EFER MSR number.
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rdmsr ; Read EFER.
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bts eax, 8 ; Set LME=1.
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wrmsr ; Write EFER.
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mov eax, cr0 ; Read CR0.
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bts eax, 31 ; Set PG=1.
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mov cr0, eax ; Write CR0.
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LONG_JUMP:
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a16 jmp dword 0x38:0x0
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BITS 64
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LongModeStart:
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mov ax, 0x30
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o16 mov ds, ax
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o16 mov es, ax
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o16 mov ss, ax
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mov edi, esi
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add edi, LockLocation
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mov al, NotVacantFlag
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TestLock:
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xchg byte [edi], al
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cmp al, NotVacantFlag
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jz TestLock
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ProgramStack:
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mov edi, esi
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add edi, StackSizeLocation
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mov rax, qword [edi]
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mov edi, esi
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add edi, StackStartAddressLocation
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add rax, qword [edi]
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mov rsp, rax
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mov qword [edi], rax
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Releaselock:
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mov al, VacantFlag
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mov edi, esi
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add edi, LockLocation
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xchg byte [edi], al
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;
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; Call assembly function to initialize FPU.
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;
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mov rax, qword [esi + InitializeFloatingPointUnitsAddress]
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sub rsp, 0x20
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call rax
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add rsp, 0x20
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;
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; Call C Function
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;
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mov edi, esi
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add edi, CProcedureLocation
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mov rax, qword [edi]
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test rax, rax
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jz GoToSleep
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sub rsp, 0x20
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call rax
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add rsp, 0x20
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GoToSleep:
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cli
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hlt
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jmp $-2
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RendezvousFunnelProcEnd:
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;-------------------------------------------------------------------------------------
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; AsmGetAddressMap (&AddressMap);
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;-------------------------------------------------------------------------------------
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; comments here for definition of address map
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global ASM_PFX(AsmGetAddressMap)
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ASM_PFX(AsmGetAddressMap):
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lea rax, [RendezvousFunnelProcStart]
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mov qword [rcx], rax
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mov qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcStart
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mov qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcStart
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mov qword [rcx+0x18], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
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mov qword [rcx+0x20], LongModeStart - RendezvousFunnelProcStart
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mov qword [rcx+0x28], LONG_JUMP - RendezvousFunnelProcStart
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ret
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@@ -1,7 +1,7 @@
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/** @file
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SMM CPU misc functions for x64 arch specific.
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Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2015 - 2024, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@@ -132,34 +132,6 @@ GetProtectedModeCS (
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return Index * 8;
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}
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/**
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Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.
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@param[in] ApHltLoopCode The address of the safe hlt-loop function.
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@param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.
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@param[in] NumberToFinishAddress Address of Semaphore of APs finish count.
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**/
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VOID
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TransferApToSafeState (
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IN UINTN ApHltLoopCode,
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IN UINTN TopOfStack,
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IN UINTN NumberToFinishAddress
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)
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{
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AsmDisablePaging64 (
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GetProtectedModeCS (),
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(UINT32)ApHltLoopCode,
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(UINT32)NumberToFinishAddress,
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0,
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(UINT32)TopOfStack
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);
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//
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// It should never reach here
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//
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ASSERT (FALSE);
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}
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/**
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Initialize the shadow stack related data structure.
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