ArmPkg: Remove RVCT support
RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
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Rebecca Cran
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@@ -1,296 +0,0 @@
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//------------------------------------------------------------------------------
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//
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// Use ARMv6 instruction to operate on a single stack
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//
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// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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// Copyright (c) 2014, ARM Limited. All rights reserved.<BR>
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// Copyright (c) 2016 HP Development Company, L.P.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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#include <Library/PcdLib.h>
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/*
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This is the stack constructed by the exception handler (low address to high address)
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# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
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Reg Offset
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=== ======
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R0 0x00 # stmfd SP!,{R0-R12}
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R1 0x04
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R2 0x08
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R3 0x0c
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R4 0x10
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R5 0x14
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R6 0x18
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R7 0x1c
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R8 0x20
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R9 0x24
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R10 0x28
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R11 0x2c
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R12 0x30
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SP 0x34 # reserved via subtraction 0x20 (32) from SP
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LR 0x38
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PC 0x3c
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CPSR 0x40
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DFSR 0x44
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DFAR 0x48
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IFSR 0x4c
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IFAR 0x50
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LR 0x54 # SVC Link register (we need to restore it)
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LR 0x58 # pushed by srsfd
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CPSR 0x5c
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*/
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EXPORT ExceptionHandlersStart
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EXPORT ExceptionHandlersEnd
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EXPORT CommonExceptionEntry
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EXPORT AsmCommonExceptionEntry
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IMPORT CommonCExceptionHandler
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PRESERVE8
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AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5
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//
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// This code gets copied to the ARM vector table
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// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
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//
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ExceptionHandlersStart
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Reset
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b ResetEntry
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UndefinedInstruction
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b UndefinedInstructionEntry
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SoftwareInterrupt
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b SoftwareInterruptEntry
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PrefetchAbort
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b PrefetchAbortEntry
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DataAbort
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b DataAbortEntry
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ReservedException
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b ReservedExceptionEntry
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Irq
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b IrqEntry
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Fiq
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b FiqEntry
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ResetEntry
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srsfd #0x13! ; Store return state on SVC stack
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; We are already in SVC mode
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stmfd SP!,{LR} ; Store the link register for the current mode
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sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} ; Store the register state
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mov R0,#0 ; ExceptionType
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ldr R1,CommonExceptionEntry
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bx R1
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UndefinedInstructionEntry
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sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
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srsfd #0x13! ; Store return state on SVC stack
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cps #0x13 ; Switch to SVC for common stack
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stmfd SP!,{LR} ; Store the link register for the current mode
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sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} ; Store the register state
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mov R0,#1 ; ExceptionType
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ldr R1,CommonExceptionEntry;
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bx R1
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SoftwareInterruptEntry
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srsfd #0x13! ; Store return state on SVC stack
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; We are already in SVC mode
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stmfd SP!,{LR} ; Store the link register for the current mode
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sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} ; Store the register state
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mov R0,#2 ; ExceptionType
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ldr R1,CommonExceptionEntry
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bx R1
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PrefetchAbortEntry
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sub LR,LR,#4
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srsfd #0x13! ; Store return state on SVC stack
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cps #0x13 ; Switch to SVC for common stack
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stmfd SP!,{LR} ; Store the link register for the current mode
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sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} ; Store the register state
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mov R0,#3 ; ExceptionType
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ldr R1,CommonExceptionEntry
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bx R1
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DataAbortEntry
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sub LR,LR,#8
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srsfd #0x13! ; Store return state on SVC stack
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cps #0x13 ; Switch to SVC for common stack
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stmfd SP!,{LR} ; Store the link register for the current mode
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sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} ; Store the register state
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mov R0,#4 ; ExceptionType
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ldr R1,CommonExceptionEntry
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bx R1
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ReservedExceptionEntry
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srsfd #0x13! ; Store return state on SVC stack
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cps #0x13 ; Switch to SVC for common stack
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stmfd SP!,{LR} ; Store the link register for the current mode
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sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} ; Store the register state
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mov R0,#5 ; ExceptionType
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ldr R1,CommonExceptionEntry
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bx R1
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IrqEntry
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sub LR,LR,#4
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srsfd #0x13! ; Store return state on SVC stack
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cps #0x13 ; Switch to SVC for common stack
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stmfd SP!,{LR} ; Store the link register for the current mode
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sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} ; Store the register state
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mov R0,#6 ; ExceptionType
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ldr R1,CommonExceptionEntry
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bx R1
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FiqEntry
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sub LR,LR,#4
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srsfd #0x13! ; Store return state on SVC stack
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cps #0x13 ; Switch to SVC for common stack
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stmfd SP!,{LR} ; Store the link register for the current mode
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sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} ; Store the register state
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; Since we have already switch to SVC R8_fiq - R12_fiq
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; never get used or saved
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mov R0,#7 ; ExceptionType
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ldr R1,CommonExceptionEntry
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bx R1
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//
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// This gets patched by the C code that patches in the vector table
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//
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CommonExceptionEntry
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dcd AsmCommonExceptionEntry
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ExceptionHandlersEnd
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//
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// This code runs from CpuDxe driver loaded address. It is patched into
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// CommonExceptionEntry.
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//
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AsmCommonExceptionEntry
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mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
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str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
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mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
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str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
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mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
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str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
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mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
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str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
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ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack
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str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
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add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
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and R3, R1, #0x1f ; Check CPSR to see if User or System Mode
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cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
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cmpne R3, #0x10 ;
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stmeqed R2, {lr}^ ; save unbanked lr
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; else
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stmneed R2, {lr} ; save SVC lr
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ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
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; Check to see if we have to adjust for Thumb entry
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sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) {
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cmp r4, #1 ; // UND & SVC have different LR adjust for Thumb
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bhi NoAdjustNeeded
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tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
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addne R5, R5, #2 ; PC += 2;
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strne R5,[SP,#0x58] ; Update LR value pushed by srsfd
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NoAdjustNeeded
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str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC
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add R1, SP, #0x60 ; We pushed 0x60 bytes on the stack
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str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP
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; R0 is ExceptionType
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mov R1,SP ; R1 is SystemContext
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#if (FixedPcdGet32(PcdVFPEnabled))
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vpush {d0-d15} ; save vstm registers in case they are used in optimizations
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#endif
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mov R4, SP ; Save current SP
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tst R4, #4
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subne SP, SP, #4 ; Adjust SP if not 8-byte aligned
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/*
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VOID
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EFIAPI
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CommonCExceptionHandler (
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IN EFI_EXCEPTION_TYPE ExceptionType, R0
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IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
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)
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*/
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blx CommonCExceptionHandler ; Call exception handler
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mov SP, R4 ; Restore SP
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#if (FixedPcdGet32(PcdVFPEnabled))
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vpop {d0-d15}
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#endif
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ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
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mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
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ldr R1, [SP, #0x44] ; Restore EFI_SYSTEM_CONTEXT_ARM.DFSR
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mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
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ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC
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str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored
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ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR
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str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored
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add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry
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add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
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and R1, R1, #0x1f ; Check to see if User or System Mode
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cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
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cmpne R1, #0x10 ;
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ldmeqed R2, {lr}^ ; restore unbanked lr
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; else
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ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}
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ldmfd SP!,{R0-R12} ; Restore general purpose registers
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; Exception handler can not change SP
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add SP,SP,#0x20 ; Clear out the remaining stack space
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ldmfd SP!,{LR} ; restore the link register for this context
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rfefd SP! ; return from exception via srsfd stack slot
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END
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