MdePkg/BaseLib: Add stack switch related definitions for IA32
The new definitions include two structures IA32_TASK_STATE_SEGMENT IA32_TSS_DESCRIPTOR two macros IA32_GDT_TYPE_TSS IA32_GDT_ALIGNMENT and one API VOID EFIAPI AsmWriteTr ( IN UINT16 Selector ); They're needed to setup task gate and interrupt stack table for stack switch. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
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@@ -6647,6 +6647,8 @@ typedef struct {
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#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E
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#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F
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#define IA32_GDT_TYPE_TSS 0x9
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#define IA32_GDT_ALIGNMENT 8
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#if defined (MDE_CPU_IA32)
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///
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@@ -6663,6 +6665,70 @@ typedef union {
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UINT64 Uint64;
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} IA32_IDT_GATE_DESCRIPTOR;
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#pragma pack (1)
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//
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// IA32 Task-State Segment Definition
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//
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typedef struct {
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UINT16 PreviousTaskLink;
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UINT16 Reserved_2;
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UINT32 ESP0;
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UINT16 SS0;
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UINT16 Reserved_10;
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UINT32 ESP1;
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UINT16 SS1;
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UINT16 Reserved_18;
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UINT32 ESP2;
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UINT16 SS2;
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UINT16 Reserved_26;
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UINT32 CR3;
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UINT32 EIP;
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UINT32 EFLAGS;
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UINT32 EAX;
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UINT32 ECX;
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UINT32 EDX;
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UINT32 EBX;
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UINT32 ESP;
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UINT32 EBP;
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UINT32 ESI;
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UINT32 EDI;
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UINT16 ES;
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UINT16 Reserved_74;
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UINT16 CS;
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UINT16 Reserved_78;
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UINT16 SS;
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UINT16 Reserved_82;
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UINT16 DS;
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UINT16 Reserved_86;
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UINT16 FS;
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UINT16 Reserved_90;
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UINT16 GS;
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UINT16 Reserved_94;
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UINT16 LDTSegmentSelector;
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UINT16 Reserved_98;
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UINT16 T;
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UINT16 IOMapBaseAddress;
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} IA32_TASK_STATE_SEGMENT;
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typedef union {
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struct {
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UINT32 LimitLow:16; ///< Segment Limit 15..00
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UINT32 BaseLow:16; ///< Base Address 15..00
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UINT32 BaseMid:8; ///< Base Address 23..16
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UINT32 Type:4; ///< Type (1 0 B 1)
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UINT32 Reserved_43:1; ///< 0
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UINT32 DPL:2; ///< Descriptor Privilege Level
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UINT32 P:1; ///< Segment Present
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UINT32 LimitHigh:4; ///< Segment Limit 19..16
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UINT32 AVL:1; ///< Available for use by system software
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UINT32 Reserved_52:2; ///< 0 0
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UINT32 G:1; ///< Granularity
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UINT32 BaseHigh:8; ///< Base Address 31..24
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} Bits;
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UINT64 Uint64;
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} IA32_TSS_DESCRIPTOR;
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#pragma pack ()
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#endif
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#if defined (MDE_CPU_X64)
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@@ -6685,6 +6751,46 @@ typedef union {
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} Uint128;
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} IA32_IDT_GATE_DESCRIPTOR;
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#pragma pack (1)
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//
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// IA32 Task-State Segment Definition
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//
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typedef struct {
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UINT32 Reserved_0;
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UINT64 RSP0;
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UINT64 RSP1;
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UINT64 RSP2;
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UINT64 Reserved_28;
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UINT64 IST[7];
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UINT64 Reserved_92;
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UINT16 Reserved_100;
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UINT16 IOMapBaseAddress;
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} IA32_TASK_STATE_SEGMENT;
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typedef union {
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struct {
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UINT32 LimitLow:16; ///< Segment Limit 15..00
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UINT32 BaseLow:16; ///< Base Address 15..00
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UINT32 BaseMidl:8; ///< Base Address 23..16
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UINT32 Type:4; ///< Type (1 0 B 1)
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UINT32 Reserved_43:1; ///< 0
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UINT32 DPL:2; ///< Descriptor Privilege Level
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UINT32 P:1; ///< Segment Present
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UINT32 LimitHigh:4; ///< Segment Limit 19..16
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UINT32 AVL:1; ///< Available for use by system software
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UINT32 Reserved_52:2; ///< 0 0
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UINT32 G:1; ///< Granularity
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UINT32 BaseMidh:8; ///< Base Address 31..24
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UINT32 BaseHigh:32; ///< Base Address 63..32
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UINT32 Reserved_96:32; ///< Reserved
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} Bits;
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struct {
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UINT64 Uint64;
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UINT64 Uint64_1;
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} Uint128;
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} IA32_TSS_DESCRIPTOR;
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#pragma pack ()
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#endif
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///
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@@ -8950,6 +9056,17 @@ AsmRdRand64 (
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OUT UINT64 *Rand
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);
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/**
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Load given selector into TR register
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@param[in] Selector Task segment selector
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**/
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VOID
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EFIAPI
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AsmWriteTr (
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IN UINT16 Selector
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);
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#endif
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#endif
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