PcAtChipsetPkg/PcRtc: Add two new PCD for RTC Index/Target registers

In certain HW implementation, the BIT7 of RTC Index register(0x70) is
for NMI sources enable/disable but the BIT7 of 0x70 cannot be read
before writing. Software which doesn't want to change the NMI sources
enable/disable setting can write to the alias register 0x74, through
which only BIT0 ~ BIT6 of 0x70 is modified.
So two new PCDs are added so that platform can have the flexibility
to change the default RTC register addresses from 0x70/0x71 to
0x74/0x75.
With the new PCDs added, it can also support special HW that provides
RTC storage in a different register pairs.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Ruiyu Ni
2018-05-25 16:29:48 +08:00
parent 5a57246eab
commit 36dd3c781e
5 changed files with 25 additions and 12 deletions

View File

@@ -1,7 +1,7 @@
/** @file
RTC Architectural Protocol GUID as defined in DxeCis 0.96.
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
This program and the accompanying materials
@@ -72,8 +72,8 @@ RtcRead (
IN UINT8 Address
)
{
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8) (Address | (UINT8) (IoRead8 (PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
return IoRead8 (PCAT_RTC_DATA_REGISTER);
IoWrite8 (PcdGet8 (PcdRtcIndexRegister), (UINT8) (Address | (UINT8) (IoRead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x80)));
return IoRead8 (PcdGet8 (PcdRtcTargetRegister));
}
/**
@@ -90,8 +90,8 @@ RtcWrite (
IN UINT8 Data
)
{
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8) (Address | (UINT8) (IoRead8 (PCAT_RTC_ADDRESS_REGISTER) & 0x80)));
IoWrite8 (PCAT_RTC_DATA_REGISTER, Data);
IoWrite8 (PcdGet8 (PcdRtcIndexRegister), (UINT8) (Address | (UINT8) (IoRead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x80)));
IoWrite8 (PcdGet8 (PcdRtcTargetRegister), Data);
}
/**