PcAtChipsetPkg/PcRtc: Add two new PCD for RTC Index/Target registers

In certain HW implementation, the BIT7 of RTC Index register(0x70) is
for NMI sources enable/disable but the BIT7 of 0x70 cannot be read
before writing. Software which doesn't want to change the NMI sources
enable/disable setting can write to the alias register 0x74, through
which only BIT0 ~ BIT6 of 0x70 is modified.
So two new PCDs are added so that platform can have the flexibility
to change the default RTC register addresses from 0x70/0x71 to
0x74/0x75.
With the new PCDs added, it can also support special HW that provides
RTC storage in a different register pairs.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf

@@ -4,7 +4,7 @@
 # This driver provides GetTime, SetTime, GetWakeupTime, SetWakeupTime services to Runtime Service Table.
 # It will install a tagging protocol with gEfiRealTimeClockArchProtocolGuid.
 #
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 # Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
 #
 # This program and the accompanying materials
@@ -77,6 +77,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout  ## CONSUMES
   gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear             ## CONSUMES
   gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear             ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister             ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister            ## CONSUMES
 
 [Depex]
   gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid