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UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttling

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Today's implementation only assumes SandyBridge CPU supports
Extended On-Demand Clock Modulation Duty Cycle.
Actually it is supported when CPUID.06h.EAX[5] == 1.

When platform requests 50% throttling, it causes value 1000b
set to the low-4 bits of IA32_CLOCK_MODULATION.
But the wrong code sets 1000b to bits[1-3] which causes assertion.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <vanjeff_919@hotmail.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
(cherry picked from commit 0c8b880223)
This commit is contained in:
Ruiyu Ni
2018-02-06 15:26:41 +08:00
parent 068b00d7da
commit 3885ffd841
1 changed files with 23 additions and 29 deletions
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52
UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
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@@ -1,7 +1,7 @@
/** @file /** @file
Clock Modulation feature. Clock Modulation feature.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@@ -67,40 +67,34 @@ ClockModulationInitialize (
IN BOOLEAN State IN BOOLEAN State
) )
{ {
if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax;
CPU_REGISTER_TABLE_WRITE_FIELD ( AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &ThermalPowerManagementEax.Uint32, NULL, NULL, NULL);
ProcessorNumber,
Msr, CPU_REGISTER_TABLE_WRITE_FIELD (
MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, ProcessorNumber,
MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER, Msr,
Bits.OnDemandClockModulationDutyCycle, MSR_IA32_CLOCK_MODULATION,
PcdGet8 (PcdCpuClockModulationDutyCycle) MSR_IA32_CLOCK_MODULATION_REGISTER,
); Bits.OnDemandClockModulationDutyCycle,
CPU_REGISTER_TABLE_WRITE_FIELD ( PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1
ProcessorNumber, );
Msr, if (ThermalPowerManagementEax.Bits.ECMD == 1) {
MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION,
MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER,
Bits.OnDemandClockModulationEnable,
(State) ? 1 : 0
);
} else {
CPU_REGISTER_TABLE_WRITE_FIELD ( CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
MSR_IA32_CLOCK_MODULATION, MSR_IA32_CLOCK_MODULATION,
MSR_IA32_CLOCK_MODULATION_REGISTER, MSR_IA32_CLOCK_MODULATION_REGISTER,
Bits.OnDemandClockModulationDutyCycle, Bits.ExtendedOnDemandClockModulationDutyCycle,
PcdGet8 (PcdCpuClockModulationDutyCycle) PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0
);
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_CLOCK_MODULATION,
MSR_IA32_CLOCK_MODULATION_REGISTER,
Bits.OnDemandClockModulationEnable,
(State) ? 1 : 0
); );
} }
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_CLOCK_MODULATION,
MSR_IA32_CLOCK_MODULATION_REGISTER,
Bits.OnDemandClockModulationEnable,
(State) ? 1 : 0
);
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }