sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

SecurityPkg/Tcg: Fix Warnings and Remarks reported by IASL

Browse Source 
Addressed warnings and remarks reported by IASL.EXE. Some methods had
unused arguments. A method was returning a value when it should not.

Cc: Zhang Chao B <chao.b.zhang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Thomas Rydman <thomas.j.rydman@intel.com>
Reviewed-by: Zhang Chao B <chao.b.zhang@intel.com>
This commit is contained in:
Zhang, Chao B
2018-12-24 13:16:01 +08:00
parent b5547b9ce9
commit 39699d078c
2 changed files with 82 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files

140
SecurityPkg/Tcg/Tcg2Smm/Tpm.asl
View File

@@ -160,68 +160,66 @@ DefinitionBlock (
// //
// Do not configure Interrupt if IRQ Num is configured 0 by default // Do not configure Interrupt if IRQ Num is configured 0 by default
// //
If (LEqual(IRQN, 0)) { If (LNotEqual(IRQN, 0)) {
Return (0) //
} // Update resource descriptor
// Use the field name to identify the offsets in the argument
// buffer and RES0 buffer.
//
CreateDWordField(Arg0, ^INTR._INT, IRQ0)
CreateDWordField(RES0, ^INTR._INT, LIRQ)
Store(IRQ0, LIRQ)
Store(IRQ0, IRQN)
// CreateBitField(Arg0, ^INTR._HE, ITRG)
// Update resource descriptor CreateBitField(RES0, ^INTR._HE, LTRG)
// Use the field name to identify the offsets in the argument Store(ITRG, LTRG)
// buffer and RES0 buffer.
//
CreateDWordField(Arg0, ^INTR._INT, IRQ0)
CreateDWordField(RES0, ^INTR._INT, LIRQ)
Store(IRQ0, LIRQ)
Store(IRQ0, IRQN)
CreateBitField(Arg0, ^INTR._HE, ITRG) CreateBitField(Arg0, ^INTR._LL, ILVL)
CreateBitField(RES0, ^INTR._HE, LTRG) CreateBitField(RES0, ^INTR._LL, LLVL)
Store(ITRG, LTRG) Store(ILVL, LLVL)
CreateBitField(Arg0, ^INTR._LL, ILVL)
CreateBitField(RES0, ^INTR._LL, LLVL)
Store(ILVL, LLVL)
//
// Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest
// nibble.
// 0000 - FIFO interface as defined in PTP for TPM 2.0 is active
// 1111 - FIFO interface as defined in TIS1.3 is active
//
If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {
// //
// If FIFO interface, interrupt vector register is // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest
// available. TCG PTP specification allows only // nibble.
// values 1..15 in this field. For other interrupts // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active
// the field should stay 0. // 1111 - FIFO interface as defined in TIS1.3 is active
// //
If (LLess (IRQ0, 16)) { If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {
Store (And(IRQ0, 0xF), INTV) //
} // If FIFO interface, interrupt vector register is
// // available. TCG PTP specification allows only
// Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4 // values 1..15 in this field. For other interrupts
// contains settings for interrupt polarity. // the field should stay 0.
// The other bits of the byte enable individual interrupts. //
// They should be all be zero, but to avoid changing the If (LLess (IRQ0, 16)) {
// configuration, the other bits are be preserved. Store (And(IRQ0, 0xF), INTV)
// 00 - high level }
// 01 - low level //
// 10 - rising edge // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4
// 11 - falling edge // contains settings for interrupt polarity.
// // The other bits of the byte enable individual interrupts.
// ACPI spec definitions: // They should be all be zero, but to avoid changing the
// _HE: '1' is Edge, '0' is Level // configuration, the other bits are be preserved.
// _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec) // 00 - high level
// // 01 - low level
If (LEqual (ITRG, 1)) { // 10 - rising edge
Or(INTE, 0x00000010, INTE) // 11 - falling edge
} Else { //
And(INTE, 0xFFFFFFEF, INTE) // ACPI spec definitions:
} // _HE: '1' is Edge, '0' is Level
if (LEqual (ILVL, 0)) { // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)
Or(INTE, 0x00000008, INTE) //
} Else { If (LEqual (ITRG, 1)) {
And(INTE, 0xFFFFFFF7, INTE) Or(INTE, 0x00000010, INTE)
} Else {
And(INTE, 0xFFFFFFEF, INTE)
}
if (LEqual (ILVL, 0)) {
Or(INTE, 0x00000008, INTE)
} Else {
And(INTE, 0xFFFFFFF7, INTE)
}
} }
} }
} }
@@ -284,12 +282,12 @@ DefinitionBlock (
// //
// TCG Hardware Information // TCG Hardware Information
// //
Method (HINF, 3, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj Method (HINF, 1, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj}) // IntObj
{ {
// //
// Switch by function index // Switch by function index
// //
Switch (ToInteger(Arg1)) Switch (ToInteger(Arg0))
{ {
Case (0) Case (0)
{ {
@@ -333,12 +331,12 @@ DefinitionBlock (
// //
// TCG Physical Presence Interface // TCG Physical Presence Interface
// //
Method (TPPI, 3, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj Method (TPPI, 2, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj}) // IntObj, PkgObj
{ {
// //
// Switch by function index // Switch by function index
// //
Switch (ToInteger(Arg1)) Switch (ToInteger(Arg0))
{ {
Case (0) Case (0)
{ {
@@ -360,7 +358,7 @@ DefinitionBlock (
// b) Submit TPM Operation Request to Pre-OS Environment // b) Submit TPM Operation Request to Pre-OS Environment
// //
Store (DerefOf (Index (Arg2, 0x00)), PPRQ) Store (DerefOf (Index (Arg1, 0x00)), PPRQ)
Store (0, PPRM) Store (0, PPRM)
Store (0x02, PPIP) Store (0x02, PPIP)
@@ -421,10 +419,10 @@ DefinitionBlock (
// g) Submit TPM Operation Request to Pre-OS Environment 2 // g) Submit TPM Operation Request to Pre-OS Environment 2
// //
Store (7, PPIP) Store (7, PPIP)
Store (DerefOf (Index (Arg2, 0x00)), PPRQ) Store (DerefOf (Index (Arg1, 0x00)), PPRQ)
Store (0, PPRM) Store (0, PPRM)
If (LEqual (PPRQ, 23)) { If (LEqual (PPRQ, 23)) {
Store (DerefOf (Index (Arg2, 0x01)), PPRM) Store (DerefOf (Index (Arg1, 0x01)), PPRM)
} }
// //
@@ -439,7 +437,7 @@ DefinitionBlock (
// e) Get User Confirmation Status for Operation // e) Get User Confirmation Status for Operation
// //
Store (8, PPIP) Store (8, PPIP)
Store (DerefOf (Index (Arg2, 0x00)), UCRQ) Store (DerefOf (Index (Arg1, 0x00)), UCRQ)
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
@@ -454,12 +452,12 @@ DefinitionBlock (
Return (1) Return (1)
} }
Method (TMCI, 3, Serialized, 0, IntObj, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj Method (TMCI, 2, Serialized, 0, IntObj, {UnknownObj, UnknownObj}) // IntObj, PkgObj
{ {
// //
// Switch by function index // Switch by function index
// //
Switch (ToInteger (Arg1)) Switch (ToInteger (Arg0))
{ {
Case (0) Case (0)
{ {
@@ -473,7 +471,7 @@ DefinitionBlock (
// //
// Save the Operation Value of the Request to MORD (reserved memory) // Save the Operation Value of the Request to MORD (reserved memory)
// //
Store (DerefOf (Index (Arg2, 0x00)), MORD) Store (DerefOf (Index (Arg1, 0x00)), MORD)
// //
// Trigger the SMI through ACPI _DSM method. // Trigger the SMI through ACPI _DSM method.
@@ -499,7 +497,7 @@ DefinitionBlock (
// //
If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))
{ {
Return (HINF (Arg1, Arg2, Arg3)) Return (HINF (Arg2))
} }
// //
@@ -507,7 +505,7 @@ DefinitionBlock (
// //
If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653"))) If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))
{ {
Return (TPPI (Arg1, Arg2, Arg3)) Return (TPPI (Arg2, Arg3))
} }
// //
@@ -515,7 +513,7 @@ DefinitionBlock (
// //
If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
{ {
Return (TMCI (Arg1, Arg2, Arg3)) Return (TMCI (Arg2, Arg3))
} }
Return (Buffer () {0}) Return (Buffer () {0})

26
SecurityPkg/Tcg/TcgSmm/Tpm.asl
View File

@@ -120,12 +120,12 @@ DefinitionBlock (
// //
// TCG Hardware Information // TCG Hardware Information
// //
Method (HINF, 3, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj Method (HINF, 1, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj}) // IntObj
{ {
// //
// Switch by function index // Switch by function index
// //
Switch (ToInteger(Arg1)) Switch (ToInteger(Arg0))
{ {
Case (0) Case (0)
{ {
@@ -169,12 +169,12 @@ DefinitionBlock (
// //
// TCG Physical Presence Interface // TCG Physical Presence Interface
// //
Method (TPPI, 3, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj Method (TPPI, 2, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj}) // IntObj, PkgObj
{ {
// //
// Switch by function index // Switch by function index
// //
Switch (ToInteger(Arg1)) Switch (ToInteger(Arg0))
{ {
Case (0) Case (0)
{ {
@@ -196,7 +196,7 @@ DefinitionBlock (
// b) Submit TPM Operation Request to Pre-OS Environment // b) Submit TPM Operation Request to Pre-OS Environment
// //
Store (DerefOf (Index (Arg2, 0x00)), PPRQ) Store (DerefOf (Index (Arg1, 0x00)), PPRQ)
Store (0x02, PPIP) Store (0x02, PPIP)
// //
@@ -256,7 +256,7 @@ DefinitionBlock (
// g) Submit TPM Operation Request to Pre-OS Environment 2 // g) Submit TPM Operation Request to Pre-OS Environment 2
// //
Store (7, PPIP) Store (7, PPIP)
Store (DerefOf (Index (Arg2, 0x00)), PPRQ) Store (DerefOf (Index (Arg1, 0x00)), PPRQ)
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
@@ -270,7 +270,7 @@ DefinitionBlock (
// e) Get User Confirmation Status for Operation // e) Get User Confirmation Status for Operation
// //
Store (8, PPIP) Store (8, PPIP)
Store (DerefOf (Index (Arg2, 0x00)), UCRQ) Store (DerefOf (Index (Arg1, 0x00)), UCRQ)
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
@@ -285,12 +285,12 @@ DefinitionBlock (
Return (1) Return (1)
} }
Method (TMCI, 3, Serialized, 0, IntObj, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj Method (TMCI, 2, Serialized, 0, IntObj, {UnknownObj, UnknownObj}) // IntObj, PkgObj
{ {
// //
// Switch by function index // Switch by function index
// //
Switch (ToInteger (Arg1)) Switch (ToInteger (Arg0))
{ {
Case (0) Case (0)
{ {
@@ -304,7 +304,7 @@ DefinitionBlock (
// //
// Save the Operation Value of the Request to MORD (reserved memory) // Save the Operation Value of the Request to MORD (reserved memory)
// //
Store (DerefOf (Index (Arg2, 0x00)), MORD) Store (DerefOf (Index (Arg1, 0x00)), MORD)
// //
// Trigger the SMI through ACPI _DSM method. // Trigger the SMI through ACPI _DSM method.
@@ -330,7 +330,7 @@ DefinitionBlock (
// //
If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))
{ {
Return (HINF (Arg1, Arg2, Arg3)) Return (HINF (Arg2))
} }
// //
@@ -338,7 +338,7 @@ DefinitionBlock (
// //
If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653"))) If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))
{ {
Return (TPPI (Arg1, Arg2, Arg3)) Return (TPPI (Arg2, Arg3))
} }
// //
@@ -346,7 +346,7 @@ DefinitionBlock (
// //
If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
{ {
Return (TMCI (Arg1, Arg2, Arg3)) Return (TMCI (Arg2, Arg3))
} }
Return (Buffer () {0}) Return (Buffer () {0})