Add dual FSP binaries support.

There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version)
TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version.

Also update FSP specification version to v1.1.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17248 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ma, Maurice
2015-04-29 03:10:24 +00:00
committed by jyao1
parent 2bf87d82e9
commit 3b17b24587
12 changed files with 115 additions and 31 deletions

View File

@@ -38,8 +38,9 @@ EXTERN FspApiCallingCheck:PROC
; Following functions will be provided in PlatformSecLib
;
EXTERN GetFspBaseAddress:PROC
EXTERN GetFspInfoHdr:PROC
EXTERN GetBootFirmwareVolumeOffset:PROC
EXTERN Pei2LoaderSwitchStack:PROC
EXTERN Loader2PeiSwitchStack:PROC
EXTERN LoadMicrocode(LoadMicrocodeDefault):PROC
EXTERN SecPlatformInit(SecPlatformInitDefault):PROC
EXTERN SecCarInit:PROC
@@ -370,8 +371,7 @@ TempRamInitApi PROC NEAR PUBLIC
jz NemInitExit
;
; CPUID/DeviceID check
; and Sec Platform Init
; Sec Platform Init
;
CALL_MMX SecPlatformInit
cmp eax, 0
@@ -505,7 +505,9 @@ FspApiCommon PROC C PUBLIC
jz @F
cmp eax, 3 ; FspMemoryInit API
jz @F
jmp Pei2LoaderSwitchStack
call GetFspInfoHdr
jmp Loader2PeiSwitchStack
@@:
;
@@ -513,9 +515,17 @@ FspApiCommon PROC C PUBLIC
;
;
; Store the address in FSP which will return control to the BL
; Place holder to store the FspInfoHeader pointer
;
push offset exit
push eax
;
; Update the FspInfoHeader pointer
;
push eax
call GetFspInfoHdr
mov [esp + 4], eax
pop eax
;
; Create a Task Frame in the stack for the Boot Loader
@@ -582,7 +592,7 @@ FspApiCommon PROC C PUBLIC
; Pass Control into the PEI Core
;
call SecStartup
add esp, 4
exit:
ret