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IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.Limit

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According to VTd spec, the real hardware decoded limit should be
PHMR/PLMR.Limit value + alignment value.

"Bits N:0 of the limit register are
decoded by hardware as all 1s."

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
(cherry picked from commit e8097a74b7)
This commit is contained in:
Star Zeng
2018-01-16 16:41:42 +08:00
parent b6da5e3823
commit 3c8012fff3
1 changed files with 3 additions and 3 deletions
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6
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
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@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License which accompanies this distribution.
@@ -60,7 +60,7 @@ typedef struct {
PEI Memory Layout:
+------------------+ <=============== PHMR.Limit (Top of memory)
+------------------+ <=============== PHMR.Limit (+ alignment) (Top of memory)
| Mem Resource |
| |
@@ -72,7 +72,7 @@ typedef struct {
DMA Buffer | * DMA FREE * |
| | -------------- |
V | Read/Write Buf |
=========== +==================+ <=============== PLMR.Limit
=========== +==================+ <=============== PLMR.Limit (+ alignment)
| PEI allocated |
| -------------- | <------- EfiFreeMemoryTop
| * PEI FREE * |