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MdePkg: Removing ipf which is no longer supported from edk2.

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Removing rules for Ipf sources file:
* Remove the source file which path with "ipf" and also listed in
  [Sources.IPF] section of INF file.
* Remove the source file which listed in [Components.IPF] section
  of DSC file and not listed in any other [Components] section.
* Remove the embedded Ipf code for MDE_CPU_IPF.

Removing rules for Inf file:
* Remove IPF from VALID_ARCHITECTURES comments.
* Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section.
* Remove the INF which only listed in [Components.IPF] section in DSC.
* Remove statements from [BuildOptions] that provide IPF specific flags.
* Remove any IPF sepcific sections.

Removing rules for Dec file:
* Remove [Includes.IPF] section from Dec.

Removing rules for Dsc file:
* Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC.
* Remove any IPF specific sections.
* Remove statements from [BuildOptions] that provide IPF specific flags.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chen A Chen <chen.a.chen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Chen A Chen
2018-07-02 09:21:05 +08:00
committed by Zhang, Chao B
parent ba6037f833
commit 3cb0a311cb
182 changed files with 152 additions and 19402 deletions
Download Patch File Download Diff File Expand all files Collapse all files

58
MdePkg/Include/Ipf/IpfMacro.i
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@ -1,58 +0,0 @@
// @file
// Contains the macros required by calling procedures in Itanium-based assembly code.
//
// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
#ifndef __IA64PROC_I__
#define __IA64PROC_I__
//
// Delcare the begin of assembly function entry.
//
// @param name Name of function in assembly code.
//
#define PROCEDURE_ENTRY(name) .##text; \
.##type name, @function; \
.##proc name; \
name::
//
// End of assembly function.
//
// @param name Name of function in assembly code.
//
#define PROCEDURE_EXIT(name) .##endp name
//
// NESTED_SETUP Requires number of locals (l) >= 3
//
#define NESTED_SETUP(i,l,o,r) \
alloc loc1=ar##.##pfs,i,l,o,r ;\
mov loc0=b0
//
// End of Nested
//
#define NESTED_RETURN \
mov b0=loc0 ;\
mov ar##.##pfs=loc1 ;;\
br##.##ret##.##dpnt b0;;
//
// Export assembly function as the global function.
//
// @param Function Name of function in assembly code.
//
#define GLOBAL_FUNCTION(Function) \
.##type Function, @function; \
.##globl Function
#endif

324
MdePkg/Include/Ipf/ProcessorBind.h
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@ -1,324 +0,0 @@
/** @file
Processor or Compiler specific defines and types for Intel Itanium(TM) processors.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __PROCESSOR_BIND_H__
#define __PROCESSOR_BIND_H__
///
/// Define the processor type so other code can make processor-based choices.
///
#define MDE_CPU_IPF
//
// Make sure we are using the correct packing rules per EFI specification
//
#pragma pack()
#if defined(__INTEL_COMPILER)
//
// Disable ICC's remark #869: "Parameter" was never referenced warning.
// This is legal ANSI C code so we disable the remark that is turned on with -Wall
//
#pragma warning ( disable : 869 )
//
// Disable ICC's remark #1418: external function definition with no prior declaration.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 1418 )
//
// Disable ICC's remark #1419: external declaration in primary source file
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 1419 )
//
// Disable ICC's remark #593: "Variable" was set but never used.
// This is legal ANSI C code so we disable the remark that is turned on with /W4
//
#pragma warning ( disable : 593 )
#endif
#if defined(_MSC_EXTENSIONS)
//
// Disable warning that make it impossible to compile at /W4
// This only works for Microsoft* tools
//
//
// Disabling bitfield type checking warnings.
//
#pragma warning ( disable : 4214 )
//
// Disabling the unreferenced formal parameter warnings.
//
#pragma warning ( disable : 4100 )
//
// Disable slightly different base types warning as CHAR8 * can not be set
// to a constant string.
//
#pragma warning ( disable : 4057 )
//
// Disable warning on conversion from function pointer to a data pointer
//
#pragma warning ( disable : 4054 )
//
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
//
#pragma warning ( disable : 4127 )
//
// Can not cast a function pointer to a data pointer. We need to do this on
// Itanium processors to get access to the PLABEL.
//
#pragma warning ( disable : 4514 )
//
// This warning is caused by functions defined but not used. For precompiled header only.
//
#pragma warning ( disable : 4505 )
//
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
//
#pragma warning ( disable : 4206 )
#endif
#if defined(_MSC_EXTENSIONS)
//
// use Microsoft C compiler dependent integer width types
//
///
/// 8-byte unsigned value.
///
typedef unsigned __int64 UINT64;
///
/// 8-byte signed value.
///
typedef __int64 INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned __int32 UINT32;
///
/// 4-byte signed value.
///
typedef __int32 INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character.
///
typedef char CHAR8;
///
/// 1-byte signed value.
///
typedef signed char INT8;
#else
///
/// 8-byte unsigned value.
///
typedef unsigned long long UINT64;
///
/// 8-byte signed value.
///
typedef long long INT64;
///
/// 4-byte unsigned value.
///
typedef unsigned int UINT32;
///
/// 4-byte signed value.
///
typedef int INT32;
///
/// 2-byte unsigned value.
///
typedef unsigned short UINT16;
///
/// 2-byte Character. Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short CHAR16;
///
/// 2-byte signed value.
///
typedef short INT16;
///
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
/// values are undefined.
///
typedef unsigned char BOOLEAN;
///
/// 1-byte unsigned value.
///
typedef unsigned char UINT8;
///
/// 1-byte Character.
///
typedef char CHAR8;
///
/// 1-byte signed value.
///
typedef signed char INT8;
#endif
///
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions.)
///
typedef UINT64 UINTN;
///
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions;
/// 8 bytes on supported 64-bit processor instructions.)
///
typedef INT64 INTN;
//
// Processor specific defines
//
///
/// A value of native width with the highest bit set.
///
#define MAX_BIT 0x8000000000000000ULL
///
/// A value of native width with the two highest bits set.
///
#define MAX_2_BITS 0xC000000000000000ULL
///
/// The maximum legal Itanium-based address
///
#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
///
/// Maximum legal Itanium-based INTN and UINTN values.
///
#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
///
/// Minimum legal Itanium-based INTN value.
///
#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)
///
/// Per the Itanium Software Conventions and Runtime Architecture Guide,
/// section 3.3.4, IPF stack must always be 16-byte aligned.
///
#define CPU_STACK_ALIGNMENT 16
///
/// Page allocation granularity for Itanium
///
#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x2000)
//
// Modifier to ensure that all protocol member functions and EFI intrinsics
// use the correct C calling convention. All protocol member functions and
// EFI intrinsics are required to modify their member functions with EFIAPI.
//
#ifdef EFIAPI
///
/// If EFIAPI is already defined, then we use that definition.
///
#elif defined(_MSC_EXTENSIONS)
///
/// Microsoft* compiler-specific method for EFIAPI calling convention.
///
#define EFIAPI __cdecl
#else
#define EFIAPI
#endif
///
/// For GNU assembly code, .global or .globl can declare global symbols.
/// Define this macro to unify the usage.
///
#define ASM_GLOBAL .globl
///
/// A pointer to a function in IPF points to a plabel.
///
typedef struct {
UINT64 EntryPoint;
UINT64 GP;
} EFI_PLABEL;
///
/// PAL Call return structure.
///
typedef struct {
UINT64 Status;
UINT64 r9;
UINT64 r10;
UINT64 r11;
} PAL_CALL_RETURN;
/**
Return the pointer to the first instruction of a function given a function pointer.
For Itanium processors, all function calls are made through a PLABEL, so a pointer to a function
is actually a pointer to a PLABEL. The pointer to the first instruction of the function
is contained within the PLABEL. This macro may be used to retrieve a pointer to the first
instruction of a function independent of the CPU architecture being used. This is very
useful when printing function addresses through DEBUG() macros.
@param FunctionPointer A pointer to a function.
@return The pointer to the first instruction of a function given a function pointer.
**/
#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(((EFI_PLABEL *)(FunctionPointer))->EntryPoint)
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#endif

1442
MdePkg/Include/Library/BaseLib.h
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File diff suppressed because it is too large Load Diff

2
MdePkg/Include/Protocol/PxeBaseCode.h
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@ -153,8 +153,6 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
//
#if defined (MDE_CPU_IA32)
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0006
#elif defined (MDE_CPU_IPF)
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0002
#elif defined (MDE_CPU_X64)
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0007
#elif defined (MDE_CPU_ARM)

7
MdePkg/Include/Uefi/UefiBaseType.h
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@ -254,13 +254,6 @@ typedef union {
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)
#elif defined (MDE_CPU_IPF)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
(((Machine) == EFI_IMAGE_MACHINE_IA64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
#elif defined (MDE_CPU_X64)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \

2
MdePkg/Include/Uefi/UefiSpec.h
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@ -2190,8 +2190,6 @@ typedef struct {
#if defined (MDE_CPU_IA32)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
#elif defined (MDE_CPU_IPF)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA64
#elif defined (MDE_CPU_X64)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64
#elif defined (MDE_CPU_EBC)

8
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
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@ -28,7 +28,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources.IA32]
@ -37,9 +37,6 @@
[Sources.X64]
X86Cache.c
[Sources.IPF]
IpfCache.c
[Sources.EBC]
EbcCache.c
@ -56,6 +53,3 @@
BaseLib
DebugLib
[LibraryClasses.Ipf]
PalLib

242
MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
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@ -1,242 +0,0 @@
/** @file
Cache Maintenance Functions.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PalLib.h>
/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
**/
VOID
EFIAPI
InvalidateInstructionCache (
VOID
)
{
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
}
/**
Invalidates a range of instruction cache lines in the cache coherency domain
of the calling CPU.
Invalidates the instruction cache lines specified by Address and Length. If
Address is not aligned on a cache line boundary, then entire instruction
cache line containing Address is invalidated. If Address + Length is not
aligned on a cache line boundary, then the entire instruction cache line
containing Address + Length -1 is invalidated. This function may choose to
invalidate the entire instruction cache if that is more efficient than
invalidating the specified range. If Length is 0, then no instruction cache
lines are invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address.
**/
VOID *
EFIAPI
InvalidateInstructionCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return AsmFlushCacheRange (Address, Length);
}
/**
Writes back and invalidates the entire data cache in cache coherency domain
of the calling CPU.
Writes back and invalidates the entire data cache in cache coherency domain
of the calling CPU. This function guarantees that all dirty cache lines are
written back to system memory, and also invalidates all the data cache lines
in the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackInvalidateDataCache (
VOID
)
{
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
}
/**
Writes back and invalidates a range of data cache lines in the cache
coherency domain of the calling CPU.
Writes back and invalidates the data cache lines specified by Address and
Length. If Address is not aligned on a cache line boundary, then entire data
cache line containing Address is written back and invalidated. If Address +
Length is not aligned on a cache line boundary, then the entire data cache
line containing Address + Length -1 is written back and invalidated. This
function may choose to write back and invalidate the entire data cache if
that is more efficient than writing back and invalidating the specified
range. If Length is 0, then no data cache lines are written back and
invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back and
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to write back and invalidate from the
data cache.
@return Address of cache invalidation.
**/
VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return AsmFlushCacheRange (Address, Length);
}
/**
Writes Back the entire data cache in cache coherency domain of the calling
CPU.
Writes Back the entire data cache in cache coherency domain of the calling
CPU. This function guarantees that all dirty cache lines are written back to
system memory. This function may also invalidate all the data cache lines in
the cache coherency domain of the calling CPU.
**/
VOID
EFIAPI
WriteBackDataCache (
VOID
)
{
PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
}
/**
Writes Back a range of data cache lines in the cache coherency domain of the
calling CPU.
Writes Back the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is written back. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is written back. This function may choose to write back the entire
data cache if that is more efficient than writing back the specified range.
If Length is 0, then no data cache lines are written back. This function may
also invalidate all the data cache lines in the specified range of the cache
coherency domain of the calling CPU. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing
mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache.
@return Address of cache written in main memory.
**/
VOID *
EFIAPI
WriteBackDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
return AsmFlushCacheRange (Address, Length);
}
/**
Invalidates the entire data cache in cache coherency domain of the calling
CPU.
Invalidates the entire data cache in cache coherency domain of the calling
CPU. This function must be used with care because dirty cache lines are not
written back to system memory. It is typically used for cache diagnostics. If
the CPU does not support invalidation of the entire data cache, then a write
back and invalidate operation should be performed on the entire data cache.
**/
VOID
EFIAPI
InvalidateDataCache (
VOID
)
{
//
// Invalidation of the entire data cache without writing back is not supported
// on IPF architecture, so a write back and invalidate operation is performed.
//
WriteBackInvalidateDataCache ();
}
/**
Invalidates a range of data cache lines in the cache coherency domain of the
calling CPU.
Invalidates the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line
containing Address is invalidated. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address +
Length -1 is invalidated. This function must never invalidate any cache lines
outside the specified range. If Length is 0, then no data cache lines are
invalidated. Address is returned. This function must be used with care
because dirty cache lines are not written back to system memory. It is
typically used for cache diagnostics. If the CPU does not support
invalidation of a data cache range, then a write back and invalidate
operation should be performed on the data cache range.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to invalidate. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing mode,
then Address is a virtual address.
@param Length The number of bytes to invalidate from the data cache.
@return Address.
**/
VOID *
EFIAPI
InvalidateDataCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
//
// Invalidation of a data cache range without writing back is not supported on
// IPF architecture, so write back and invalidate operation is performed.
//
return AsmFlushCacheRange (Address, Length);
}

10
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
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@ -29,7 +29,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources.IA32]
@ -51,10 +51,6 @@
X64/CpuFlushTlb.nasm| GCC
X64/CpuFlushTlb.S | GCC
[Sources.IPF]
Ipf/CpuFlushTlb.s
Ipf/CpuSleep.c
[Sources.EBC]
Ebc/CpuSleepFlushTlb.c
@ -76,7 +72,3 @@
MdePkg/MdePkg.dec
[LibraryClasses.IPF]
PalLib
BaseLib

58
MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
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@ -1,58 +0,0 @@
/// @file
/// CpuFlushTlb() function for Itanium-based architecture.
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: CpuFlushTlb.s
///
///
.auto
.text
ASM_GLOBAL PalCall
.type PalCall, @function
.proc CpuFlushTlb
.type CpuFlushTlb, @function
CpuFlushTlb::
alloc loc0 = ar.pfs, 0, 3, 5, 0
mov out0 = 0
mov out1 = 6
mov out2 = 0
mov out3 = 0
mov loc1 = b0
mov out4 = 0
brl.call.sptk b0 = PalCall
mov loc2 = psr // save PSR
mov ar.pfs = loc0
extr.u r14 = r10, 32, 32 // r14 <- count1
rsm 1 << 14 // Disable interrupts
extr.u r15 = r11, 32, 32 // r15 <- stride1
extr.u r10 = r10, 0, 32 // r10 <- count2
add r10 = -1, r10
extr.u r11 = r11, 0, 32 // r11 <- stride2
br.cond.sptk LoopPredicate
LoopOuter:
mov ar.lc = r10 // LC <- count2
mov ar.ec = r0 // EC <- 0
Loop:
ptc.e r9
add r9 = r11, r9 // r9 += stride2
br.ctop.sptk Loop
add r9 = r15, r9 // r9 += stride1
LoopPredicate:
cmp.ne p6 = r0, r14 // count1 == 0?
add r14 = -1, r14
(p6) br.cond.sptk LoopOuter
mov psr.l = loc2
mov b0 = loc1
br.ret.sptk.many b0
.endp

66
MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
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@ -1,66 +0,0 @@
/** @file
Base Library CPU functions for Itanium
Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Library/PalLib.h>
#include <Library/BaseLib.h>
/**
Places the CPU in a sleep state until an interrupt is received.
Places the CPU in a sleep state until an interrupt is received. If interrupts
are disabled prior to calling this function, then the CPU will be placed in a
sleep state indefinitely.
**/
VOID
EFIAPI
CpuSleep (
VOID
)
{
UINT64 Tpr;
//
// It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state
// back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.
// So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts.
// If interrupts are enabled, then just use current TRP setting.
//
if (GetInterruptState ()) {
//
// If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting.
//
PalCall (PAL_HALT_LIGHT, 0, 0, 0);
} else {
//
// If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT.
//
//
// Save TPR
//
Tpr = AsmReadTpr();
//
// Set TPR.mmi to mask all external interrupts
//
AsmWriteTpr (BIT16 | Tpr);
PalCall (PAL_HALT_LIGHT, 0, 0, 0);
//
// Restore TPR
//
AsmWriteTpr (Tpr);
}
}

2
MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
View File

@ -24,7 +24,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
View File

@ -25,7 +25,7 @@
CONSTRUCTOR = BaseDebugLibSerialPortConstructor
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
View File

@ -23,7 +23,7 @@
LIBRARY_CLASS = DebugPrintErrorLevelLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
View File

@ -11,7 +11,7 @@
# this ExtractGuidedSectionLib couldn't be used for guided section extraction that is required
# by PEI and DXE core for recovery or capsule image processing, etc.
#
# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -34,7 +34,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]

11
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
View File

@ -30,7 +30,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 EBC IPF ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
@ -56,9 +56,6 @@
IoLibEbc.c
IoLib.c
[Sources.IPF]
IoLibIpf.c
[Sources.ARM]
IoLibArm.c
@ -72,9 +69,3 @@
DebugLib
BaseLib
[LibraryClasses.IPF]
PcdLib
[Pcd.IPF]
gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf ## SOMETIMES_CONSUMES

736
MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c
View File

@ -1,736 +0,0 @@
/** @file
Common I/O Library routines.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseIoLibIntrinsicInternal.h"
#include <Library/PcdLib.h>
#define MAP_PORT_BASE_TO_MEM(_Port) \
((((_Port) & 0xfffc) << 10) | ((_Port) & 0x0fff))
/**
Translates I/O port address to memory address.
This function translates I/O port address to memory address by adding the 64MB
aligned I/O Port space to the I/O address.
If I/O Port space base is not 64MB aligned, then ASSERT ().
@param Port The I/O port to read.
@return The memory address.
**/
UINTN
InternalGetMemoryMapAddress (
IN UINTN Port
)
{
UINTN Address;
UINTN IoBlockBaseAddress;
Address = MAP_PORT_BASE_TO_MEM (Port);
IoBlockBaseAddress = PcdGet64(PcdIoBlockBaseAddressForIpf);
//
// Make sure that the I/O Port space base is 64MB aligned.
//
ASSERT ((IoBlockBaseAddress & 0x3ffffff) == 0);
Address += IoBlockBaseAddress;
return Address;
}
/**
Reads an 8-bit I/O port.
Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT8
EFIAPI
IoRead8 (
IN UINTN Port
)
{
return MmioRead8 (InternalGetMemoryMapAddress (Port));
}
/**
Reads a 16-bit I/O port.
Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 16-bit boundary, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT16
EFIAPI
IoRead16 (
IN UINTN Port
)
{
return MmioRead16 (InternalGetMemoryMapAddress (Port));
}
/**
Reads a 32-bit I/O port.
Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 32-bit boundary, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT32
EFIAPI
IoRead32 (
IN UINTN Port
)
{
return MmioRead32 (InternalGetMemoryMapAddress (Port));
}
/**
Reads a 64-bit I/O port.
Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
This function must guarantee that all I/O read and write operations are
serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 64-bit boundary, then ASSERT().
@param Port The I/O port to read.
@return The value read.
**/
UINT64
EFIAPI
IoRead64 (
IN UINTN Port
)
{
ASSERT (FALSE);
return 0;
}
/**
Writes an 8-bit I/O port.
Writes the 8-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT8
EFIAPI
IoWrite8 (
IN UINTN Port,
IN UINT8 Value
)
{
return MmioWrite8 (InternalGetMemoryMapAddress (Port), Value);
}
/**
Writes a 16-bit I/O port.
Writes the 16-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 16-bit boundary, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT16
EFIAPI
IoWrite16 (
IN UINTN Port,
IN UINT16 Value
)
{
return MmioWrite16 (InternalGetMemoryMapAddress (Port), Value);
}
/**
Writes a 32-bit I/O port.
Writes the 32-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 32-bit boundary, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT32
EFIAPI
IoWrite32 (
IN UINTN Port,
IN UINT32 Value
)
{
return MmioWrite32 (InternalGetMemoryMapAddress (Port), Value);
}
/**
Writes a 64-bit I/O port.
Writes the 64-bit I/O port specified by Port with the value specified by Value
and returns Value. This function must guarantee that all I/O read and write
operations are serialized.
If 64-bit I/O port operations are not supported, then ASSERT().
If Port is not aligned on a 64-bit boundary, then ASSERT().
@param Port The I/O port to write.
@param Value The value to write to the I/O port.
@return The value written the I/O port.
**/
UINT64
EFIAPI
IoWrite64 (
IN UINTN Port,
IN UINT64 Value
)
{
ASSERT (FALSE);
return 0;
}
/**
Reads an 8-bit I/O port fifo into a block of memory.
Reads the 8-bit I/O fifo port specified by Port.
The port is read Count times, and the read data is
stored in the provided Buffer.
This function must guarantee that all I/O read and write operations are
serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@param Count The number of times to read I/O port.
@param Buffer The buffer to store the read data into.
**/
VOID
EFIAPI
IoReadFifo8 (
IN UINTN Port,
IN UINTN Count,
OUT VOID *Buffer
)
{
UINT8 *Buffer8;
Buffer8 = (UINT8 *)Buffer;
while (Count-- > 0) {
*Buffer8++ = IoRead8 (Port);
}
}
/**
Reads a 16-bit I/O port fifo into a block of memory.
Reads the 16-bit I/O fifo port specified by Port.
The port is read Count times, and the read data is
stored in the provided Buffer.
This function must guarantee that all I/O read and write operations are
serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@param Count The number of times to read I/O port.
@param Buffer The buffer to store the read data into.
**/
VOID
EFIAPI
IoReadFifo16 (
IN UINTN Port,
IN UINTN Count,
OUT VOID *Buffer
)
{
UINT16 *Buffer16;
Buffer16 = (UINT16 *)Buffer;
while (Count-- > 0) {
*Buffer16++ = IoRead16 (Port);
}
}
/**
Reads a 32-bit I/O port fifo into a block of memory.
Reads the 32-bit I/O fifo port specified by Port.
The port is read Count times, and the read data is
stored in the provided Buffer.
This function must guarantee that all I/O read and write operations are
serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to read.
@param Count The number of times to read I/O port.
@param Buffer The buffer to store the read data into.
**/
VOID
EFIAPI
IoReadFifo32 (
IN UINTN Port,
IN UINTN Count,
OUT VOID *Buffer
)
{
UINT32 *Buffer32;
Buffer32 = (UINT32 *)Buffer;
while (Count-- > 0) {
*Buffer32++ = IoRead32 (Port);
}
}
/**
Writes a block of memory into an 8-bit I/O port fifo.
Writes the 8-bit I/O fifo port specified by Port.
The port is written Count times, and the write data is
retrieved from the provided Buffer.
This function must guarantee that all I/O write and write operations are
serialized.
If 8-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Count The number of times to write I/O port.
@param Buffer The buffer to retrieve the write data from.
**/
VOID
EFIAPI
IoWriteFifo8 (
IN UINTN Port,
IN UINTN Count,
IN VOID *Buffer
)
{
UINT8 *Buffer8;
Buffer8 = (UINT8 *)Buffer;
while (Count-- > 0) {
IoWrite8 (Port, *Buffer8++);
}
}
/**
Writes a block of memory into a 16-bit I/O port fifo.
Writes the 16-bit I/O fifo port specified by Port.
The port is written Count times, and the write data is
retrieved from the provided Buffer.
This function must guarantee that all I/O write and write operations are
serialized.
If 16-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Count The number of times to write I/O port.
@param Buffer The buffer to retrieve the write data from.
**/
VOID
EFIAPI
IoWriteFifo16 (
IN UINTN Port,
IN UINTN Count,
IN VOID *Buffer
)
{
UINT16 *Buffer16;
Buffer16 = (UINT16 *)Buffer;
while (Count-- > 0) {
IoWrite16 (Port, *Buffer16++);
}
}
/**
Writes a block of memory into a 32-bit I/O port fifo.
Writes the 32-bit I/O fifo port specified by Port.
The port is written Count times, and the write data is
retrieved from the provided Buffer.
This function must guarantee that all I/O write and write operations are
serialized.
If 32-bit I/O port operations are not supported, then ASSERT().
@param Port The I/O port to write.
@param Count The number of times to write I/O port.
@param Buffer The buffer to retrieve the write data from.
**/
VOID
EFIAPI
IoWriteFifo32 (
IN UINTN Port,
IN UINTN Count,
IN VOID *Buffer
)
{
UINT32 *Buffer32;
Buffer32 = (UINT32 *)Buffer;
while (Count-- > 0) {
IoWrite32 (Port, *Buffer32++);
}
}
/**
Reads an 8-bit MMIO register.
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT8
EFIAPI
MmioRead8 (
IN UINTN Address
)
{
UINT8 Data;
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT8 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 16-bit MMIO register.
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT16
EFIAPI
MmioRead16 (
IN UINTN Address
)
{
UINT16 Data;
//
// Make sure that Address is 16-bit aligned.
//
ASSERT ((Address & 1) == 0);
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT16 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 32-bit MMIO register.
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT32
EFIAPI
MmioRead32 (
IN UINTN Address
)
{
UINT32 Data;
//
// Make sure that Address is 32-bit aligned.
//
ASSERT ((Address & 3) == 0);
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT32 *) Address);
MemoryFence ();
return Data;
}
/**
Reads a 64-bit MMIO register.
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
returned. This function must guarantee that all MMIO read and write
operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 64-bit boundary, then ASSERT().
@param Address The MMIO register to read.
@return The value read.
**/
UINT64
EFIAPI
MmioRead64 (
IN UINTN Address
)
{
UINT64 Data;
//
// Make sure that Address is 64-bit aligned.
//
ASSERT ((Address & 7) == 0);
Address |= BIT63;
MemoryFence ();
Data = *((volatile UINT64 *) Address);
MemoryFence ();
return Data;
}
/**
Writes an 8-bit MMIO register.
Writes the 8-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 8-bit MMIO register operations are not supported, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
@return Value.
**/
UINT8
EFIAPI
MmioWrite8 (
IN UINTN Address,
IN UINT8 Value
)
{
Address |= BIT63;
MemoryFence ();
*((volatile UINT8 *) Address) = Value;
MemoryFence ();
return Value;
}
/**
Writes a 16-bit MMIO register.
Writes the 16-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 16-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
@return Value.
**/
UINT16
EFIAPI
MmioWrite16 (
IN UINTN Address,
IN UINT16 Value
)
{
//
// Make sure that Address is 16-bit aligned.
//
ASSERT ((Address & 1) == 0);
Address |= BIT63;
MemoryFence ();
*((volatile UINT16 *) Address) = Value;
MemoryFence ();
return Value;
}
/**
Writes a 32-bit MMIO register.
Writes the 32-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 32-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
@return Value.
**/
UINT32
EFIAPI
MmioWrite32 (
IN UINTN Address,
IN UINT32 Value
)
{
//
// Make sure that Address is 32-bit aligned.
//
ASSERT ((Address & 3) == 0);
Address |= BIT63;
MemoryFence ();
*((volatile UINT32 *) Address) = Value;
MemoryFence ();
return Value;
}
/**
Writes a 64-bit MMIO register.
Writes the 64-bit MMIO register specified by Address with the value specified
by Value and returns Value. This function must guarantee that all MMIO read
and write operations are serialized.
If 64-bit MMIO register operations are not supported, then ASSERT().
If Address is not aligned on a 64-bit boundary, then ASSERT().
@param Address The MMIO register to write.
@param Value The value to write to the MMIO register.
**/
UINT64
EFIAPI
MmioWrite64 (
IN UINTN Address,
IN UINT64 Value
)
{
//
// Make sure that Address is 64-bit aligned.
//
ASSERT ((Address & 7) == 0);
Address |= BIT63;
MemoryFence ();
*((volatile UINT64 *) Address) = Value;
MemoryFence ();
return Value;
}

35
MdePkg/Library/BaseLib/BaseLib.inf
View File

@ -25,7 +25,7 @@
LIBRARY_CLASS = BaseLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
@ -537,39 +537,6 @@
X64/RdRand.S | GCC
ChkStkGcc.c | GCC
[Sources.IPF]
Ipf/AccessGp.s
Ipf/ReadCpuid.s
Ipf/ExecFc.s
Ipf/AsmPalCall.s
Ipf/AccessPsr.s
Ipf/AccessPmr.s
Ipf/AccessKr.s
Ipf/AccessKr7.s
Ipf/AccessGcr.s
Ipf/AccessEicr.s
Ipf/AccessDbr.s
Ipf/AccessMsr.s | INTEL
Ipf/AccessMsr.s | GCC
Ipf/AccessMsrDb.s | MSFT
Ipf/InternalFlushCacheRange.s
Ipf/FlushCacheRange.c
Ipf/InternalSwitchStack.c
Ipf/GetInterruptState.s
Ipf/CpuPause.s
Ipf/CpuBreakpoint.c | INTEL
Ipf/CpuBreakpointMsc.c | MSFT
Ipf/AsmCpuMisc.s | GCC
Ipf/Unaligned.c
Ipf/SwitchStack.s
Ipf/LongJmp.s
Ipf/SetJmp.s
Ipf/ReadCr.s
Ipf/ReadAr.s
Ipf/Ia64gen.h
Ipf/Asm.h
Math64.c
[Sources.EBC]
Ebc/CpuBreakpoint.c
Ebc/SetJumpLongJump.c

922
MdePkg/Library/BaseLib/BaseLibInternals.h
View File

@ -1,7 +1,7 @@
/** @file
Declaration of internal functions in BaseLib.
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -910,926 +910,6 @@ InternalX86RdRand64 (
OUT UINT64 *Rand
);
#elif defined (MDE_CPU_IPF)
//
//
// IPF specific functions
//
/**
Reads control register DCR.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_DCR.
@return The 64-bit control register DCR.
**/
UINT64
EFIAPI
AsmReadControlRegisterDcr (
VOID
);
/**
Reads control register ITM.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_ITM.
@return The 64-bit control register ITM.
**/
UINT64
EFIAPI
AsmReadControlRegisterItm (
VOID
);
/**
Reads control register IVA.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IVA.
@return The 64-bit control register IVA.
**/
UINT64
EFIAPI
AsmReadControlRegisterIva (
VOID
);
/**
Reads control register PTA.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_PTA.
@return The 64-bit control register PTA.
**/
UINT64
EFIAPI
AsmReadControlRegisterPta (
VOID
);
/**
Reads control register IPSR.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IPSR.
@return The 64-bit control register IPSR.
**/
UINT64
EFIAPI
AsmReadControlRegisterIpsr (
VOID
);
/**
Reads control register ISR.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_ISR.
@return The 64-bit control register ISR.
**/
UINT64
EFIAPI
AsmReadControlRegisterIsr (
VOID
);
/**
Reads control register IIP.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IIP.
@return The 64-bit control register IIP.
**/
UINT64
EFIAPI
AsmReadControlRegisterIip (
VOID
);
/**
Reads control register IFA.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IFA.
@return The 64-bit control register IFA.
**/
UINT64
EFIAPI
AsmReadControlRegisterIfa (
VOID
);
/**
Reads control register ITIR.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_ITIR.
@return The 64-bit control register ITIR.
**/
UINT64
EFIAPI
AsmReadControlRegisterItir (
VOID
);
/**
Reads control register IIPA.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IIPA.
@return The 64-bit control register IIPA.
**/
UINT64
EFIAPI
AsmReadControlRegisterIipa (
VOID
);
/**
Reads control register IFS.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IFS.
@return The 64-bit control register IFS.
**/
UINT64
EFIAPI
AsmReadControlRegisterIfs (
VOID
);
/**
Reads control register IIM.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IIM.
@return The 64-bit control register IIM.
**/
UINT64
EFIAPI
AsmReadControlRegisterIim (
VOID
);
/**
Reads control register IHA.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IHA.
@return The 64-bit control register IHA.
**/
UINT64
EFIAPI
AsmReadControlRegisterIha (
VOID
);
/**
Reads control register LID.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_LID.
@return The 64-bit control register LID.
**/
UINT64
EFIAPI
AsmReadControlRegisterLid (
VOID
);
/**
Reads control register IVR.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IVR.
@return The 64-bit control register IVR.
**/
UINT64
EFIAPI
AsmReadControlRegisterIvr (
VOID
);
/**
Reads control register TPR.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_TPR.
@return The 64-bit control register TPR.
**/
UINT64
EFIAPI
AsmReadControlRegisterTpr (
VOID
);
/**
Reads control register EOI.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_EOI.
@return The 64-bit control register EOI.
**/
UINT64
EFIAPI
AsmReadControlRegisterEoi (
VOID
);
/**
Reads control register IRR0.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IRR0.
@return The 64-bit control register IRR0.
**/
UINT64
EFIAPI
AsmReadControlRegisterIrr0 (
VOID
);
/**
Reads control register IRR1.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IRR1.
@return The 64-bit control register IRR1.
**/
UINT64
EFIAPI
AsmReadControlRegisterIrr1 (
VOID
);
/**
Reads control register IRR2.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IRR2.
@return The 64-bit control register IRR2.
**/
UINT64
EFIAPI
AsmReadControlRegisterIrr2 (
VOID
);
/**
Reads control register IRR3.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_IRR3.
@return The 64-bit control register IRR3.
**/
UINT64
EFIAPI
AsmReadControlRegisterIrr3 (
VOID
);
/**
Reads control register ITV.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_ITV.
@return The 64-bit control register ITV.
**/
UINT64
EFIAPI
AsmReadControlRegisterItv (
VOID
);
/**
Reads control register PMV.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_PMV.
@return The 64-bit control register PMV.
**/
UINT64
EFIAPI
AsmReadControlRegisterPmv (
VOID
);
/**
Reads control register CMCV.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_CMCV.
@return The 64-bit control register CMCV.
**/
UINT64
EFIAPI
AsmReadControlRegisterCmcv (
VOID
);
/**
Reads control register LRR0.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_LRR0.
@return The 64-bit control register LRR0.
**/
UINT64
EFIAPI
AsmReadControlRegisterLrr0 (
VOID
);
/**
Reads control register LRR1.
This is a worker function for AsmReadControlRegister()
when its parameter Index is IPF_CONTROL_REGISTER_LRR1.
@return The 64-bit control register LRR1.
**/
UINT64
EFIAPI
AsmReadControlRegisterLrr1 (
VOID
);
/**
Reads application register K0.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_K0.
@return The 64-bit application register K0.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterK0 (
VOID
);
/**
Reads application register K1.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_K1.
@return The 64-bit application register K1.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterK1 (
VOID
);
/**
Reads application register K2.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_K2.
@return The 64-bit application register K2.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterK2 (
VOID
);
/**
Reads application register K3.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_K3.
@return The 64-bit application register K3.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterK3 (
VOID
);
/**
Reads application register K4.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_K4.
@return The 64-bit application register K4.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterK4 (
VOID
);
/**
Reads application register K5.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_K5.
@return The 64-bit application register K5.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterK5 (
VOID
);
/**
Reads application register K6.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_K6.
@return The 64-bit application register K6.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterK6 (
VOID
);
/**
Reads application register K7.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_K7.
@return The 64-bit application register K7.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterK7 (
VOID
);
/**
Reads application register RSC.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_RSC.
@return The 64-bit application register RSC.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterRsc (
VOID
);
/**
Reads application register BSP.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_BSP.
@return The 64-bit application register BSP.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterBsp (
VOID
);
/**
Reads application register BSPSTORE.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_BSPSTORE.
@return The 64-bit application register BSPSTORE.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterBspstore (
VOID
);
/**
Reads application register RNAT.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_RNAT.
@return The 64-bit application register RNAT.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterRnat (
VOID
);
/**
Reads application register FCR.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_FCR.
@return The 64-bit application register FCR.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterFcr (
VOID
);
/**
Reads application register EFLAG.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_EFLAG.
@return The 64-bit application register EFLAG.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterEflag (
VOID
);
/**
Reads application register CSD.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_CSD.
@return The 64-bit application register CSD.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterCsd (
VOID
);
/**
Reads application register SSD.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_SSD.
@return The 64-bit application register SSD.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterSsd (
VOID
);
/**
Reads application register CFLG.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_CFLG.
@return The 64-bit application register CFLG.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterCflg (
VOID
);
/**
Reads application register FSR.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_FSR.
@return The 64-bit application register FSR.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterFsr (
VOID
);
/**
Reads application register FIR.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_FIR.
@return The 64-bit application register FIR.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterFir (
VOID
);
/**
Reads application register FDR.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_FDR.
@return The 64-bit application register FDR.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterFdr (
VOID
);
/**
Reads application register CCV.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_CCV.
@return The 64-bit application register CCV.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterCcv (
VOID
);
/**
Reads application register UNAT.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_UNAT.
@return The 64-bit application register UNAT.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterUnat (
VOID
);
/**
Reads application register FPSR.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_FPSR.
@return The 64-bit application register FPSR.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterFpsr (
VOID
);
/**
Reads application register ITC.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_ITC.
@return The 64-bit application register ITC.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterItc (
VOID
);
/**
Reads application register PFS.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_PFS.
@return The 64-bit application register PFS.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterPfs (
VOID
);
/**
Reads application register LC.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_LC.
@return The 64-bit application register LC.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterLc (
VOID
);
/**
Reads application register EC.
This is a worker function for AsmReadApplicationRegister()
when its parameter Index is IPF_APPLICATION_REGISTER_EC.
@return The 64-bit application register EC.
**/
UINT64
EFIAPI
AsmReadApplicationRegisterEc (
VOID
);
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the new stack
specified by NewStack and passing in the parameters specified by Context1 and
Context2. Context1 and Context2 are optional and may be NULL. The function
EntryPoint must never return.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param NewBsp A pointer to the new memory location for RSE backing
store.
**/
VOID
EFIAPI
AsmSwitchStackAndBackingStore (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VOID *NewBsp
);
/**
Internal worker function to invalidate a range of instruction cache lines
in the cache coherency domain of the calling CPU.
Internal worker function to invalidate the instruction cache lines specified
by Address and Length. If Address is not aligned on a cache line boundary,
then entire instruction cache line containing Address is invalidated. If
Address + Length is not aligned on a cache line boundary, then the entire
instruction cache line containing Address + Length -1 is invalidated. This
function may choose to invalidate the entire instruction cache if that is more
efficient than invalidating the specified range. If Length is 0, the no instruction
cache lines are invalidated. Address is returned.
This function is only available on IPF.
@param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address
**/
VOID *
EFIAPI
InternalFlushCacheRange (
IN VOID *Address,
IN UINTN Length
);
#else
#endif

118
MdePkg/Library/BaseLib/Ipf/AccessDbr.s
View File

@ -1,118 +0,0 @@
/// @file
/// IPF specific Debug Breakpoint Registers accessing functions
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessDbr.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadDbr
//
// This routine is used to Reads the current value of Data Breakpoint Register (DBR).
//
// Arguments :
//
// On Entry : The 8-bit DBR index to read.
//
// Return Value: The current value of DBR by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadDbr, @function
.proc AsmReadDbr
.regstk 1, 0, 0, 0
AsmReadDbr::
mov r8 = dbr[in0];;
br.ret.dpnt b0;;
.endp AsmReadDbr
//---------------------------------------------------------------------------------
//++
// AsmWriteDbr
//
// This routine is used to write the current value to Data Breakpoint Register (DBR).
//
// Arguments :
//
// On Entry : The 8-bit DBR index to read.
// The value should be written to DBR
//
// Return Value: The value written to DBR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteDbr, @function
.proc AsmWriteDbr
.regstk 2, 0, 0, 0
AsmWriteDbr::
mov dbr[in0] = in1
mov r8 = in1;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteDbr
//---------------------------------------------------------------------------------
//++
// AsmReadIbr
//
// This routine is used to Reads the current value of Instruction Breakpoint Register (IBR).
//
// Arguments :
//
// On Entry : The 8-bit IBR index.
//
// Return Value: The current value of IBR by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIbr, @function
.proc AsmReadIbr
.regstk 1, 0, 0, 0
AsmReadIbr::
mov r8 = ibr[in0];;
br.ret.dpnt b0;;
.endp AsmReadIbr
//---------------------------------------------------------------------------------
//++
// AsmWriteIbr
//
// This routine is used to write the current value to Instruction Breakpoint Register (IBR).
//
// Arguments :
//
// On Entry : The 8-bit IBR index.
// The value should be written to IBR
//
// Return Value: The value written to IBR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteIbr, @function
.proc AsmWriteIbr
.regstk 2, 0, 0, 0
AsmWriteIbr::
mov ibr[in0] = in1
mov r8 = in1;;
srlz.i;;
br.ret.dpnt b0;;
.endp AsmWriteIbr

512
MdePkg/Library/BaseLib/Ipf/AccessEicr.s
View File

@ -1,512 +0,0 @@
/// @file
/// IPF specific External Interrupt Control Registers accessing functions
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessEicr.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadLid
//
// This routine is used to read the value of Local Interrupt ID Register (LID).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of LID.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadLid, @function
.proc AsmReadLid
AsmReadLid::
mov r8 = cr.lid;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmReadLid
//---------------------------------------------------------------------------------
//++
// AsmWriteLid
//
// This routine is used to write the value to Local Interrupt ID Register (LID).
//
// Arguments :
//
// On Entry : The value need to be written to LID.
//
// Return Value: The value written to LID.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteLid, @function
.proc AsmWriteLid
.regstk 1, 0, 0, 0
AsmWriteLid::
mov cr.lid = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteLid
//---------------------------------------------------------------------------------
//++
// AsmReadIvr
//
// This routine is used to read the value of External Interrupt Vector Register (IVR).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IVR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIvr, @function
.proc AsmReadIvr
AsmReadIvr::
mov r8 = cr.ivr;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmReadIvr
//---------------------------------------------------------------------------------
//++
// AsmReadTpr
//
// This routine is used to read the value of Task Priority Register (TPR).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of TPR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadTpr, @function
.proc AsmReadTpr
AsmReadTpr::
mov r8 = cr.tpr;;
br.ret.dpnt b0;;
.endp AsmReadTpr
//---------------------------------------------------------------------------------
//++
// AsmWriteTpr
//
// This routine is used to write the value to Task Priority Register (TPR).
//
// Arguments :
//
// On Entry : The value need to be written to TPR.
//
// Return Value: The value written to TPR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteTpr, @function
.proc AsmWriteTpr
.regstk 1, 0, 0, 0
AsmWriteTpr::
mov cr.tpr = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteTpr
//---------------------------------------------------------------------------------
//++
// AsmWriteEoi
//
// This routine is used to write the value to End of External Interrupt Register (EOI).
//
// Arguments :
//
// On Entry : The value need to be written to EOI.
//
// Return Value: The value written to EOI.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteEoi, @function
.proc AsmWriteEoi
AsmWriteEoi::
mov cr.eoi = r0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteEoi
//---------------------------------------------------------------------------------
//++
// AsmReadIrr0
//
// This routine is used to Read the value of External Interrupt Request Register 0 (IRR0).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IRR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIrr0, @function
.proc AsmReadIrr0
AsmReadIrr0::
mov r8 = cr.irr0;;
br.ret.dpnt b0;;
.endp AsmReadIrr0
//---------------------------------------------------------------------------------
//++
// AsmReadIrr1
//
// This routine is used to Read the value of External Interrupt Request Register 1 (IRR1).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IRR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIrr1, @function
.proc AsmReadIrr1
AsmReadIrr1::
mov r8 = cr.irr1;;
br.ret.dpnt b0;;
.endp AsmReadIrr1
//---------------------------------------------------------------------------------
//++
// AsmReadIrr2
//
// This routine is used to Read the value of External Interrupt Request Register 2 (IRR2).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IRR2.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIrr2, @function
.proc AsmReadIrr2
AsmReadIrr2::
mov r8 = cr.irr2;;
br.ret.dpnt b0;;
.endp AsmReadIrr2
//---------------------------------------------------------------------------------
//++
// AsmReadIrr3
//
// This routine is used to Read the value of External Interrupt Request Register 3 (IRR3).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IRR3.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIrr3, @function
.proc AsmReadIrr3
AsmReadIrr3::
mov r8 = cr.irr3;;
br.ret.dpnt b0;;
.endp AsmReadIrr3
//---------------------------------------------------------------------------------
//++
// AsmReadItv
//
// This routine is used to Read the value of Interval Timer Vector Register (ITV).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of ITV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadItv, @function
.proc AsmReadItv
AsmReadItv::
mov r8 = cr.itv;;
br.ret.dpnt b0;;
.endp AsmReadItv
//---------------------------------------------------------------------------------
//++
// AsmWriteItv
//
// This routine is used to write the value to Interval Timer Vector Register (ITV).
//
// Arguments :
//
// On Entry : The value need to be written to ITV
//
// Return Value: The value written to ITV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteItv, @function
.proc AsmWriteItv
.regstk 1, 0, 0, 0
AsmWriteItv::
mov cr.itv = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteItv
//---------------------------------------------------------------------------------
//++
// AsmReadPmv
//
// This routine is used to Read the value of Performance Monitoring Vector Register (PMV).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of PMV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPmv, @function
.proc AsmReadPmv
AsmReadPmv::
mov r8 = cr.pmv;;
br.ret.dpnt b0;;
.endp AsmReadPmv
//---------------------------------------------------------------------------------
//++
// AsmWritePmv
//
// This routine is used to write the value to Performance Monitoring Vector Register (PMV).
//
// Arguments :
//
// On Entry : The value need to be written to PMV
//
// Return Value: The value written to PMV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePmv, @function
.proc AsmWritePmv
.regstk 1, 0, 0, 0
AsmWritePmv::
mov cr.pmv = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWritePmv
//---------------------------------------------------------------------------------
//++
// AsmReadCmcv
//
// This routine is used to Read the value of Corrected Machine Check Vector Register (CMCV).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of CMCV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadCmcv, @function
.proc AsmReadCmcv
AsmReadCmcv::
mov r8 = cr.cmcv;;
br.ret.dpnt b0;;
.endp AsmReadCmcv
//---------------------------------------------------------------------------------
//++
// AsmWriteCmcv
//
// This routine is used to write the value to Corrected Machine Check Vector Register (CMCV).
//
// Arguments :
//
// On Entry : The value need to be written to CMCV
//
// Return Value: The value written to CMCV.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteCmcv, @function
.proc AsmWriteCmcv
.regstk 1, 0, 0, 0
AsmWriteCmcv::
mov cr.cmcv = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteCmcv
//---------------------------------------------------------------------------------
//++
// AsmReadLrr0
//
// This routine is used to read the value of Local Redirection Register 0 (LRR0).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of LRR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadLrr0, @function
.proc AsmReadLrr0
AsmReadLrr0::
mov r8 = cr.lrr0;;
br.ret.dpnt b0;;
.endp AsmReadLrr0
//---------------------------------------------------------------------------------
//++
// AsmWriteLrr0
//
// This routine is used to write the value to Local Redirection Register 0 (LRR0).
//
// Arguments :
//
// On Entry : The value need to be written to LRR0.
//
// Return Value: The value written to LRR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteLrr0, @function
.proc AsmWriteLrr0
.regstk 1, 0, 0, 0
AsmWriteLrr0::
mov cr.lrr0 = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteLrr0
//---------------------------------------------------------------------------------
//++
// AsmReadLrr1
//
// This routine is used to read the value of Local Redirection Register 1 (LRR1).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of LRR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadLrr1, @function
.proc AsmReadLrr1
AsmReadLrr1::
mov r8 = cr.lrr1;;
br.ret.dpnt b0;;
.endp AsmReadLrr1
//---------------------------------------------------------------------------------
//++
// AsmWriteLrr1
//
// This routine is used to write the value to Local Redirection Register 1 (LRR1).
//
// Arguments :
//
// On Entry : The value need to be written to LRR1.
//
// Return Value: The value written to LRR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteLrr1, @function
.proc AsmWriteLrr1
.regstk 1, 0, 0, 0
AsmWriteLrr1::
mov cr.lrr1 = in0
mov r8 = in0;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteLrr1

274
MdePkg/Library/BaseLib/Ipf/AccessGcr.s
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@ -1,274 +0,0 @@
/// @file
/// IPF specific Global Control Registers accessing functions
///
/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessGcr.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadDcr
//
// This routine is used to Read the value of Default Control Register (DCR).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of DCR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadDcr, @function
.proc AsmReadDcr
AsmReadDcr::
mov r8 = cr.dcr;;
br.ret.dpnt b0;;
.endp AsmReadDcr
//---------------------------------------------------------------------------------
//++
// AsmWriteDcr
//
// This routine is used to write the value to Default Control Register (DCR).
//
// Arguments :
//
// On Entry : The value need to be written to DCR
//
// Return Value: The value written to DCR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteDcr, @function
.proc AsmWriteDcr
.regstk 1, 0, 0, 0
AsmWriteDcr::
mov cr.dcr = in0
mov r8 = in0;;
srlz.i;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteDcr
//---------------------------------------------------------------------------------
//++
// AsmReadItc
//
// This routine is used to Read the value of Interval Timer Counter Register (ITC).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of ITC.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadItc, @function
.proc AsmReadItc
AsmReadItc::
mov r8 = ar.itc;;
br.ret.dpnt b0;;
.endp AsmReadItc
//---------------------------------------------------------------------------------
//++
// AsmWriteItc
//
// This routine is used to write the value to Interval Timer Counter Register (ITC).
//
// Arguments :
//
// On Entry : The value need to be written to the ITC
//
// Return Value: The value written to the ITC.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteItc, @function
.proc AsmWriteItc
.regstk 1, 0, 0, 0
AsmWriteItc::
mov ar.itc = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteItc
//---------------------------------------------------------------------------------
//++
// AsmReadItm
//
// This routine is used to Read the value of Interval Timer Match Register (ITM).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of ITM.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadItm, @function
.proc AsmReadItm
AsmReadItm::
mov r8 = cr.itm;;
br.ret.dpnt b0;;
.endp AsmReadItm
//---------------------------------------------------------------------------------
//++
// AsmWriteItm
//
// This routine is used to write the value to Interval Timer Match Register (ITM).
//
// Arguments :
//
// On Entry : The value need to be written to ITM
//
// Return Value: The value written to ITM.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteItm, @function
.proc AsmWriteItm
.regstk 1, 0, 0, 0
AsmWriteItm::
mov cr.itm = in0
mov r8 = in0;;
srlz.d;
br.ret.dpnt b0;;
.endp AsmWriteItm
//---------------------------------------------------------------------------------
//++
// AsmReadIva
//
// This routine is used to read the value of Interruption Vector Address Register (IVA).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of IVA.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIva, @function
.proc AsmReadIva
AsmReadIva::
mov r8 = cr.iva;;
br.ret.dpnt b0;;
.endp AsmReadIva
//---------------------------------------------------------------------------------
//++
// AsmWriteIva
//
// This routine is used to write the value to Interruption Vector Address Register (IVA).
//
// Arguments :
//
// On Entry : The value need to be written to IVA
//
// Return Value: The value written to IVA.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteIva, @function
.proc AsmWriteIva
.regstk 1, 3, 0, 0
AsmWriteIva::
alloc loc1=ar.pfs,1,4,0,0 ;;
mov loc2 = psr
rsm 0x6000 // Make sure interrupts are masked
mov cr.iva = in0
srlz.i;;
mov psr.l = loc2;;
srlz.i;;
srlz.d;;
mov ar.pfs=loc1 ;;
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteIva
//---------------------------------------------------------------------------------
//++
// AsmReadPta
//
// This routine is used to read the value of Page Table Address Register (PTA).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current value of PTA.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPta, @function
.proc AsmReadPta
AsmReadPta::
mov r8 = cr.pta;;
br.ret.dpnt b0;;
.endp AsmReadPta
//---------------------------------------------------------------------------------
//++
// AsmWritePta
//
// This routine is used to write the value to Page Table Address Register (PTA)).
//
// Arguments :
//
// On Entry : The value need to be written to PTA
//
// Return Value: The value written to PTA.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePta, @function
.proc AsmWritePta
.regstk 1, 0, 0, 0
AsmWritePta::
mov cr.pta = in0
mov r8 = in0;;
srlz.i;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWritePta

86
MdePkg/Library/BaseLib/Ipf/AccessGp.s
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@ -1,86 +0,0 @@
/// @file
/// IPF specific Global Pointer and Stack Pointer accessing functions
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessGp.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadGp
//
// This routine is used to read the current value of 64-bit Global Pointer (GP).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current GP value.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadGp, @function
.proc AsmReadGp
AsmReadGp::
mov r8 = gp;;
br.ret.dpnt b0;;
.endp AsmReadGp
//---------------------------------------------------------------------------------
//++
// AsmWriteGp
//
// This routine is used to write the current value of 64-bit Global Pointer (GP).
//
// Arguments :
//
// On Entry : The value need to be written.
//
// Return Value: The value have been written.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteGp, @function
.proc AsmWriteGp
.regstk 1, 0, 0, 0
AsmWriteGp::
mov gp = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteGp
//---------------------------------------------------------------------------------
//++
// AsmReadSp
//
// This routine is used to read the current value of 64-bit Stack Pointer (SP).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current SP value.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadSp, @function
.proc AsmReadSp
AsmReadSp::
mov r8 = sp;;
br.ret.dpnt b0;;
.endp AsmReadSp

360
MdePkg/Library/BaseLib/Ipf/AccessKr.s
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@ -1,360 +0,0 @@
/// @file
/// IPF specific AsmReadKrX() and AsmWriteKrX() functions, 'X' is from '0' to '6'
///
/// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessKr.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadKr0
//
// This routine is used to get KR0.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr0, @function
.proc AsmReadKr0
AsmReadKr0::
mov r8 = ar.k0;;
br.ret.dpnt b0;;
.endp AsmReadKr0
//---------------------------------------------------------------------------------
//++
// AsmWriteKr0
//
// This routine is used to Write KR0.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR0.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr0, @function
.proc AsmWriteKr0
.regstk 1, 3, 0, 0
AsmWriteKr0::
alloc loc1=ar.pfs,1,4,0,0 ;;
mov loc2 = psr;;
rsm 0x6000;; // Masking interrupts
mov ar.k0 = in0
srlz.i;;
mov psr.l = loc2;;
srlz.i;;
srlz.d;;
mov r8 = in0;;
mov ar.pfs=loc1 ;;
br.ret.dpnt b0;;
.endp AsmWriteKr0
//---------------------------------------------------------------------------------
//++
// AsmReadKr1
//
// This routine is used to get KR1.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr1, @function
.proc AsmReadKr1
AsmReadKr1::
mov r8 = ar.k1;;
br.ret.dpnt b0;;
.endp AsmReadKr1
//---------------------------------------------------------------------------------
//++
// AsmWriteKr1
//
// This routine is used to Write KR1.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR1.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr1, @function
.proc AsmWriteKr1
AsmWriteKr1::
mov ar.k1 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr1
//---------------------------------------------------------------------------------
//++
// AsmReadKr2
//
// This routine is used to get KR2.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR2.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr2, @function
.proc AsmReadKr2
AsmReadKr2::
mov r8 = ar.k2;;
br.ret.dpnt b0;;
.endp AsmReadKr2
//---------------------------------------------------------------------------------
//++
// AsmWriteKr2
//
// This routine is used to Write KR2.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR2.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr2, @function
.proc AsmWriteKr2
AsmWriteKr2::
mov ar.k2 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr2
//---------------------------------------------------------------------------------
//++
// AsmReadKr3
//
// This routine is used to get KR3.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR3.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr3, @function
.proc AsmReadKr3
AsmReadKr3::
mov r8 = ar.k3;;
br.ret.dpnt b0;;
.endp AsmReadKr3
//---------------------------------------------------------------------------------
//++
// AsmWriteKr3
//
// This routine is used to Write KR3.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR3.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr3, @function
.proc AsmWriteKr3
AsmWriteKr3::
mov ar.k3 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr3
//---------------------------------------------------------------------------------
//++
// AsmReadKr4
//
// This routine is used to get KR4.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR4.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr4, @function
.proc AsmReadKr4
AsmReadKr4::
mov r8 = ar.k4;;
br.ret.dpnt b0;;
.endp AsmReadKr4
//---------------------------------------------------------------------------------
//++
// AsmWriteKr4
//
// This routine is used to Write KR4.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR4.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr4, @function
.proc AsmWriteKr4
AsmWriteKr4::
mov ar.k4 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr4
//---------------------------------------------------------------------------------
//++
// AsmReadKr5
//
// This routine is used to get KR5.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR5.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr5, @function
.proc AsmReadKr5
AsmReadKr5::
mov r8 = ar.k5;;
br.ret.dpnt b0;;
.endp AsmReadKr5
//---------------------------------------------------------------------------------
//++
// AsmWriteKr5
//
// This routine is used to Write KR5.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR5.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr5, @function
.proc AsmWriteKr5
AsmWriteKr5::
mov ar.k5 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr5
//---------------------------------------------------------------------------------
//++
// AsmReadKr6
//
// This routine is used to get KR6.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR6.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr6, @function
.proc AsmReadKr6
AsmReadKr6::
mov r8 = ar.k6;;
br.ret.dpnt b0;;
.endp AsmReadKr6
//---------------------------------------------------------------------------------
//++
// AsmWriteKr6
//
// This routine is used to write KR6.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR6.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr6, @function
.proc AsmWriteKr6
AsmWriteKr6::
mov ar.k6 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr6

63
MdePkg/Library/BaseLib/Ipf/AccessKr7.s
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@ -1,63 +0,0 @@
/// @file
/// IPF specific AsmReadKr7() and AsmWriteKr7()
///
/// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessKr7.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadKr7
//
// This routine is used to get KR7.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value store in KR7.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadKr7, @function
.proc AsmReadKr7
AsmReadKr7::
mov r8 = ar.k7;;
br.ret.dpnt b0;;
.endp AsmReadKr7
//---------------------------------------------------------------------------------
//++
// AsmWriteKr7
//
// This routine is used to write KR7.
//
// Arguments :
//
// On Entry : None.
//
// Return Value: The value written to the KR7.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteKr7, @function
.proc AsmWriteKr7
.regstk 1, 3, 0, 0
AsmWriteKr7::
mov ar.k7 = in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmWriteKr7

79
MdePkg/Library/BaseLib/Ipf/AccessMsr.s
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@ -1,79 +0,0 @@
/// @file
/// IPF specific Machine Specific Registers accessing functions.
///
/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadMsr
//
// Reads the current value of a Machine Specific Register (MSR).
//
// Reads and returns the current value of the Machine Specific Register specified by Index. No
// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
// Index is valid, or the caller must set up fault handlers to catch the faults. This function is
// only available on IPF.
//
// Arguments :
//
// On Entry : The 8-bit Machine Specific Register index to read.
//
// Return Value: The current value of the Machine Specific Register specified by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadMsr, @function
.proc AsmReadMsr
.regstk 1, 0, 0, 0
AsmReadMsr::
mov r8=msr[in0];;
br.ret.sptk b0;;
.endp AsmReadMsr
//---------------------------------------------------------------------------------
//++
// AsmWriteMsr
//
// Writes the current value of a Machine Specific Register (MSR).
//
// Writes Value to the Machine Specific Register specified by Index. Value is returned. No
// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
// Index is valid, or the caller must set up fault handlers to catch the faults. This function is
// only available on IPF.
//
// Arguments :
//
// On Entry : The 8-bit Machine Specific Register index to write.
// The 64-bit value to write to the Machine Specific Register.
//
// Return Value: The 64-bit value to write to the Machine Specific Register.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteMsr, @function
.proc AsmWriteMsr
.regstk 2, 0, 0, 0
AsmWriteMsr::
mov msr[in0] = in1
mov r8 = in1;;
srlz.d;;
br.ret.sptk b0;;
.endp AsmWriteMsr

121
MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s
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@ -1,121 +0,0 @@
/// @file
/// IPF specific Machine Specific Registers accessing functions.
/// This implementation uses raw data to prepresent the assembly instruction of
/// mov msr[]= and mov =msr[].
///
/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadMsr
//
// Reads the current value of a Machine Specific Register (MSR).
//
// Reads and returns the current value of the Machine Specific Register specified by Index. No
// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
// Index is valid, or the caller must set up fault handlers to catch the faults. This function is
// only available on IPF.
//
// Arguments :
//
// On Entry : The 8-bit Machine Specific Register index to read.
//
// Return Value: The current value of the Machine Specific Register specified by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadMsr, @function
.proc AsmReadMsr
.regstk 1, 0, 0, 0
AsmReadMsr::
//
// The follow 16 bytes stand for the bundle of
// mov r8=msr[in0];;
// since MSFT tool chain does not support mov =msr[] instruction
//
data1 0x0D
data1 0x40
data1 0x00
data1 0x40
data1 0x16
data1 0x04
data1 0x00
data1 0x00
data1 0x00
data1 0x02
data1 0x00
data1 0x00
data1 0x00
data1 0x00
data1 0x04
data1 0x00
br.ret.sptk b0;;
.endp AsmReadMsr
//---------------------------------------------------------------------------------
//++
// AsmWriteMsr
//
// Writes the current value of a Machine Specific Register (MSR).
//
// Writes Value to the Machine Specific Register specified by Index. Value is returned. No
// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
// Index is valid, or the caller must set up fault handlers to catch the faults. This function is
// only available on IPF.
//
// Arguments :
//
// On Entry : The 8-bit Machine Specific Register index to write.
// The 64-bit value to write to the Machine Specific Register.
//
// Return Value: The 64-bit value to write to the Machine Specific Register.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteMsr, @function
.proc AsmWriteMsr
.regstk 2, 0, 0, 0
AsmWriteMsr::
//
// The follow 16 bytes stand for the bundle of
// mov msr[in0] = in1
// mov r8 = in1;;
// since MSFT tool chain does not support mov msr[]= instruction
//
data1 0x0D
data1 0x00
data1 0x84
data1 0x40
data1 0x06
data1 0x04
data1 0x00
data1 0x00
data1 0x00
data1 0x02
data1 0x00
data1 0x00
data1 0x01
data1 0x08
data1 0x01
data1 0x84
srlz.d;;
br.ret.sptk b0;;
.endp AsmWriteMsr

124
MdePkg/Library/BaseLib/Ipf/AccessPmr.s
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@ -1,124 +0,0 @@
/// @file
/// IPF specific Performance Monitor Configuration/Data Registers accessing functions
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessPmr.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadPmc
//
// This routine is used to Reads the current value of Performance Monitor Configuration Register (PMC).
//
// Arguments :
//
// On Entry : The 8-bit PMC index.
//
// Return Value: The current value of PMC by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPmc, @function
.proc AsmReadPmc
.regstk 1, 0, 0, 0
AsmReadPmc::
srlz.i;;
srlz.d;;
mov r8 = pmc[in0];;
br.ret.dpnt b0;;
.endp AsmReadPmc
//---------------------------------------------------------------------------------
//++
// AsmWritePmc
//
// This routine is used to write the current value to a Performance Monitor Configuration Register (PMC).
//
// Arguments :
//
// On Entry : The 8-bit PMC index.
// The value should be written to PMC
//
// Return Value: The value written to PMC.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePmc, @function
.proc AsmWritePmc
.regstk 2, 0, 0, 0
AsmWritePmc::
mov pmc[in0] = in1
mov r8 = in1;;
srlz.i;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWritePmc
//---------------------------------------------------------------------------------
//++
// AsmReadPmd
//
// This routine is used to Reads the current value of Performance Monitor Data Register (PMD).
//
// Arguments :
//
// On Entry : The 8-bit PMD index.
//
// Return Value: The current value of PMD by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPmd, @function
.proc AsmReadPmd
.regstk 1, 0, 0, 0
AsmReadPmd::
srlz.i;;
srlz.d;;
mov r8 = pmd[in0];;
br.ret.dpnt b0;;
.endp AsmReadPmd
//---------------------------------------------------------------------------------
//++
// AsmWritePmd
//
// This routine is used to write the current value to Performance Monitor Data Register (PMD).
//
// Arguments :
//
// On Entry : The 8-bit PMD index.
// The value should be written to PMD
//
// Return Value: The value written to PMD.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePmd, @function
.proc AsmWritePmd
.regstk 2, 0, 0, 0
AsmWritePmd::
mov pmd[in0] = in1
mov r8 = in1;;
srlz.i;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWritePmd

111
MdePkg/Library/BaseLib/Ipf/AccessPsr.s
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@ -1,111 +0,0 @@
/// @file
/// IPF specific Processor Status Register accessing functions
///
/// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessPsr.s
///
///
#define CpuModeMask 0x0000001008020000
#define CpuInVirtualMode 0x1
#define CpuInPhysicalMode 0x0
#define CpuInMixMode (0x0 - 0x1)
//---------------------------------------------------------------------------------
//++
// AsmReadPsr
//
// This routine is used to read the current value of Processor Status Register (PSR).
//
// Arguments :
//
// On Entry :
//
// Return Value: The current PSR value.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadPsr, @function
.proc AsmReadPsr
AsmReadPsr::
mov r8 = psr;;
br.ret.dpnt b0;;
.endp AsmReadPsr
//---------------------------------------------------------------------------------
//++
// AsmWritePsr
//
// This routine is used to write the value of Processor Status Register (PSR).
//
// Arguments :
//
// On Entry : The value need to be written.
//
// Return Value: The value have been written.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWritePsr, @function
.proc AsmWritePsr
.regstk 1, 0, 0, 0
AsmWritePsr::
mov psr.l = in0
mov r8 = in0;;
srlz.d;;
srlz.i;;
br.ret.dpnt b0;;
.endp AsmWritePsr
//---------------------------------------------------------------------------------
//++
// AsmCpuVirtual
//
// This routine is used to determines if the CPU is currently executing
// in virtual, physical, or mixed mode.
//
// If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.
// If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.
// If the CPU is not in physical mode or virtual mode, then it is in mixed mode,
// and -1 is returned.
//
// Arguments:
//
// On Entry: None
//
// Return Value: The CPU mode flag
// return 1 The CPU is in virtual mode.
// return 0 The CPU is in physical mode.
// return -1 The CPU is in mixed mode.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmCpuVirtual, @function
.proc AsmCpuVirtual
AsmCpuVirtual::
mov r29 = psr
movl r30 = CpuModeMask;;
and r28 = r30, r29;;
cmp.eq p6, p7 = r30, r28;;
(p6) mov r8 = CpuInVirtualMode;;
(p6) br.ret.dpnt b0;;
(p7) cmp.eq p6, p7 = 0x0, r28;;
(p6) mov r8 = CpuInPhysicalMode;;
(p7) mov r8 = CpuInMixMode;;
br.ret.dpnt b0;;
.endp AsmCpuVirtual

27
MdePkg/Library/BaseLib/Ipf/Asm.h
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@ -1,27 +0,0 @@
/** @file
This module contains generic macros for an assembly writer.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _ASM_H_
#define _ASM_H_
#define TRUE 1
#define FALSE 0
#define PROCEDURE_ENTRY(name) .##text; \
.##type name, @function; \
.##proc name; \
name::
#define PROCEDURE_EXIT(name) .##endp name
#endif // _ASM_H

79
MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s
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@ -1,79 +0,0 @@
/// @file
/// Contains an implementation of CallPalProcStacked on Itanium-based
/// architecture.
///
/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AsmCpuMisc.s
///
///
.text
.proc CpuBreakpoint
.type CpuBreakpoint, @function
CpuBreakpoint::
break.i 0;;
br.ret.dpnt b0;;
.endp CpuBreakpoint
.proc MemoryFence
.type MemoryFence, @function
MemoryFence::
mf;; // memory access ordering
// do we need the mf.a also here?
mf.a // wait for any IO to complete?
// not sure if we need serialization here, just put it, in case...
srlz.d;;
srlz.i;;
br.ret.dpnt b0;;
.endp MemoryFence
.proc DisableInterrupts
.type DisableInterrupts, @function
DisableInterrupts::
rsm 0x4000
srlz.d;;
br.ret.dpnt b0;;
.endp DisableInterrupts
.proc EnableInterrupts
.type EnableInterrupts, @function
EnableInterrupts::
ssm 0x4000
srlz.d;;
br.ret.dpnt b0;;
.endp EnableInterrupts
.proc EnableDisableInterrupts
.type EnableDisableInterrupts, @function
EnableDisableInterrupts::
ssm 0x4000
srlz.d;;
srlz.i;;
rsm 0x4000
srlz.d;;
br.ret.dpnt b0;;
.endp EnableDisableInterrupts

158
MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
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@ -1,158 +0,0 @@
/// @file
/// Contains an implementation of CallPalProcStacked on Itanium-based
/// architecture.
///
/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AsmPalCall.s
///
///
//-----------------------------------------------------------------------------
//++
// AsmPalCall
//
// Makes a PAL procedure call.
// This is function to make a PAL procedure call. Based on the Index
// value this API will make static or stacked PAL call. The following table
// describes the usage of PAL Procedure Index Assignment. Architected procedures
// may be designated as required or optional. If a PAL procedure is specified
// as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the
// Status field of the PAL_CALL_RETURN structure.
// This indicates that the procedure is not present in this PAL implementation.
// It is the caller's responsibility to check for this return code after calling
// any optional PAL procedure.
// No parameter checking is performed on the 5 input parameters, but there are
// some common rules that the caller should follow when making a PAL call. Any
// address passed to PAL as buffers for return parameters must be 8-byte aligned.
// Unaligned addresses may cause undefined results. For those parameters defined
// as reserved or some fields defined as reserved must be zero filled or the invalid
// argument return value may be returned or undefined result may occur during the
// execution of the procedure. If the PalEntryPoint does not point to a valid
// PAL entry point then the system behavior is undefined. This function is only
// available on IPF.
//
// On Entry :
// in0: PAL_PROC entrypoint
// in1-in4 : PAL_PROC arguments
//
// Return Value:
//
// As per stacked calling conventions.
//
//--
//---------------------------------------------------------------------------
//
// PAL function calls
//
#define PAL_MC_CLEAR_LOG 0x0015
#define PAL_MC_DYNAMIC_STATE 0x0018
#define PAL_MC_ERROR_INFO 0x0019
#define PAL_MC_RESUME 0x001a
.text
.proc AsmPalCall
.type AsmPalCall, @function
AsmPalCall::
alloc loc1 = ar.pfs,5,8,4,0
mov loc0 = b0
mov loc3 = b5
mov loc4 = r2
mov loc7 = r1
mov r2 = psr;;
mov r28 = in1
mov loc5 = r2;;
movl loc6 = 0x100;;
cmp.ge p6,p7 = r28,loc6;;
(p6) movl loc6 = 0x1FF;;
(p7) br.dpnt.few PalCallStatic;; // 0 ~ 255 make a static Pal Call
(p6) cmp.le p6,p7 = r28,loc6;;
(p6) br.dpnt.few PalCallStacked;; // 256 ~ 511 make a stacked Pal Call
(p7) movl loc6 = 0x300;;
(p7) cmp.ge p6,p7 = r28,loc6;;
(p7) br.dpnt.few PalCallStatic;; // 512 ~ 767 make a static Pal Call
(p6) movl loc6 = 0x3FF;;
(p6) cmp.le p6,p7 = r28,loc6;;
(p6) br.dpnt.few PalCallStacked;; // 768 ~ 1023 make a stacked Pal Call
(p7) mov r8 = 0xFFFFFFFFFFFFFFFF;; // > 1024 return invalid
(p7) br.dpnt.few ComeBackFromPALCall;;
PalCallStatic:
movl loc6 = PAL_MC_CLEAR_LOG;;
cmp.eq p6,p7 = r28,loc6;;
(p7) movl loc6 = PAL_MC_DYNAMIC_STATE;;
(p7) cmp.eq p6,p7 = r28,loc6;;
(p7) movl loc6 = PAL_MC_ERROR_INFO;;
(p7) cmp.eq p6,p7 = r28,loc6;;
(p7) movl loc6 = PAL_MC_RESUME;;
(p7) cmp.eq p6,p7 = r28,loc6 ;;
mov loc6 = 0x1;;
(p7) dep r2 = loc6,r2,13,1;; // psr.ic = 1
// p6 will be true, if it is one of the MCHK calls. There has been lots of debate
// on psr.ic for these values. For now, do not do any thing to psr.ic
dep r2 = r0,r2,14,1;; // psr.i = 0
mov psr.l = r2
srlz.d // Needs data serailization.
srlz.i // Needs instruction serailization.
StaticGetPALLocalIP:
mov loc2 = ip;;
add loc2 = ComeBackFromPALCall - StaticGetPALLocalIP,loc2;;
mov b0 = loc2 // return address after Pal call
mov r29 = in2
mov r30 = in3
mov r31 = in4
mov b5 = in0;; // get the PalProcEntrypt from input
br.sptk b5;; // Take the plunge.
PalCallStacked:
dep r2 = r0,r2,14,1;; // psr.i = 0
mov psr.l = r2;;
srlz.d // Needs data serailization.
srlz.i // Needs instruction serailization.
StackedGetPALLocalIP:
mov out0 = in1
mov out1 = in2
mov out2 = in3
mov out3 = in4
mov b5 = in0 ;; // get the PalProcEntrypt from input
br.call.dpnt b0 = b5 ;; // Take the plunge.
ComeBackFromPALCall:
mov psr.l = loc5 ;;
srlz.d // Needs data serailization.
srlz.i // Needs instruction serailization.
mov b5 = loc3
mov r2 = loc4
mov r1 = loc7
mov b0 = loc0
mov ar.pfs = loc1;;
br.ret.dpnt b0;;
.endp AsmPalCall

96
MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
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@ -1,96 +0,0 @@
/** @file
Base Library CPU functions for Itanium
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Generates a breakpoint on the CPU.
Generates a breakpoint on the CPU. The breakpoint must be implemented such
that code can resume normal execution after the breakpoint.
**/
VOID
EFIAPI
CpuBreakpoint (
VOID
)
{
__break (0);
}
/**
Used to serialize load and store operations.
All loads and stores that proceed calls to this function are guaranteed to be
globally visible when this function returns.
**/
VOID
EFIAPI
MemoryFence (
VOID
)
{
__mfa ();
}
/**
Disables CPU interrupts.
Disables CPU interrupts.
**/
VOID
EFIAPI
DisableInterrupts (
VOID
)
{
_disable ();
}
/**
Enables CPU interrupts.
Enables CPU interrupts.
**/
VOID
EFIAPI
EnableInterrupts (
VOID
)
{
_enable ();
}
/**
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
**/
VOID
EFIAPI
EnableDisableInterrupts (
VOID
)
{
EnableInterrupts ();
DisableInterrupts ();
}

102
MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
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@ -1,102 +0,0 @@
/** @file
Base Library CPU functions for Itanium
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
#pragma intrinsic (_enable)
#pragma intrinsic (_disable)
#pragma intrinsic (__break)
#pragma intrinsic (__mfa)
/**
Generates a breakpoint on the CPU.
Generates a breakpoint on the CPU. The breakpoint must be implemented such
that code can resume normal execution after the breakpoint.
**/
VOID
EFIAPI
CpuBreakpoint (
VOID
)
{
__break (0);
}
/**
Used to serialize load and store operations.
All loads and stores that proceed calls to this function are guaranteed to be
globally visible when this function returns.
**/
VOID
EFIAPI
MemoryFence (
VOID
)
{
__mfa ();
}
/**
Disables CPU interrupts.
Disables CPU interrupts.
**/
VOID
EFIAPI
DisableInterrupts (
VOID
)
{
_disable ();
}
/**
Enables CPU interrupts.
Enables CPU interrupts.
**/
VOID
EFIAPI
EnableInterrupts (
VOID
)
{
_enable ();
}
/**
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
Enables CPU interrupts for the smallest window required to capture any
pending interrupts.
**/
VOID
EFIAPI
EnableDisableInterrupts (
VOID
)
{
EnableInterrupts ();
DisableInterrupts ();
}

25
MdePkg/Library/BaseLib/Ipf/CpuPause.s
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@ -1,25 +0,0 @@
/// @file
/// CpuPause() function for Itanium-based architecture.
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: CpuPause.s
///
///
.auto
.text
.proc CpuPause
.type CpuPause, @function
CpuPause::
hint.i @pause
br.ret.sptk.many b0
.endp

66
MdePkg/Library/BaseLib/Ipf/ExecFc.s
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@ -1,66 +0,0 @@
/// @file
/// IPF specific AsmFc() and AsmFci () functions
///
/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: ExecFc.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmFc
//
// This routine is used to execute a FC instruction on the specific address.
//
// Arguments :
//
// On Entry : The specific address need to execute FC instruction.
//
// Return Value: The specific address have been execute FC instruction.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmFc, @function
.proc AsmFc
.regstk 1, 0, 0, 0
AsmFc::
fc in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmFc
//---------------------------------------------------------------------------------
//++
// AsmFci
//
// This routine is used to execute a FC.i instruction on the specific address.
//
// Arguments :
//
// On Entry : The specific address need to execute FC.i instruction.
//
// Return Value: The specific address have been execute FC.i instruction.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmFci, @function
.proc AsmFci
.regstk 1, 0, 0, 0
AsmFci::
fc.i in0
mov r8 = in0;;
br.ret.dpnt b0;;
.endp AsmFci

51
MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c
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@ -1,51 +0,0 @@
/** @file
AsmFlushCacheRange() function for IPF.
Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Flush a range of cache lines in the cache coherency domain of the calling
CPU.
Flushes the cache lines specified by Address and Length. If Address is not aligned
on a cache line boundary, then entire cache line containing Address is flushed.
If Address + Length is not aligned on a cache line boundary, then the entire cache
line containing Address + Length - 1 is flushed. This function may choose to flush
the entire cache if that is more efficient than flushing the specified range. If
Length is 0, the no cache lines are flushed. Address is returned.
This function is only available on IPF.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the instruction lines to invalidate. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing mode,
then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address.
**/
VOID *
EFIAPI
AsmFlushCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return InternalFlushCacheRange (Address, Length);
}

27
MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
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@ -1,27 +0,0 @@
/// @file
/// Retrieve of the interrupt state of the running processor for the Itanium
/// architecture.
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: GetInterruptState.s
///
///
.auto
.text
.proc GetInterruptState
.type GetInterruptState, @function
GetInterruptState::
mov r8 = psr
extr.u r8 = r8, 14, 1
br.ret.sptk.many b0
.endp GetInterruptState

205
MdePkg/Library/BaseLib/Ipf/Ia64gen.h
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@ -1,205 +0,0 @@
/** @file
Register Definition for IPF.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IA64GEN_H_
#define _IA64GEN_H_
#define TT_UNAT 0
#define C_PSR 0
#define J_UNAT 0
#define T_TYPE 0
#define T_IPSR 0x8
#define T_ISR 0x10
#define T_IIP 0x18
#define T_IFA 0x20
#define T_IIPA 0x28
#define T_IFS 0x30
#define T_IIM 0x38
#define T_RSC 0x40
#define T_BSP 0x48
#define T_BSPSTORE 0x50
#define T_RNAT 0x58
#define T_PFS 0x60
#define T_KBSPSTORE 0x68
#define T_UNAT 0x70
#define T_CCV 0x78
#define T_DCR 0x80
#define T_PREDS 0x88
#define T_NATS 0x90
#define T_R1 0x98
#define T_GP 0x98
#define T_R2 0xa0
#define T_R3 0xa8
#define T_R4 0xb0
#define T_R5 0xb8
#define T_R6 0xc0
#define T_R7 0xc8
#define T_R8 0xd0
#define T_R9 0xd8
#define T_R10 0xe0
#define T_R11 0xe8
#define T_R12 0xf0
#define T_SP 0xf0
#define T_R13 0xf8
#define T_R14 0x100
#define T_R15 0x108
#define T_R16 0x110
#define T_R17 0x118
#define T_R18 0x120
#define T_R19 0x128
#define T_R20 0x130
#define T_R21 0x138
#define T_R22 0x140
#define T_R23 0x148
#define T_R24 0x150
#define T_R25 0x158
#define T_R26 0x160
#define T_R27 0x168
#define T_R28 0x170
#define T_R29 0x178
#define T_R30 0x180
#define T_R31 0x188
#define T_F2 0x1f0
#define T_F3 0x200
#define T_F4 0x210
#define T_F5 0x220
#define T_F6 0x230
#define T_F7 0x240
#define T_F8 0x250
#define T_F9 0x260
#define T_F10 0x270
#define T_F11 0x280
#define T_F12 0x290
#define T_F13 0x2a0
#define T_F14 0x2b0
#define T_F15 0x2c0
#define T_F16 0x2d0
#define T_F17 0x2e0
#define T_F18 0x2f0
#define T_F19 0x300
#define T_F20 0x310
#define T_F21 0x320
#define T_F22 0x330
#define T_F23 0x340
#define T_F24 0x350
#define T_F25 0x360
#define T_F26 0x370
#define T_F27 0x380
#define T_F28 0x390
#define T_F29 0x3a0
#define T_F30 0x3b0
#define T_F31 0x3c0
#define T_FPSR 0x1e0
#define T_B0 0x190
#define T_B1 0x198
#define T_B2 0x1a0
#define T_B3 0x1a8
#define T_B4 0x1b0
#define T_B5 0x1b8
#define T_B6 0x1c0
#define T_B7 0x1c8
#define T_EC 0x1d0
#define T_LC 0x1d8
#define J_NATS 0x8
#define J_PFS 0x10
#define J_BSP 0x18
#define J_RNAT 0x20
#define J_PREDS 0x28
#define J_LC 0x30
#define J_R4 0x38
#define J_R5 0x40
#define J_R6 0x48
#define J_R7 0x50
#define J_SP 0x58
#define J_F2 0x60
#define J_F3 0x70
#define J_F4 0x80
#define J_F5 0x90
#define J_F16 0xa0
#define J_F17 0xb0
#define J_F18 0xc0
#define J_F19 0xd0
#define J_F20 0xe0
#define J_F21 0xf0
#define J_F22 0x100
#define J_F23 0x110
#define J_F24 0x120
#define J_F25 0x130
#define J_F26 0x140
#define J_F27 0x150
#define J_F28 0x160
#define J_F29 0x170
#define J_F30 0x180
#define J_F31 0x190
#define J_FPSR 0x1a0
#define J_B0 0x1a8
#define J_B1 0x1b0
#define J_B2 0x1b8
#define J_B3 0x1c0
#define J_B4 0x1c8
#define J_B5 0x1d0
#define TRAP_FRAME_LENGTH 0x3d0
#define C_UNAT 0x28
#define C_NATS 0x30
#define C_PFS 0x8
#define C_BSPSTORE 0x10
#define C_RNAT 0x18
#define C_RSC 0x20
#define C_PREDS 0x38
#define C_LC 0x40
#define C_DCR 0x48
#define C_R1 0x50
#define C_GP 0x50
#define C_R4 0x58
#define C_R5 0x60
#define C_R6 0x68
#define C_R7 0x70
#define C_SP 0x78
#define C_R13 0x80
#define C_F2 0x90
#define C_F3 0xa0
#define C_F4 0xb0
#define C_F5 0xc0
#define C_F16 0xd0
#define C_F17 0xe0
#define C_F18 0xf0
#define C_F19 0x100
#define C_F20 0x110
#define C_F21 0x120
#define C_F22 0x130
#define C_F23 0x140
#define C_F24 0x150
#define C_F25 0x160
#define C_F26 0x170
#define C_F27 0x180
#define C_F28 0x190
#define C_F29 0x1a0
#define C_F30 0x1b0
#define C_F31 0x1c0
#define C_FPSR 0x1d0
#define C_B0 0x1d8
#define C_B1 0x1e0
#define C_B2 0x1e8
#define C_B3 0x1f0
#define C_B4 0x1f8
#define C_B5 0x200
#define TT_R2 0x8
#define TT_R3 0x10
#define TT_R8 0x18
#define TT_R9 0x20
#define TT_R10 0x28
#define TT_R11 0x30
#define TT_R14 0x38
#endif _IA64GEN_H

94
MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
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//++
// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php.
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// Module Name:
// InternalFlushCacheRange.s
//
// Abstract:
// Assemble routine to flush cache lines
//
// Revision History:
//
//--
.file "IpfCpuCache.s"
#include <IpfMacro.i>
//
// Internal worker function to invalidate a range of instruction cache lines
// in the cache coherency domain of the calling CPU.
//
// Internal worker function to invalidate the instruction cache lines specified
// by Address and Length. If Address is not aligned on a cache line boundary,
// then entire instruction cache line containing Address is invalidated. If
// Address + Length is not aligned on a cache line boundary, then the entire
// instruction cache line containing Address + Length -1 is invalidated. This
// function may choose to invalidate the entire instruction cache if that is more
// efficient than invalidating the specified range. If Length is 0, the no instruction
// cache lines are invalidated. Address is returned.
// This function is only available on IPF.
//
// @param Address The base address of the instruction cache lines to
// invalidate. If the CPU is in a physical addressing mode, then
// Address is a physical address. If the CPU is in a virtual
// addressing mode, then Address is a virtual address.
//
// @param Length The number of bytes to invalidate from the instruction cache.
//
// @return Address
//
// VOID *
// EFIAPI
// InternalFlushCacheRange (
// IN VOID *Address,
// IN UINTN Length
// );
//
PROCEDURE_ENTRY (InternalFlushCacheRange)
NESTED_SETUP (5,8,0,0)
mov loc2 = ar.lc
mov loc3 = in0 // Start address.
mov loc4 = in1;; // Length in bytes.
cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache
(p6) br.spnt.many DoneFlushingC;;
add loc4 = loc4,loc3
mov loc5 = 1;;
sub loc4 = loc4, loc5 ;; // the End address to flush
dep loc3 = r0,loc3,0,5
dep loc4 = r0,loc4,0,5;;
shr loc3 = loc3,5
shr loc4 = loc4,5;; // 32 byte cache line
sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but
// the br.cloop will first execute one time
mov loc3 = in0
mov loc5 = 32
mov ar.lc = loc4;;
StillFlushingC:
fc loc3;;
sync.i;;
srlz.i;;
add loc3 = loc5,loc3;;
br.cloop.sptk.few StillFlushingC;;
DoneFlushingC:
mov ar.lc = loc2
mov r8 = in0 // return *Address
NESTED_RETURN
PROCEDURE_EXIT (InternalFlushCacheRange)

64
MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
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@ -1,64 +0,0 @@
/** @file
SwitchStack() function for IPF.
Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the
new stack specified by NewStack and passing in the parameters specified
by Context1 and Context2. Context1 and Context2 are optional and may
be NULL. The function EntryPoint must never return.
Marker will be ignored on IA-32, x64, and EBC.
IPF CPUs expect one additional parameter of type VOID * that specifies
the new backing store pointer.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param Marker VA_LIST marker for the variable argument list.
**/
VOID
EFIAPI
InternalSwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VA_LIST Marker
)
{
VOID *NewBsp;
//
// Get new backing store pointer from variable list
//
NewBsp = VA_ARG (Marker, VOID *);
//
// New backing store pointer should be aligned with CPU_STACK_ALIGNMENT
//
ASSERT (((UINTN)NewBsp & (CPU_STACK_ALIGNMENT - 1)) == 0);
AsmSwitchStackAndBackingStore (EntryPoint, Context1, Context2, NewStack, NewBsp);
}

121
MdePkg/Library/BaseLib/Ipf/LongJmp.s
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/// @file
/// Contains an implementation of longjmp for the Itanium-based architecture.
///
/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: longjmp.s
///
///
.auto
.text
.proc InternalLongJump
.type InternalLongJump, @function
.regstk 2, 0, 0, 0
InternalLongJump::
add r10 = 0x10*20 + 8*14, in0
movl r2 = ~((((1 << 14) - 1) << 16) | 3)
ld8.nt1 r14 = [r10], -8*2 // BSP, skip PFS
mov r15 = ar.bspstore // BSPSTORE
ld8.nt1 r17 = [r10], -8 // UNAT after spill
mov r16 = ar.rsc // RSC
cmp.leu p6 = r14, r15
ld8.nt1 r18 = [r10], -8 // UNAT
ld8.nt1 r25 = [r10], -8 // b5
and r2 = r16, r2
ldf.fill.nt1 f2 = [in0], 0x10
ld8.nt1 r24 = [r10], -8 // b4
mov b5 = r25
mov ar.rsc = r2
ld8.nt1 r23 = [r10], -8 // b3
mov b4 = r24
ldf.fill.nt1 f3 = [in0], 0x10
mov ar.unat = r17
(p6) br.spnt.many _skip_flushrs
flushrs
mov r15 = ar.bsp // New BSPSTORE
_skip_flushrs:
mov r31 = ar.rnat // RNAT
loadrs
ldf.fill.nt1 f4 = [in0], 0x10
ld8.nt1 r22 = [r10], -8
dep r2 = -1, r14, 3, 6
ldf.fill.nt1 f5 = [in0], 0x10
ld8.nt1 r21 = [r10], -8
cmp.ltu p6 = r2, r15
ld8.nt1 r20 = [r10], -0x10 // skip sp
(p6) ld8.nta r31 = [r2]
mov b3 = r23
ldf.fill.nt1 f16 = [in0], 0x10
ld8.fill.nt1 r7 = [r10], -8
mov b2 = r22
ldf.fill.nt1 f17 = [in0], 0x10
ld8.fill.nt1 r6 = [r10], -8
mov b1 = r21
ldf.fill.nt1 f18 = [in0], 0x10
ld8.fill.nt1 r5 = [r10], -8
mov b0 = r20
ldf.fill.nt1 f19 = [in0], 0x10
ld8.fill.nt1 r4 = [r10], 8*13
ldf.fill.nt1 f20 = [in0], 0x10
ld8.nt1 r19 = [r10], 0x10 // PFS
ldf.fill.nt1 f21 = [in0], 0x10
ld8.nt1 r26 = [r10], 8 // Predicate
mov ar.pfs = r19
ldf.fill.nt1 f22 = [in0], 0x10
ld8.nt1 r27 = [r10], 8 // LC
mov pr = r26, -1
ldf.fill.nt1 f23 = [in0], 0x10
ld8.nt1 r28 = [r10], -17*8 - 0x10
mov ar.lc = r27
ldf.fill.nt1 f24 = [in0], 0x10
ldf.fill.nt1 f25 = [in0], 0x10
mov r8 = in1
ldf.fill.nt1 f26 = [in0], 0x10
ldf.fill.nt1 f31 = [r10], -0x10
ldf.fill.nt1 f27 = [in0], 0x10
ldf.fill.nt1 f30 = [r10], -0x10
ldf.fill.nt1 f28 = [in0]
ldf.fill.nt1 f29 = [r10], 0x10*3 + 8*4
ld8.fill.nt1 sp = [r10]
mov ar.unat = r18
mov ar.bspstore = r14
mov ar.rnat = r31
invala
mov ar.rsc = r16
br.ret.sptk b0
.endp

109
MdePkg/Library/BaseLib/Ipf/ReadAr.s
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/// @file
/// IPF specific application register reading functions
///
/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadApplicationRegister
//
// Reads a 64-bit application register.
//
// Reads and returns the application register specified by Index.
// If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.
//
// Arguments :
//
// On Entry : The index of the application register to read.
//
// Return Value: The application register specified by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadApplicationRegister, @function
.proc AsmReadApplicationRegister
.regstk 1, 0, 0, 0
AsmReadApplicationRegister::
//
// ARs are defined in the ranges 0-44 and 64-66 (with some holes).
// Compact this list by subtracting 16 from the top range.
// 0-44, 64-66 -> 0-44, 48-50
//
mov r15=2
mov r14=pr // save predicates
cmp.leu p6,p7=64,in0 // p6 = AR# >= 64
;;
(p7) cmp.leu p7,p0=48,in0 // p7 = 32 <= AR# < 64
(p6) add in0=-16,in0 // if (AR >= 64) AR# -= 16
;;
(p7) mov r15=0 // if bad range (48-63)
;;
mov ret0=-1 // in case of illegal AR #
shl r15=r15,in0 // r15 = 0x2 << AR#
;;
mov pr=r15,-1
;;
//
// At this point the predicates contain a bit field of the
// AR desired. (The bit is the AR+1, since pr0 is always 1.)
//
.pred.rel "mutex",p1,p2,p3,p4,p5,p6,p7,p8,p17,p18,p19,p20,p22,p25,\
p26,p27,p28,p29,p30,p31,p33,p37,p41,p45,p49,p50,p51
(p1) mov ret0=ar.k0 // ar0
(p2) mov ret0=ar.k1 // ar1
(p3) mov ret0=ar.k2 // ar2
(p4) mov ret0=ar.k3 // ar3
(p5) mov ret0=ar.k4 // ar4
(p6) mov ret0=ar.k5 // ar5
(p7) mov ret0=ar.k6 // ar6
(p8) mov ret0=ar.k7 // ar7
(p17) mov ret0=ar.rsc // ar16
(p18) mov ret0=ar.bsp // ar17
(p19) mov ret0=ar.bspstore // ar18
(p20) mov ret0=ar.rnat // ar19
(p22) mov ret0=ar.fcr // ar21 [iA32]
(p25) mov ret0=ar.eflag // ar24 [iA32]
(p26) mov ret0=ar.csd // ar25 [iA32]
(p27) mov ret0=ar.ssd // ar26 [iA32]
(p28) mov ret0=ar.cflg // ar27 [iA32]
(p29) mov ret0=ar.fsr // ar28 [iA32]
(p30) mov ret0=ar.fir // ar29 [iA32]
(p31) mov ret0=ar.fdr // ar30 [iA32]
(p33) mov ret0=ar.ccv // ar32
(p37) mov ret0=ar.unat // ar36
(p41) mov ret0=ar.fpsr // ar40
(p45) mov ret0=ar.itc // ar44
//
// This is the translated (-16) range.
//
(p49) mov ret0=ar.pfs // ar64
(p50) mov ret0=ar.lc // ar65
(p51) mov ret0=ar.ec // ar66
// Restore predicates and return.
mov pr=r14,-1
br.ret.sptk b0
.endp

40
MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
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@ -1,40 +0,0 @@
/// @file
/// IPF specific AsmReadCpuid()function
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: ReadCpuid.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadCpuid
//
// This routine is used to Reads the current value of Processor Identifier Register (CPUID).
//
// Arguments :
//
// On Entry : The 8-bit Processor Identifier Register index to read.
//
// Return Value: The current value of Processor Identifier Register specified by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadCpuid, @function
.proc AsmReadCpuid
.regstk 1, 0, 0, 0
AsmReadCpuid::
mov r8 = cpuid[in0];;
br.ret.dpnt b0;;
.endp AsmReadCpuid

102
MdePkg/Library/BaseLib/Ipf/ReadCr.s
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/// @file
/// IPF specific control register reading functions
///
/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadControlRegister
//
// Reads a 64-bit control register.
//
// Reads and returns the control register specified by Index.
// If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.
//
// Arguments :
//
// On Entry : The index of the control register to read.
//
// Return Value: The control register specified by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadControlRegister, @function
.proc AsmReadControlRegister
.regstk 1, 0, 0, 0
AsmReadControlRegister::
//
// CRs are defined in the ranges 0-25 and 64-81 (with some holes).
// Compact this list by subtracting 32 from the top range.
// 0-25, 64-81 -> 0-25, 32-49
//
mov r15=2
mov r14=pr // save predicates
cmp.leu p6,p7=64,in0 // p6 = CR# >= 64
;;
(p7) cmp.leu p7,p0=32,in0 // p7 = 32 <= CR# < 64
(p6) add in0=-32,in0 // if (CR >= 64) CR# -= 32
;;
(p7) mov r15=0 // if bad range (32-63)
;;
mov ret0=-1 // in case of illegal CR #
shl r15=r15,in0 // r15 = 0x2 << CR#
;;
mov pr=r15,-1
;;
//
// At this point the predicates contain a bit field of the
// CR desired. (The bit is the CR+1, since pr0 is always 1.)
//
.pred.rel "mutex",p1,p2,p3,p9,p17,p18,p20,p21,p22,p23,p24,p25,p26,\
p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p49,p50
(p1) mov ret0=cr.dcr // cr0
(p2) mov ret0=cr.itm // cr1
(p3) mov ret0=cr.iva // cr2
(p9) mov ret0=cr.pta // cr8
(p17) mov ret0=cr.ipsr // cr16
(p18) mov ret0=cr.isr // cr17
(p20) mov ret0=cr.iip // cr19
(p21) mov ret0=cr.ifa // cr20
(p22) mov ret0=cr.itir // cr21
(p23) mov ret0=cr.iipa // cr22
(p24) mov ret0=cr.ifs // cr23
(p25) mov ret0=cr.iim // cr24
(p26) mov ret0=cr.iha // cr25
// This is the translated (-32) range.
(p33) mov ret0=cr.lid // cr64
(p34) mov ret0=cr.ivr // cr65
(p35) mov ret0=cr.tpr // cr66
(p36) mov ret0=cr.eoi // cr67
(p37) mov ret0=cr.irr0 // cr68
(p38) mov ret0=cr.irr1 // cr69
(p39) mov ret0=cr.irr2 // cr70
(p40) mov ret0=cr.irr3 // cr71
(p41) mov ret0=cr.itv // cr72
(p42) mov ret0=cr.pmv // cr73
(p43) mov ret0=cr.cmcv // cr74
(p49) mov ret0=cr.lrr0 // cr80
(p50) mov ret0=cr.lrr1 // cr81
//
// Restore predicates and return.
//
mov pr=r14,-1
br.ret.sptk b0
.endp

108
MdePkg/Library/BaseLib/Ipf/SetJmp.s
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/// @file
/// Contains an implementation of longjmp for the Itanium-based architecture.
///
/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: longjmp.s
///
///
.auto
.text
ASM_GLOBAL InternalAssertJumpBuffer
.type InternalAssertJumpBuffer, @function
.proc SetJump
.type SetJump, @function
SetJump::
alloc loc0 = ar.pfs, 1, 2, 1, 0
mov loc1 = b0
mov out0 = in0
brl.call.sptk.many b0 = InternalAssertJumpBuffer
mov r14 = ar.unat
mov r15 = ar.bsp
add r10 = 0x10*20, in0
stf.spill.nta [in0] = f2, 0x10
st8.spill.nta [r10] = r4, 8
mov r21 = b1
stf.spill.nta [in0] = f3, 0x10
st8.spill.nta [r10] = r5, 8
mov r22 = b2
stf.spill.nta [in0] = f4, 0x10
st8.spill.nta [r10] = r6, 8
mov r23 = b3
stf.spill.nta [in0] = f5, 0x10
st8.spill.nta [r10] = r7, 8
mov r24 = b4
stf.spill.nta [in0] = f16, 0x10
st8.spill.nta [r10] = sp, 8
mov r25 = b5
stf.spill.nta [in0] = f17, 0x10
st8.nta [r10] = loc1, 8
mov r16 = pr
stf.spill.nta [in0] = f18, 0x10
st8.nta [r10] = r21, 8
mov r17 = ar.lc
stf.spill.nta [in0] = f19, 0x10
st8.nta [r10] = r22, 8
stf.spill.nta [in0] = f20, 0x10
st8.nta [r10] = r23, 8
stf.spill.nta [in0] = f21, 0x10
st8.nta [r10] = r24, 8
stf.spill.nta [in0] = f22, 0x10
st8.nta [r10] = r25, 8
stf.spill.nta [in0] = f23, 0x10
mov r18 = ar.unat
stf.spill.nta [in0] = f24, 0x10
st8.nta [r10] = r14, 8 // UNAT
stf.spill.nta [in0] = f25, 0x10
st8.nta [r10] = r18, 8 // UNAT after spill
stf.spill.nta [in0] = f26, 0x10
st8.nta [r10] = loc0, 8 // PFS
stf.spill.nta [in0] = f27, 0x10
st8.nta [r10] = r15, 8 // BSP
mov r8 = 0
stf.spill.nta [in0] = f28, 0x10
mov r19 = ar.fpsr
stf.spill.nta [in0] = f29, 0x10
st8.nta [r10] = r16, 8 // PR
mov ar.pfs = loc0
stf.spill.nta [in0] = f30, 0x10
st8.nta [r10] = r17, 8 // LC
mov b0 = loc1
stf.spill.nta [in0] = f31, 0x10
st8.nta [r10] = r19 // FPSR
mov ar.unat = r14
br.ret.sptk b0
.endp SetJump

52
MdePkg/Library/BaseLib/Ipf/SwitchStack.s
View File

@ -1,52 +0,0 @@
/// @file
/// IPF specific SwitchStack() function
///
/// Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: SwitchStack.s
///
///
.auto
.text
.proc AsmSwitchStackAndBackingStore
.type AsmSwitchStackAndBackingStore, @function
.regstk 5, 0, 0, 0
AsmSwitchStackAndBackingStore::
mov r14 = ar.rsc
movl r2 = ~((((1 << 14) - 1) << 16) | 3)
mov r17 = in1
mov r18 = in2
and r2 = r14, r2
flushrs
mov ar.rsc = r2
mov sp = in3
mov r19 = in4
ld8.nt1 r16 = [in0], 8
ld8.nta gp = [in0]
mov r3 = -1
loadrs
mov ar.bspstore = r19
mov b7 = r16
alloc r2 = ar.pfs, 0, 0, 2, 0
mov out0 = r17
mov out1 = r18
mov ar.rnat = r3
mov ar.rsc = r14
br.call.sptk.many b0 = b7
.endp AsmSwitchStackAndBackingStore

243
MdePkg/Library/BaseLib/Ipf/Unaligned.c
View File

@ -1,243 +0,0 @@
/** @file
Unaligned access functions of BaseLib for IPF.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Reads a 16-bit value from memory that may be unaligned.
This function returns the 16-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer The pointer to a 16-bit value that may be unaligned.
@return The 16-bit value read from Buffer.
**/
UINT16
EFIAPI
ReadUnaligned16 (
IN CONST UINT16 *Buffer
)
{
ASSERT (Buffer != NULL);
return (UINT16)(((UINT8*)Buffer)[0] | (((UINT8*)Buffer)[1] << 8));
}
/**
Writes a 16-bit value to memory that may be unaligned.
This function writes the 16-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer The pointer to a 16-bit value that may be unaligned.
@param Value The 16-bit value to write to Buffer.
@return The 16-bit value to write to Buffer.
**/
UINT16
EFIAPI
WriteUnaligned16 (
OUT UINT16 *Buffer,
IN UINT16 Value
)
{
ASSERT (Buffer != NULL);
((UINT8*)Buffer)[0] = (UINT8)Value;
((UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
return Value;
}
/**
Reads a 24-bit value from memory that may be unaligned.
This function returns the 24-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer The pointer to a 24-bit value that may be unaligned.
@return The 24-bit value read from Buffer.
**/
UINT32
EFIAPI
ReadUnaligned24 (
IN CONST UINT32 *Buffer
)
{
ASSERT (Buffer != NULL);
return (UINT32)(
ReadUnaligned16 ((UINT16*)Buffer) |
(((UINT8*)Buffer)[2] << 16)
);
}
/**
Writes a 24-bit value to memory that may be unaligned.
This function writes the 24-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer The pointer to a 24-bit value that may be unaligned.
@param Value The 24-bit value to write to Buffer.
@return The 24-bit value to write to Buffer.
**/
UINT32
EFIAPI
WriteUnaligned24 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
*(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
return Value;
}
/**
Reads a 32-bit value from memory that may be unaligned.
This function returns the 32-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer The pointer to a 32-bit value that may be unaligned.
@return The 32-bit value read from Buffer.
**/
UINT32
EFIAPI
ReadUnaligned32 (
IN CONST UINT32 *Buffer
)
{
UINT16 LowerBytes;
UINT16 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
return (UINT32) (LowerBytes | (HigherBytes << 16));
}
/**
Writes a 32-bit value to memory that may be unaligned.
This function writes the 32-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer The pointer to a 32-bit value that may be unaligned.
@param Value The 32-bit value to write to Buffer.
@return The 32-bit value to write to Buffer.
**/
UINT32
EFIAPI
WriteUnaligned32 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
return Value;
}
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer The pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
IN CONST UINT64 *Buffer
)
{
UINT32 LowerBytes;
UINT32 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
}
/**
Writes a 64-bit value to memory that may be unaligned.
This function writes the 64-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer The pointer to a 64-bit value that may be unaligned.
@param Value The 64-bit value to write to Buffer.
@return The 64-bit value to write to Buffer.
**/
UINT64
EFIAPI
WriteUnaligned64 (
OUT UINT64 *Buffer,
IN UINT64 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
return Value;
}

2
MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
View File

@ -26,7 +26,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]

3
MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
View File

@ -10,6 +10,7 @@
#
# The implementation is also useful as a fast priority queue.
#
# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (C) 2014, Red Hat, Inc.
#
# This program and the accompanying materials are licensed and made available
@ -33,7 +34,7 @@
LIBRARY_CLASS = OrderedCollectionLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

40
MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
View File

@ -1,40 +0,0 @@
## @file
# Null instance of PAL Library with empty functions.
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BasePalLibNull
MODULE_UNI_FILE = BasePalLibNull.uni
FILE_GUID = 632D5625-B73D-43b8-AF30-8D225D96168E
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PalLib
#
# VALID_ARCHITECTURES = IPF
#
[Sources]
PalCall.c
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]
DebugLib

21
MdePkg/Library/BasePalLibNull/BasePalLibNull.uni
View File

@ -1,21 +0,0 @@
// /** @file
// Null instance of PAL Library with empty functions.
//
// Null instance of PAL Library with empty functions.
//
// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php.
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// **/
#string STR_MODULE_ABSTRACT #language en-US "Null instance of PAL Library with empty functions"
#string STR_MODULE_DESCRIPTION #language en-US "Null instance of PAL Library with empty functions."

59
MdePkg/Library/BasePalLibNull/PalCall.c
View File

@ -1,59 +0,0 @@
/** @file
Template and Sample instance of PalCallLib.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/PalLib.h>
#include <Library/DebugLib.h>
/**
Makes a PAL procedure call.
This is a wrapper function to make a PAL procedure call. Based on the Index value,
this API will make static or stacked PAL call. Architected procedures may be designated
as required or optional. If a PAL procedure is specified as optional, a unique return
code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
This indicates that the procedure is not present in this PAL implementation. It is the
caller's responsibility to check for this return code after calling any optional PAL
procedure. No parameter checking is performed on the 4 input parameters, but there are
some common rules that the caller should follow when making a PAL call. Any address
passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
may cause undefined results. For those parameters defined as reserved or some fields
defined as reserved must be zero filled or the invalid argument return value may be
returned or undefined result may occur during the execution of the procedure.
This function is only available on IPF.
@param Index The PAL procedure Index number.
@param Arg2 The 2nd parameter for PAL procedure calls.
@param Arg3 The 3rd parameter for PAL procedure calls.
@param Arg4 The 4th parameter for PAL procedure calls.
@return The structure returned from the PAL Call procedure, including the status and return value.
**/
PAL_CALL_RETURN
EFIAPI
PalCall (
IN UINT64 Index,
IN UINT64 Arg2,
IN UINT64 Arg3,
IN UINT64 Arg4
)
{
PAL_CALL_RETURN Ret;
Ret.Status = (UINT64) -1;
ASSERT (!RETURN_ERROR (RETURN_UNSUPPORTED));
return Ret;
}

2
MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
View File

@ -27,7 +27,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
View File

@ -26,7 +26,7 @@
LIBRARY_CLASS = PciCf8Lib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
View File

@ -26,7 +26,7 @@
LIBRARY_CLASS = PciExpressLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
View File

@ -26,7 +26,7 @@
LIBRARY_CLASS = PciLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
View File

@ -27,7 +27,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]

4
MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
View File

@ -3,7 +3,7 @@
#
# Default PCI Segment Information Library that shouldn't be used by real platform.
#
# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -27,7 +27,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
View File

@ -4,7 +4,7 @@
# PCI Segment Library that layers on top of the PCI Library which only
# supports segment 0 PCI configuration access.
#
# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -28,7 +28,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
View File

@ -24,7 +24,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
View File

@ -24,7 +24,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

5
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
View File

@ -33,7 +33,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
@ -43,9 +43,6 @@
[Sources.IA32, Sources.X64, Sources.EBC, Sources.AARCH64]
PeCoffLoaderEx.c
[Sources.IPF]
Ipf/PeCoffLoaderEx.c
[Sources.ARM]
Arm/PeCoffLoaderEx.c

422
MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
View File

@ -1,422 +0,0 @@
/** @file
Fixes Intel Itanium(TM) specific relocation types.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BasePeCoffLibInternals.h"
#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)
#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
*(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
#define IMM64_IMM7B_INST_WORD_X 3
#define IMM64_IMM7B_SIZE_X 7
#define IMM64_IMM7B_INST_WORD_POS_X 4
#define IMM64_IMM7B_VAL_POS_X 0
#define IMM64_IMM9D_INST_WORD_X 3
#define IMM64_IMM9D_SIZE_X 9
#define IMM64_IMM9D_INST_WORD_POS_X 18
#define IMM64_IMM9D_VAL_POS_X 7
#define IMM64_IMM5C_INST_WORD_X 3
#define IMM64_IMM5C_SIZE_X 5
#define IMM64_IMM5C_INST_WORD_POS_X 13
#define IMM64_IMM5C_VAL_POS_X 16
#define IMM64_IC_INST_WORD_X 3
#define IMM64_IC_SIZE_X 1
#define IMM64_IC_INST_WORD_POS_X 12
#define IMM64_IC_VAL_POS_X 21
#define IMM64_IMM41A_INST_WORD_X 1
#define IMM64_IMM41A_SIZE_X 10
#define IMM64_IMM41A_INST_WORD_POS_X 14
#define IMM64_IMM41A_VAL_POS_X 22
#define IMM64_IMM41B_INST_WORD_X 1
#define IMM64_IMM41B_SIZE_X 8
#define IMM64_IMM41B_INST_WORD_POS_X 24
#define IMM64_IMM41B_VAL_POS_X 32
#define IMM64_IMM41C_INST_WORD_X 2
#define IMM64_IMM41C_SIZE_X 23
#define IMM64_IMM41C_INST_WORD_POS_X 0
#define IMM64_IMM41C_VAL_POS_X 40
#define IMM64_SIGN_INST_WORD_X 3
#define IMM64_SIGN_SIZE_X 1
#define IMM64_SIGN_INST_WORD_POS_X 27
#define IMM64_SIGN_VAL_POS_X 63
/**
Performs an Itanium-based specific relocation fixup.
@param Reloc The pointer to the relocation record.
@param Fixup The pointer to the address to fix up.
@param FixupData The pointer to a buffer to log the fixups.
@param Adjust The offset to adjust the fixup.
@retval RETURN_SUCCESS Succeed to fix the relocation entry.
@retval RETURN_UNSUPPOTED Unrecoganized relocation entry.
**/
RETURN_STATUS
PeCoffLoaderRelocateImageEx (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
UINT64 *Fixup64;
UINT64 FixupVal;
switch ((*Reloc) >> 12) {
case EFI_IMAGE_REL_BASED_IA64_IMM64:
//
// Align it to bundle address before fixing up the
// 64-bit immediate value of the movl instruction.
//
Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
FixupVal = (UINT64)0;
//
// Extract the lower 32 bits of IMM64 from bundle
//
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IC_INST_WORD_X,
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
EXT_IMM64(FixupVal,
(UINT32 *)Fixup + IMM64_IMM41A_INST_WORD_X,
IMM64_IMM41A_SIZE_X,
IMM64_IMM41A_INST_WORD_POS_X,
IMM64_IMM41A_VAL_POS_X
);
//
// Update 64-bit address
//
FixupVal += Adjust;
//
// Insert IMM64 into bundle
//
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41A_INST_WORD_X),
IMM64_IMM41A_SIZE_X,
IMM64_IMM41A_INST_WORD_POS_X,
IMM64_IMM41A_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41B_INST_WORD_X),
IMM64_IMM41B_SIZE_X,
IMM64_IMM41B_INST_WORD_POS_X,
IMM64_IMM41B_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_IMM41C_INST_WORD_X),
IMM64_IMM41C_SIZE_X,
IMM64_IMM41C_INST_WORD_POS_X,
IMM64_IMM41C_VAL_POS_X
);
INS_IMM64(FixupVal,
((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),
IMM64_SIGN_SIZE_X,
IMM64_SIGN_INST_WORD_POS_X,
IMM64_SIGN_VAL_POS_X
);
Fixup64 = (UINT64 *) Fixup;
if (*FixupData != NULL) {
*FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
*(UINT64 *)(*FixupData) = *Fixup64;
*FixupData = *FixupData + sizeof(UINT64);
}
break;
default:
return RETURN_UNSUPPORTED;
}
return RETURN_SUCCESS;
}
/**
Returns TRUE if the machine type of PE/COFF image is supported. Supported
does not mean the image can be executed it means the PE/COFF loader supports
loading and relocating of the image type. It's up to the caller to support
the entry point.
The itanium version PE/COFF loader/relocater supports itanium and EBC image.
@param Machine Machine type from the PE Header.
@return TRUE if this PE/COFF loader can load the image
@return FALSE unrecoganized machine type of image.
**/
BOOLEAN
PeCoffLoaderImageFormatSupported (
IN UINT16 Machine
)
{
if ((Machine == IMAGE_FILE_MACHINE_IA64) || (Machine == IMAGE_FILE_MACHINE_EBC)) {
return TRUE;
}
return FALSE;
}
/**
ImageRead function that operates on a memory buffer whos base is passed into
FileHandle.
@param Reloc Ponter to baes of the input stream
@param Fixup Offset to the start of the buffer
@param FixupData The number of bytes to copy into the buffer
@param Adjust Location to place results of read
@retval RETURN_SUCCESS Data is read from FileOffset from the Handle into
the buffer.
@retval RETURN_UNSUPPORTED Un-recoganized relocation entry
type.
**/
RETURN_STATUS
PeHotRelocateImageEx (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
{
UINT64 *Fixup64;
UINT64 FixupVal;
switch ((*Reloc) >> 12) {
case EFI_IMAGE_REL_BASED_DIR64:
Fixup64 = (UINT64 *) Fixup;
*FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));
if (*(UINT64 *) (*FixupData) == *Fixup64) {
*Fixup64 = *Fixup64 + (UINT64) Adjust;
}
*FixupData = *FixupData + sizeof (UINT64);
break;
case EFI_IMAGE_REL_BASED_IA64_IMM64:
Fixup64 = (UINT64 *) Fixup;
*FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));
if (*(UINT64 *) (*FixupData) == *Fixup64) {
//
// Align it to bundle address before fixing up the
// 64-bit immediate value of the movl instruction.
//
//
Fixup = (CHAR8 *) ((UINT64) Fixup & (UINT64)~(15));
FixupVal = (UINT64) 0;
//
// Extract the lower 32 bits of IMM64 from bundle
//
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X,
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X,
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X,
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IC_INST_WORD_X,
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
EXT_IMM64 (
FixupVal,
(UINT32 *) Fixup + IMM64_IMM41A_INST_WORD_X,
IMM64_IMM41A_SIZE_X,
IMM64_IMM41A_INST_WORD_POS_X,
IMM64_IMM41A_VAL_POS_X
);
//
// Update 64-bit address
//
FixupVal += Adjust;
//
// Insert IMM64 into bundle
//
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X),
IMM64_IMM7B_SIZE_X,
IMM64_IMM7B_INST_WORD_POS_X,
IMM64_IMM7B_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X),
IMM64_IMM9D_SIZE_X,
IMM64_IMM9D_INST_WORD_POS_X,
IMM64_IMM9D_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X),
IMM64_IMM5C_SIZE_X,
IMM64_IMM5C_INST_WORD_POS_X,
IMM64_IMM5C_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IC_INST_WORD_X),
IMM64_IC_SIZE_X,
IMM64_IC_INST_WORD_POS_X,
IMM64_IC_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM41A_INST_WORD_X),
IMM64_IMM41A_SIZE_X,
IMM64_IMM41A_INST_WORD_POS_X,
IMM64_IMM41A_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM41B_INST_WORD_X),
IMM64_IMM41B_SIZE_X,
IMM64_IMM41B_INST_WORD_POS_X,
IMM64_IMM41B_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_IMM41C_INST_WORD_X),
IMM64_IMM41C_SIZE_X,
IMM64_IMM41C_INST_WORD_POS_X,
IMM64_IMM41C_VAL_POS_X
);
INS_IMM64 (
FixupVal,
((UINT32 *) Fixup + IMM64_SIGN_INST_WORD_X),
IMM64_SIGN_SIZE_X,
IMM64_SIGN_INST_WORD_POS_X,
IMM64_SIGN_VAL_POS_X
);
*(UINT64 *) (*FixupData) = *Fixup64;
}
*FixupData = *FixupData + sizeof (UINT64);
break;
default:
DEBUG ((EFI_D_ERROR, "PeHotRelocateEx:unknown fixed type\n"));
return RETURN_UNSUPPORTED;
}
return RETURN_SUCCESS;
}

2
MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
View File

@ -24,7 +24,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
View File

@ -27,7 +27,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#

2
MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
View File

@ -26,7 +26,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BasePrintLib/BasePrintLib.inf
View File

@ -24,7 +24,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#

4
MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
View File

@ -1,7 +1,7 @@
## @file
# Report Status Code Library with empty functions.
#
# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -25,7 +25,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
View File

@ -5,7 +5,7 @@
# resume. All the library interfaces simply return EFI_SUCCESS without
# performing any operation.
#
# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are
# licensed and made available under the terms and conditions of the BSD License
@ -31,7 +31,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
View File

@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
View File

@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
View File

@ -4,7 +4,7 @@
# S3 PCI Segment Services that perform PCI Configuration cycles and
# also enable the PCI operation to be replayed during an S3 resume.
#
# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials are
# licensed and made available under the terms and conditions of the BSD License
@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
View File

@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
View File

@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

3
MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
View File

@ -4,6 +4,7 @@
# This library provides helper functions to prevent integer overflow during
# type conversion, addition, subtraction, and multiplication.
#
# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, Microsoft Corporation
#
# All rights reserved.
@ -48,7 +49,7 @@
[Sources.Ia32, Sources.ARM]
SafeIntLib32.c
[Sources.X64, Sources.IPF, Sources.AARCH64]
[Sources.X64, Sources.AARCH64]
SafeIntLib64.c
[Sources.EBC]

4
MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
View File

@ -1,7 +1,7 @@
## @file
# Null instance of Serial Port Library with empty functions.
#
# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -24,7 +24,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
View File

@ -1,7 +1,7 @@
## @file
# Null implementation of the SMBUS Library.
#
# Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -22,7 +22,7 @@
LIBRARY_CLASS = SmbusLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

15
MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
View File

@ -24,7 +24,7 @@
LIBRARY_CLASS = SynchronizationLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
BaseSynchronizationLibInternals.h
@ -69,19 +69,6 @@
X64/GccInline.c | GCC
SynchronizationGcc.c | GCC
[Sources.IPF]
Ipf/Synchronization.c
Ipf/InterlockedCompareExchange64.s
Ipf/InterlockedCompareExchange32.s
Ipf/InterlockedCompareExchange16.s
Ipf/InternalGetSpinLockProperties.c | MSFT
Ipf/InternalGetSpinLockProperties.c | GCC
Synchronization.c | INTEL
SynchronizationMsc.c | MSFT
SynchronizationGcc.c | GCC
[Sources.EBC]
Synchronization.c
Ebc/Synchronization.c

30
MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange16.s
View File

@ -1,30 +0,0 @@
/// @file
/// Contains an implementation of InterlockedCompareExchange16 on Itanium-
/// based architecture.
///
/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
/// Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: InterlockedCompareExchange16.s
///
///
.auto
.text
.proc InternalSyncCompareExchange16
.type InternalSyncCompareExchange16, @function
InternalSyncCompareExchange16::
zxt2 r33 = r33
mov ar.ccv = r33
cmpxchg2.rel r8 = [r32], r34
mf
br.ret.sptk.many b0
.endp InternalSyncCompareExchange16

29
MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange32.s
View File

@ -1,29 +0,0 @@
/// @file
/// Contains an implementation of InterlockedCompareExchange32 on Itanium-
/// based architecture.
///
/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: InterlockedCompareExchange32.s
///
///
.auto
.text
.proc InternalSyncCompareExchange32
.type InternalSyncCompareExchange32, @function
InternalSyncCompareExchange32::
zxt4 r33 = r33
mov ar.ccv = r33
cmpxchg4.rel r8 = [r32], r34
mf
br.ret.sptk.many b0
.endp InternalSyncCompareExchange32

28
MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange64.s
View File

@ -1,28 +0,0 @@
/// @file
/// Contains an implementation of InterlockedCompareExchange64 on Itanium-
/// based architecture.
///
/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: InterlockedCompareExchange64.s
///
///
.auto
.text
.proc InternalSyncCompareExchange64
.type InternalSyncCompareExchange64, @function
InternalSyncCompareExchange64::
mov ar.ccv = r33
cmpxchg8.rel r8 = [r32], r34
mf
br.ret.sptk.many b0
.endp InternalSyncCompareExchange64

29
MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockProperties.c
View File

@ -1,29 +0,0 @@
/** @file
Internal function to get spin lock alignment.
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/**
Internal function to retrieve the architecture specific spin lock alignment
requirements for optimal spin lock performance.
@return The architecture specific spin lock alignment.
**/
UINTN
InternalGetSpinLockProperties (
VOID
)
{
return 32;
}

77
MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c
View File

@ -1,77 +0,0 @@
/** @file
Implementation of synchronization functions on Itanium.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseSynchronizationLibInternals.h"
/**
Performs an atomic increment of an 32-bit unsigned integer.
Performs an atomic increment of the 32-bit unsigned integer specified by
Value and returns the incremented value. The increment operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to increment.
@return The incremented value.
**/
UINT32
EFIAPI
InternalSyncIncrement (
IN volatile UINT32 *Value
)
{
UINT32 OriginalValue;
do {
OriginalValue = *Value;
} while (OriginalValue != InternalSyncCompareExchange32 (
Value,
OriginalValue,
OriginalValue + 1
));
return OriginalValue + 1;
}
/**
Performs an atomic decrement of an 32-bit unsigned integer.
Performs an atomic decrement of the 32-bit unsigned integer specified by
Value and returns the decrement value. The decrement operation must be
performed using MP safe mechanisms. The state of the return value is not
guaranteed to be MP safe.
@param Value A pointer to the 32-bit value to decrement.
@return The decrement value.
**/
UINT32
EFIAPI
InternalSyncDecrement (
IN volatile UINT32 *Value
)
{
UINT32 OriginalValue;
do {
OriginalValue = *Value;
} while (OriginalValue != InternalSyncCompareExchange32 (
Value,
OriginalValue,
OriginalValue - 1
));
return OriginalValue - 1;
}

2
MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
View File

@ -29,7 +29,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
View File

@ -24,7 +24,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

2
MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
View File

@ -24,7 +24,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]

2
MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
View File

@ -27,7 +27,7 @@
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]

46
MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
View File

@ -1,46 +0,0 @@
## @file
# The library implements the Extended SAL Library Class for boot service only modules.
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = DxeExtendedSalLib
MODULE_UNI_FILE = DxeExtendedSalLib.uni
FILE_GUID = 8FDED21D-7AB5-4c26-8CF7-20EC4DB9861D
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = ExtendedSalLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION
CONSTRUCTOR = DxeExtendedSalLibConstruct
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IPF
#
[Sources.IPF]
ExtendedSalLib.c
Ipf/AsmExtendedSalLib.s
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]
UefiBootServicesTableLib
[Protocols]
gEfiExtendedSalBootServiceProtocolGuid ## CONSUMES
[Depex.common.DXE_DRIVER]
gEfiExtendedSalBootServiceProtocolGuid

21
MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.uni
View File

@ -1,21 +0,0 @@
// /** @file
// The library implements the Extended SAL Library Class for boot service only modules.
//
// This library implements the Extended SAL Library Class for boot service only modules.
//
// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php.
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// **/
#string STR_MODULE_ABSTRACT #language en-US "Implements the Extended SAL Library Class for boot service only modules"
#string STR_MODULE_DESCRIPTION #language en-US "This library implements the Extended SAL Library Class for boot service only modules."

1001
MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c
View File

File diff suppressed because it is too large Load Diff

97
MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s
View File

@ -1,97 +0,0 @@
/// @file
/// Assembly procedures to get and set ESAL entry point.
///
/// Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
.auto
.text
#include "IpfMacro.i"
//
// Exports
//
ASM_GLOBAL GetEsalEntryPoint
//-----------------------------------------------------------------------------
//++
// GetEsalEntryPoint
//
// Return Esal global and PSR register.
//
// On Entry :
//
//
// Return Value:
// r8 = EFI_SAL_SUCCESS
// r9 = Physical Plabel
// r10 = Virtual Plabel
// r11 = psr
//
// As per static calling conventions.
//
//--
//---------------------------------------------------------------------------
PROCEDURE_ENTRY (GetEsalEntryPoint)
NESTED_SETUP (0,8,0,0)
EsalCalcStart:
mov r8 = ip;;
add r8 = (EsalEntryPoint - EsalCalcStart), r8;;
mov r9 = r8;;
add r10 = 0x10, r8;;
mov r11 = psr;;
mov r8 = r0;;
NESTED_RETURN
PROCEDURE_EXIT (GetEsalEntryPoint)
//-----------------------------------------------------------------------------
//++
// SetEsalPhysicalEntryPoint
//
// Set the dispatcher entry point
//
// On Entry:
// in0 = Physical address of Esal Dispatcher
// in1 = Physical GP
//
// Return Value:
// r8 = EFI_SAL_SUCCESS
//
// As per static calling conventions.
//
//--
//---------------------------------------------------------------------------
PROCEDURE_ENTRY (SetEsalPhysicalEntryPoint)
NESTED_SETUP (2,8,0,0)
EsalCalcStart1:
mov r8 = ip;;
add r8 = (EsalEntryPoint - EsalCalcStart1), r8;;
st8 [r8] = in0;;
add r8 = 0x08, r8;;
st8 [r8] = in1;;
mov r8 = r0;;
NESTED_RETURN
PROCEDURE_EXIT (SetEsalPhysicalEntryPoint)
.align 32
EsalEntryPoint:
data8 0 // Physical Entry
data8 0 // GP
data8 0 // Virtual Entry
data8 0 // GP

4
MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
View File

@ -22,14 +22,14 @@
FILE_GUID = f773469b-e265-4b0c-b0a6-2f971fbfe72b
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = ExtractGuidedSectionLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
LIBRARY_CLASS = ExtractGuidedSectionLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
CONSTRUCTOR = DxeExtractGuidedSectionLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
MdePkg/Library/DxeHobLib/DxeHobLib.inf
View File

@ -23,11 +23,11 @@
FILE_GUID = f12b59c9-76d0-4661-ad7c-f04d1bef0558
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
CONSTRUCTOR = HobLibConstructor
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

4
MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
View File

@ -1,7 +1,7 @@
## @file
# DXE instance of Hsti Library.
#
# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -19,7 +19,7 @@
FILE_GUID = 7DE1C620-F587-4116-A36D-40F3467B9A0C
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = HstiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
LIBRARY_CLASS = HstiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
[Sources]
HstiAip.c

4
MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
View File

@ -22,13 +22,13 @@
FILE_GUID = 33D33BF3-349E-4768-9459-836A9F7558FB
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = IoLib|DXE_DRIVER DXE_SAL_DRIVER
LIBRARY_CLASS = IoLib|DXE_DRIVER
CONSTRUCTOR = IoLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]

49
MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
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@ -1,49 +0,0 @@
## @file
# I/O Library instance that layers on top of Itanium ESAL services.
#
# I/O Library implementation that uses Itanium ESAL services for I/O
# and MMIO operations.
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials are licensed and made available
# under the terms and conditions of the BSD License which accompanies this
# distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = DxeIoLibEsal
MODULE_UNI_FILE = DxeIoLibEsal.uni
FILE_GUID = 0D8E6E4E-B029-475f-9122-60A3FEDBA8C0
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = IoLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IPF
#
[Sources]
IoHighLevel.c
IoLib.c
IoLibMmioBuffer.c
DxeIoLibEsalInternal.h
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]
ExtendedSalLib
BaseLib
DebugLib
[Depex]
gEfiExtendedSalBaseIoServicesProtocolGuid

23
MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.uni
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@ -1,23 +0,0 @@
// /** @file
// I/O Library instance that layers on top of Itanium ESAL services.
//
// I/O Library implementation that uses Itanium ESAL services for I/O
// and MMIO operations.
//
// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
//
// This program and the accompanying materials are licensed and made available
// under the terms and conditions of the BSD License which accompanies this
// distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php.
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// **/
#string STR_MODULE_ABSTRACT #language en-US "I/O Library instance that layers on top of Itanium ESAL services"
#string STR_MODULE_DESCRIPTION #language en-US "I/O Library implementation that uses Itanium ESAL services for I/O and MMIO operations."

28
MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h
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@ -1,28 +0,0 @@
/** @file
Internal include file for the I/O Library using ESAL services.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __DXE_IO_LIB_ESAL_INTERNAL_H_
#define __DXE_IO_LIB_ESAL_INTERNAL_H_
#include <PiDxe.h>
#include <Protocol/CpuIo2.h>
#include <Protocol/ExtendedSalServiceClasses.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseLib.h>
#include <Library/ExtendedSalLib.h>
#endif

2303
MdePkg/Library/DxeIoLibEsal/IoHighLevel.c
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