Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

https://svn.code.sf.net/p/edk2/code/trunk/edk2/, 

which are for MinnowBoard MAX open source project.


Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL

@@ -0,0 +1,623 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  2012  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+
+// Use this information when determining the Possible IRQs that can be
+// used in a given system.
+//
+// The following IRQs are always in use by legacy devices:
+//              0  = System Timer
+//              2  = 8259 PIC
+//              8  = RTC
+//              9  = SCI Interrupt (It may be used, we choose not to)
+//              13 = Co-processor Error
+//
+// The following may be in use by legacy devices:
+//              1  = If using PS/2 Keyboard
+//              3  = If COMx Port Enabled and IRQ = 3
+//              4  = If COMx Port Enabled and IRQ = 4
+//              5  = If LPT Port Enabled and IRQ = 5
+//              6  = If FDC Enabled
+//              7  = If LPT Port Enabled and IRQ = 7
+//              12 = If using PS/2 Mouse
+//              14 = Primary IDE (If populated and in Compatibility Mode)
+//              15 = Secondary IDE (If populated and in Compatibility Mode)
+//
+// The following will never be in use by legacy devices:
+//              10 = Assign to PARC, PCRC, PERC, PGRC
+//              11 = Assign to PBRC, PDRC, PFRC, PHRC
+
+Device(LNKA)                            // PARC Routing Resource
+{
+  Name(_HID,EISAID("PNP0C0F"))    // PCI Interrupt Link Device
+
+  Name(_UID,1)                    // Unique to other Link Devices
+
+  // Disable the PCI IRQ.
+
+  Method(_DIS,0,Serialized)
+  {
+    Or(PARC,0x80,PARC)
+  }
+
+  // Possible IRQ Resource Setting.
+
+  Method (_PRS, 0, Serialized)
+  {
+    return (PRSA)
+  }
+
+  // Current IRQ Resource Setting.
+
+  Method(_CRS,0,Serialized)
+  {
+    Name(RTLA,ResourceTemplate()
+    {
+      IRQ(Level,ActiveLow,Shared) {}
+    })
+
+    // Point to specific byte.
+
+    CreateWordField(RTLA,1,IRQ0)
+
+    // Zero out IRQ mask bits 0-15
+
+    Store(Zero,IRQ0)
+
+    ShiftLeft(1,And(PARC,0x0F),IRQ0)
+
+    Return(RTLA)
+  }
+
+  // Set IRQ Resource Setting.
+
+  Method(_SRS,1,Serialized)
+  {
+    // Point to the specific byte passed in
+
+    CreateWordField(Arg0,1,IRQ0)
+
+    // Determine the IRQ bit to set and store it
+
+    FindSetRightBit(IRQ0,Local0)
+    Decrement(Local0)
+    Store(Local0,PARC)
+  }
+
+  // PCI IRQ Status.
+
+  Method(_STA,0,Serialized)
+  {
+    If(And(PARC,0x80))
+    {
+      Return(0x0009)
+    }
+    Else
+    {
+      Return(0x000B)
+    }
+  }
+}
+
+Device(LNKB)                            // PBRC Routing Resource
+{
+  Name(_HID,EISAID("PNP0C0F"))
+
+  Name(_UID,2)
+
+  // Disable the PCI IRQ.
+
+  Method(_DIS,0,Serialized)
+  {
+    Or(PBRC,0x80,PBRC)
+  }
+
+  // Possible IRQ Resource Setting.
+
+  Method (_PRS, 0, Serialized)
+  {
+    return (PRSB)
+  }
+
+  // Current IRQ Resource Setting.
+
+  Method(_CRS,0,Serialized)
+  {
+    Name(RTLB,ResourceTemplate()
+    {
+      IRQ(Level,ActiveLow,Shared) {}
+    })
+
+    // Point to specific byte.
+
+    CreateWordField(RTLB,1,IRQ0)
+
+    // Zero out IRQ mask bits 0-15
+
+    Store(Zero,IRQ0)
+
+    ShiftLeft(1,And(PBRC,0x0F),IRQ0)
+
+    Return(RTLB)
+  }
+
+  // Set IRQ Resource Setting.
+
+  Method(_SRS,1,Serialized)
+  {
+    // Point to the specific byte passed in.
+
+    CreateWordField(Arg0,1,IRQ0)
+
+    // Determine the IRQ bit to set and store it,
+
+    FindSetRightBit(IRQ0,Local0)
+    Decrement(Local0)
+    Store(Local0,PBRC)
+  }
+
+  // PCI IRQ Status.
+
+  Method(_STA,0,Serialized)
+  {
+    If(And(PBRC,0x80))
+    {
+      Return(0x0009)
+    }
+    Else
+    {
+      Return(0x000B)
+    }
+  }
+}
+
+Device(LNKC)                            // PCRC Routing Resource
+{
+  Name(_HID,EISAID("PNP0C0F"))
+
+  Name(_UID,3)
+
+  // Disable the PCI IRQ.
+
+  Method(_DIS,0,Serialized)
+  {
+    Or(PCRC,0x80,PCRC)
+  }
+
+  // Possible IRQ Resource Setting.
+
+  Method (_PRS, 0, Serialized)
+  {
+    return (PRSC)
+  }
+
+  // Current IRQ Resource Setting.
+
+  Method(_CRS,0,Serialized)
+  {
+    Name(RTLC,ResourceTemplate()
+    {
+      IRQ(Level,ActiveLow,Shared) {}
+    })
+
+    // Point to specific byte.
+
+    CreateWordField(RTLC,1,IRQ0)
+
+    // Zero out IRQ mask bits 0-15
+
+    Store(Zero,IRQ0)
+
+    ShiftLeft(1,And(PCRC,0x0F),IRQ0)
+
+    Return(RTLC)
+  }
+
+  // Set IRQ Resource Setting.
+
+  Method(_SRS,1,Serialized)
+  {
+    // Point to the specific byte passed in.
+
+    CreateWordField(Arg0,1,IRQ0)
+
+    // Determine the IRQ bit to set and store it,
+
+    FindSetRightBit(IRQ0,Local0)
+    Decrement(Local0)
+    Store(Local0,PCRC)
+  }
+
+  // PCI IRQ Status.
+
+  Method(_STA,0,Serialized)
+  {
+    If(And(PCRC,0x80))
+    {
+      Return(0x0009)
+    }
+    Else
+    {
+      Return(0x000B)
+    }
+  }
+}
+
+Device(LNKD)                            // PDRC Routing Resource
+{
+  Name(_HID,EISAID("PNP0C0F"))
+
+  Name(_UID,4)
+
+  // Disable the PCI IRQ.
+
+  Method(_DIS,0,Serialized)
+  {
+    Or(PDRC,0x80,PDRC)
+  }
+
+  // Possible IRQ Resource Setting.
+
+  Method (_PRS, 0, Serialized)
+  {
+    return (PRSD)
+  }
+
+  // Current IRQ Resource Setting.
+
+  Method(_CRS,0,Serialized)
+  {
+    Name(RTLD,ResourceTemplate()
+    {
+      IRQ(Level,ActiveLow,Shared) {}
+    })
+
+    // Point to specific byte.
+
+    CreateWordField(RTLD,1,IRQ0)
+
+    // Zero out IRQ mask bits 0-15
+
+    Store(Zero,IRQ0)
+
+    ShiftLeft(1,And(PDRC,0x0F),IRQ0)
+
+    Return(RTLD)
+  }
+
+  // Set IRQ Resource Setting.
+
+  Method(_SRS,1,Serialized)
+  {
+    // Point to the specific byte passed in.
+
+    CreateWordField(Arg0,1,IRQ0)
+
+    // Determine the IRQ bit to set and store it,
+
+    FindSetRightBit(IRQ0,Local0)
+    Decrement(Local0)
+    Store(Local0,PDRC)
+  }
+
+  // PCI IRQ Status.
+
+  Method(_STA,0,Serialized)
+  {
+    If(And(PDRC,0x80))
+    {
+      Return(0x0009)
+    }
+    Else
+    {
+      Return(0x000B)
+    }
+  }
+}
+
+Device(LNKE)                            // PERC Routing Resource
+{
+  Name(_HID,EISAID("PNP0C0F"))
+
+  Name(_UID,5)
+
+  // Disable the PCI IRQ.
+
+  Method(_DIS,0,Serialized)
+  {
+    Or(PERC,0x80,PERC)
+  }
+
+  // Possible IRQ Resource Setting.
+
+  Method (_PRS, 0, Serialized)
+  {
+    return (PRSE)
+  }
+
+  // Current IRQ Resource Setting.
+
+  Method(_CRS,0,Serialized)
+  {
+    Name(RTLE,ResourceTemplate()
+    {
+      IRQ(Level,ActiveLow,Shared) {}
+    })
+
+    // Point to specific byte.
+
+    CreateWordField(RTLE,1,IRQ0)
+
+    // Zero out IRQ mask bits 0-15
+
+    Store(Zero,IRQ0)
+
+    ShiftLeft(1,And(PERC,0x0F),IRQ0)
+
+    Return(RTLE)
+  }
+
+  // Set IRQ Resource Setting.
+
+  Method(_SRS,1,Serialized)
+  {
+    // Point to the specific byte passed in
+
+    CreateWordField(Arg0,1,IRQ0)
+
+    // Determine the IRQ bit to set and store it
+
+    FindSetRightBit(IRQ0,Local0)
+    Decrement(Local0)
+    Store(Local0,PERC)
+  }
+
+  // PCI IRQ Status.
+
+  Method(_STA,0,Serialized)
+  {
+    If(And(PERC,0x80))
+    {
+      Return(0x0009)
+    }
+    Else
+    {
+      Return(0x000B)
+    }
+  }
+}
+
+Device(LNKF)                            // PFRC Routing Resource
+{
+  Name(_HID,EISAID("PNP0C0F"))
+
+  Name(_UID,6)
+
+  // Disable the PCI IRQ.
+
+  Method(_DIS,0,Serialized)
+  {
+    Or(PFRC,0x80,PFRC)
+  }
+
+  // Possible IRQ Resource Setting.
+
+  Method (_PRS, 0, Serialized)
+  {
+    return (PRSF)
+  }
+
+  // Current IRQ Resource Setting.
+
+  Method(_CRS,0,Serialized)
+  {
+    Name(RTLF,ResourceTemplate()
+    {
+      IRQ(Level,ActiveLow,Shared) {}
+    })
+
+    // Point to specific byte.
+
+    CreateWordField(RTLF,1,IRQ0)
+
+    // Zero out IRQ mask bits 0-15
+
+    Store(Zero,IRQ0)
+
+    ShiftLeft(1,And(PFRC,0x0F),IRQ0)
+
+    Return(RTLF)
+  }
+
+  // Set IRQ Resource Setting.
+
+  Method(_SRS,1,Serialized)
+  {
+    // Point to the specific byte passed in.
+
+    CreateWordField(Arg0,1,IRQ0)
+
+    // Determine the IRQ bit to set and store it,
+
+    FindSetRightBit(IRQ0,Local0)
+    Decrement(Local0)
+    Store(Local0,PFRC)
+  }
+
+  // PCI IRQ Status.
+
+  Method(_STA,0,Serialized)
+  {
+    If(And(PFRC,0x80))
+    {
+      Return(0x0009)
+    }
+    Else
+    {
+      Return(0x000B)
+    }
+  }
+}
+
+Device(LNKG)                            // PGRC Routing Resource
+{
+  Name(_HID,EISAID("PNP0C0F"))
+
+  Name(_UID,7)
+
+  // Disable the PCI IRQ.
+
+  Method(_DIS,0,Serialized)
+  {
+    Or(PGRC,0x80,PGRC)
+  }
+
+  // Possible IRQ Resource Setting.
+
+  Method (_PRS, 0, Serialized)
+  {
+    return (PRSG)
+  }
+
+  // Current IRQ Resource Setting.
+
+  Method(_CRS,0,Serialized)
+  {
+    Name(RTLG,ResourceTemplate()
+    {
+      IRQ(Level,ActiveLow,Shared) {}
+    })
+
+    // Point to specific byte.
+
+    CreateWordField(RTLG,1,IRQ0)
+
+    // Zero out IRQ mask bits 0-15
+
+    Store(Zero,IRQ0)
+
+    ShiftLeft(1,And(PGRC,0x0F),IRQ0)
+
+    Return(RTLG)
+  }
+
+  // Set IRQ Resource Setting.
+
+  Method(_SRS,1,Serialized)
+  {
+    // Point to the specific byte passed in.
+
+    CreateWordField(Arg0,1,IRQ0)
+
+    // Determine the IRQ bit to set and store it,
+
+    FindSetRightBit(IRQ0,Local0)
+    Decrement(Local0)
+    Store(Local0,PGRC)
+  }
+
+  // PCI IRQ Status.
+
+  Method(_STA,0,Serialized)
+  {
+    If(And(PGRC,0x80))
+    {
+      Return(0x0009)
+    }
+    Else
+    {
+      Return(0x000B)
+    }
+  }
+}
+
+Device(LNKH)                            // PHRC Routing Resource
+{
+  Name(_HID,EISAID("PNP0C0F"))
+
+  Name(_UID,8)
+
+  // Disable the PCI IRQ.
+
+  Method(_DIS,0,Serialized)
+  {
+    Or(PHRC,0x80,PHRC)
+  }
+
+  // Possible IRQ Resource Setting.
+
+  Method (_PRS, 0, Serialized)
+  {
+    return (PRSH)
+  }
+
+  // Current IRQ Resource Setting.
+
+  Method(_CRS,0,Serialized)
+  {
+    Name(RTLH,ResourceTemplate()
+    {
+      IRQ(Level,ActiveLow,Shared) {}
+    })
+
+    // Point to specific byte.
+
+    CreateWordField(RTLH,1,IRQ0)
+
+    // Zero out IRQ mask bits 0-15
+
+    Store(Zero,IRQ0)
+
+    ShiftLeft(1,And(PHRC,0x0F),IRQ0)
+
+    Return(RTLH)
+  }
+
+  // Set IRQ Resource Setting.
+
+  Method(_SRS,1,Serialized)
+  {
+    // Point to the specific byte passed in.
+
+    CreateWordField(Arg0,1,IRQ0)
+
+    // Determine the IRQ bit to set and store it,
+
+    FindSetRightBit(IRQ0,Local0)
+    Decrement(Local0)
+    Store(Local0,PHRC)
+  }
+
+  // PCI IRQ Status.
+
+  Method(_STA,0,Serialized)
+  {
+    If(And(PHRC,0x80))
+    {
+      Return(0x0009)
+    }
+    Else
+    {
+      Return(0x000B)
+    }
+  }
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h

@@ -0,0 +1,76 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  AcpiTablePlatform.h
+
+
+Abstract: File contains platform specific ACPI defines for use in ACPI tables
+
+
+--*/
+#ifndef _Platform_h_INCLUDED_
+#define _Platform_h_INCLUDED_
+
+#ifdef ECP_FLAG
+#include "EdkIIGlueDxe.h"
+#endif
+#include <IndustryStandard/Acpi.h>
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_OEM_ID           'O','E','M','I','D',' '   // OEMID 6 bytes long
+#define EFI_ACPI_OEM_TABLE_ID     SIGNATURE_64('O','E','M','T','A','B','L','E') // OEM table id 8 bytes long
+#define EFI_ACPI_OEM_REVISION     0x00000005
+#define EFI_ACPI_CREATOR_ID       SIGNATURE_32('C','R','E','A')
+#define EFI_ACPI_CREATOR_REVISION 0x0100000D
+#define INT_MODEL       0x01
+#define PM_PROFILE      EFI_ACPI_4_0_PM_PROFILE_MOBILE
+#define SCI_INT_VECTOR  0x0009
+#define SMI_CMD_IO_PORT 0x000000B2
+#define ACPI_ENABLE     0x0A0
+#define ACPI_DISABLE    0x0A1
+#define S4BIOS_REQ      0x00
+#define PSTATE_CNT      0x00
+#define PM1a_EVT_BLK    0x00000400
+#define PM1b_EVT_BLK    0x00000000
+#define PM1a_CNT_BLK    0x00000404
+#define PM1b_CNT_BLK    0x00000000
+#define PM2_CNT_BLK     0x00000450
+#define PM_TMR_BLK      0x00000408
+#define GPE0_BLK        0x00000420
+#define GPE1_BLK        0x00000000
+#define PM1_EVT_LEN     0x04
+#define PM1_CNT_LEN     0x02
+#define PM2_CNT_LEN     0x01
+#define PM_TM_LEN       0x04
+#define GPE0_BLK_LEN    0x10
+#define GPE1_BLK_LEN    0x00
+#define GPE1_BASE       0x00
+#define CST_CNT         0x00
+#define P_LVL2_LAT      0x0064
+#define P_LVL3_LAT      0x01F4
+#define FLUSH_SIZE      0x0400
+#define FLUSH_STRIDE    0x0010
+#define DUTY_OFFSET     0x01
+#define DUTY_WIDTH      0x03
+#define DAY_ALRM        0x0D
+#define MON_ALRM        0x00
+#define CENTURY         0x32
+#define FLAG            ( EFI_ACPI_4_0_WBINVD | EFI_ACPI_4_0_SLP_BUTTON | EFI_ACPI_4_0_RESET_REG_SUP | EFI_ACPI_4_0_RTC_S4)
+#define IAPC_BOOT_ARCH  ( EFI_ACPI_4_0_VGA_NOT_PRESENT | EFI_ACPI_4_0_8042 | EFI_ACPI_4_0_LEGACY_DEVICES)
+#define RESERVED        0x00
+
+#endif

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf

@@ -0,0 +1,44 @@
+## @file
+# Component description file for PlatformAcpiTable module.
+#
+# Build acpi table data required by system boot.
+#  All .asi files tagged with "ToolCode="DUMMY"" in following file list are device description and are included
+#  by top level ASL file which will be dealed with by asl.exe application.
+#
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#
+##
+
+[defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  EDK_RELEASE_VERSION            = 0x00020000
+  EFI_SPECIFICATION_VERSION      = 0x00020000
+
+[sources.common]
+  DSDT.ASL
+  Facs/Facs.aslc
+  Facp/Facp.aslc
+  Madt/Madt30.aslc
+  Mcfg/Mcfg.aslc
+  Hpet/Hpet.aslc
+  Lpit/Lpit.aslc
+
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Vlv2TbltDevicePkg/PlatformPkg.dec
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl

@@ -0,0 +1,55 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+
+// NOTE:  The _PDC Implementation is out of the scope of this
+// reference code.  Please see the latest Hyper-Threading Technology
+// Reference Code for complete implementation details.
+
+Scope(\_PR)
+{
+  Processor(CPU0,         // Unique name for Processor 0.
+            1,                        // Unique ID for Processor 0.
+            0x00,                 // CPU0 ACPI P_BLK address = ACPIBASE + 10h.
+            0)                        // CPU0  P_BLK length = 6 bytes.
+  {}
+
+  Processor(CPU1,         // Unique name for Processor 1.
+            2,                        // Unique ID for Processor 1.
+            0x00,
+            0)                    // CPU1 P_BLK length = 6 bytes.
+  {}
+
+  Processor(CPU2,         // Unique name for Processor 2.
+            3,                        // Unique ID for Processor 2.
+            0x00,
+            0)                    // CPU2 P_BLK length = 6 bytes.
+  {}
+
+  Processor(CPU3,         // Unique name for Processor 3.
+            4,                        // Unique ID for Processor 3.
+            0x00,
+            0)                    // CPU3 P_BLK length = 6 bytes.
+  {}
+}     // End _PR
+
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL

@@ -0,0 +1,81 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+DefinitionBlock (
+  "DSDT.aml",
+  "DSDT",
+  0x02,  // DSDT revision.
+  "OEMID", // OEM ID (6 byte string)
+  "VLV-SOC", // OEM table ID  (8 byte string)
+  0x0 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+  External(MDBG, MethodObj)
+
+  Method(ADBG, 1, Serialized)
+  {
+
+    If(CondRefOf(MDBG))   //check if SSDT is loaded
+    {
+      Return(MDBG(Arg0))
+    }
+
+    Return(0)
+  }
+
+
+// Miscellaneous services enabled in Project
+  include ("token.asl")
+  include ("GloblNvs.asl")
+  include ("PciTree.asl")
+  include ("Pch.asl")
+  include ("Vlv.asl")
+  include ("CPU.asl")
+  include ("Platform.asl")
+  include ("THERMAL.ASL")
+  include ("PCI_DRC.ASL")
+  include ("Video.asl")
+  include ("Gpe.asl")
+  include ("IoTVirtualDevice.asl")
+
+  // Sleep states supported by Chipset/Board.
+  // SSx - BIOS setup controlled enabled _Sx Sleep state status
+  // Values to be written to SLP_TYPE register are provided by SBACPI.SDL (South Bridge ACPI ModulePart)
+
+  Name(\_S0, Package(4) {0x0,0x0,0,0}) // mandatory System state
+  Name(\_S1, Package(4) {0x1,0x0,0,0})
+  Name(\_S3, Package(4) {0x5,0x0,0,0})
+  Name(\_S4, Package(4) {0x6,0x0,0,0})
+  Name(\_S5, Package(4) {0x7,0x0,0,0}) // mandatory System state
+
+  Method(PTS, 1)          // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE
+  {
+    If(Arg0)            // entering any sleep state
+    {
+    }
+  }
+  Method(WAK, 1)          // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP
+  {
+  }
+
+}// End of ASL File

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc

@@ -0,0 +1,194 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  Facp.c
+
+
+Abstract: The fixed ACPI description Table (FADT) Structure
+
+
+--*/
+#ifdef ECP_FLAG
+#include "EDKIIGlueDxe.h"
+#else
+#include <PiDxe.h>
+#endif
+#include <IndustryStandard/Acpi50.h>
+#include "AcpiTablePlatform.h"
+
+EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
+  {
+    EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),
+    EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+    0,                                                                                    // to make sum of entire table == 0
+    EFI_ACPI_OEM_ID,         // OEMID is a 6 bytes long field
+    EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)
+    EFI_ACPI_OEM_REVISION,      // OEM revision number
+    EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID
+    EFI_ACPI_CREATOR_REVISION   // ASL compiler revision number
+  },
+  0,                                                                                    // Physical addesss of FACS
+  0,                                                                                    // Physical address of DSDT
+  INT_MODEL,                                                                                    // System Interrupt Model (ignored in 2k and later, must be 0 for 98)
+  PM_PROFILE,                                                                                   // Preferred PM Profile
+  SCI_INT_VECTOR,                                                                       // System vector of SCI interrupt
+  SMI_CMD_IO_PORT,                                                                      // Port address of SMI command port
+  ACPI_ENABLE,                                                                          // value to write to port smi_cmd to enable ACPI
+  ACPI_DISABLE,                                                                         // value to write to port smi_cmd to disable ACPI
+  S4BIOS_REQ,                                                                           // Value to write to SMI CMD port to enter the S4BIOS state
+  PSTATE_CNT,       // PState control
+  PM1a_EVT_BLK,                                                                         // Port address of Power Mgt 1a Event Reg Blk
+  PM1b_EVT_BLK,                                                                         // Port address of Power Mgt 1b Event Reg Blk
+  PM1a_CNT_BLK,                                                                         // Port address of Power Mgt 1a Ctrl Reg Blk
+  PM1b_CNT_BLK,                                                                         // Port address of Power Mgt 1b Ctrl Reg Blk
+  PM2_CNT_BLK,                                                                          // Port address of Power Mgt 2  Ctrl Reg Blk
+  PM_TMR_BLK,                                                                           // Port address of Power Mgt Timer Ctrl Reg Blk
+  GPE0_BLK,                                                                             // Port addr of General Purpose Event 0 Reg Blk
+  GPE1_BLK,                                                                             // Port addr of General Purpose Event 1 Reg Blk
+  PM1_EVT_LEN,                                                                          // Byte Length of ports at pm1X_evt_blk
+  PM1_CNT_LEN,                                                                          // Byte Length of ports at pm1X_cnt_blk
+  PM2_CNT_LEN,                                                                          // Byte Length of ports at pm2_cnt_blk
+  PM_TM_LEN,                                                                            // Byte Length of ports at pm_tm_blk
+  GPE0_BLK_LEN,                                                                         // Byte Length of ports at gpe0_blk
+  GPE1_BLK_LEN,                                                                         // Byte Length of ports at gpe1_blk
+  GPE1_BASE,                                                                            // offset in gpe model where gpe1 events start
+  CST_CNT,          // _CST support
+  P_LVL2_LAT,                                                                           // worst case HW latency to enter/exit C2 state
+  P_LVL3_LAT,                                                                           // worst case HW latency to enter/exit C3 state
+  FLUSH_SIZE,                                                                           // Size of area read to flush caches
+  FLUSH_STRIDE,                                                                         // Stride used in flushing caches
+  DUTY_OFFSET,                                                                          // bit location of duty cycle field in p_cnt reg
+  DUTY_WIDTH,                                                                           // bit width of duty cycle field in p_cnt reg
+  DAY_ALRM,                                                                             // index to day-of-month alarm in RTC CMOS RAM
+  MON_ALRM,                                                                             // index to month-of-year alarm in RTC CMOS RAM
+  CENTURY,                                                                              // index to century in RTC CMOS RAM
+  IAPC_BOOT_ARCH,                                                                       // IA-PCI Boot Architecture Flag
+  RESERVED,                                                                             // reserved
+  FLAG,
+  {
+    EFI_ACPI_5_0_SYSTEM_IO,
+    8,
+    0,
+    0,
+    0xCF9
+  },
+  0x06,             // Hardware reset value
+  0, 0, 0,          // Reserved
+  0,                // XFirmwareCtrl
+  0,                // XDsdt
+  //
+  // X_PM1a Event Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x20,
+  0x00,
+  EFI_ACPI_3_0_DWORD,
+  PM1a_EVT_BLK,
+
+  //
+  // X_PM1b Event Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x00,
+  0x00,
+  EFI_ACPI_RESERVED_BYTE,
+  PM1b_EVT_BLK,
+
+  //
+  // X_PM1a Control Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x10,
+  0x00,
+  EFI_ACPI_3_0_WORD,
+  PM1a_CNT_BLK,
+
+  //
+  // X_PM1b Control Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x00,
+  0x00,
+  EFI_ACPI_RESERVED_BYTE,
+  PM1b_CNT_BLK,
+
+  //
+  // X_PM2 Control Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x08,
+  0x00,
+  EFI_ACPI_3_0_BYTE,
+  PM2_CNT_BLK,
+
+  //
+  // X_PM Timer Control Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x20,
+  0x00,
+  EFI_ACPI_3_0_DWORD,
+  PM_TMR_BLK,
+
+  //
+  // X_General Purpose Event 0 Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x80,
+  0x00,
+  EFI_ACPI_RESERVED_BYTE,
+  GPE0_BLK,
+
+  //
+  // X_General Purpose Event 1 Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x00,
+  0x00,
+  EFI_ACPI_RESERVED_BYTE,
+  GPE1_BLK,
+
+  //
+  // Sleep Control Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x08,
+  0x00,
+  EFI_ACPI_RESERVED_BYTE,
+  0,
+
+  //
+  // Sleep Status Register Block
+  //
+  EFI_ACPI_5_0_SYSTEM_IO,
+  0x08,
+  0x00,
+  EFI_ACPI_RESERVED_BYTE,
+  0,
+};
+
+VOID*
+ReferenceAcpiTable (
+  VOID
+  )
+{
+  //
+  // Reference the table being generated to prevent the optimizer from
+  // removing the data structure from the executable
+  //
+  return (VOID*)&FACP;
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc

@@ -0,0 +1,90 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  Ea815acpiFACS.c
+
+
+Abstract:
+
+  This file contains the FACS structure definition.
+
+--*/
+
+//
+// Statements that include other files
+//
+#ifdef ECP_FLAG
+#include "EDKIIGlueDxe.h"
+#else
+#include <PiDxe.h>
+#endif
+#include <IndustryStandard/Acpi50.h>
+#include "AcpiTablePlatform.h"
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = {
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
+  sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),
+
+  //
+  // Hardware Signature will be updated at runtime
+  //
+  0x00000000,                  //HardwareSignature
+  0x00000000,                  //FirmwareWakingVector
+  0x00000000,                  //GlobalLock
+  0x00000000,                  //Flags
+  0x0000000000000000,          //XFirmwareWakingVector
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
+  EFI_ACPI_RESERVED_BYTE,      //Reserved0[3]
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  0x00000000,                  //OspmFlags
+  EFI_ACPI_RESERVED_BYTE,      //Reserved1[24]
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE,
+  EFI_ACPI_RESERVED_BYTE
+};
+
+VOID*
+ReferenceAcpiTable (
+  VOID
+  )
+{
+  //
+  // Reference the table being generated to prevent the optimizer from
+  // removing the data structure from the executable
+  //
+  return (VOID*)&FACS;
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl

@@ -0,0 +1,352 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+
+// Define a Global region of ACPI NVS Region that may be used for any
+// type of implementation.  The starting offset and size will be fixed
+// up by the System BIOS during POST.  Note that the Size must be a word
+// in size to be fixed up correctly.
+
+OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
+Field(GNVS,AnyAcc,Lock,Preserve)
+{
+  Offset(0),       // Miscellaneous Dynamic Registers:
+  OSYS,   16,      //   (00) Operating System
+      ,   8,       //   (02)
+      ,   8,       //   (03)
+      ,   8,       //   (04)
+      ,   8,       //   (05)
+      ,   8,       //   (06)
+      ,   8,       //   (07)
+      ,   8,       //   (08)
+      ,   8,       //   (09)
+      ,   8,       //   (10)
+  P80D,   32,      //   (11) Port 80 Debug Port Value
+  LIDS,   8,       //   (15) Lid State (Lid Open = 1)
+      ,   8,       //   (16)
+      ,   8,       //   (17)
+  Offset(18),      // Thermal Policy Registers:
+      ,   8,       //   (18)
+      ,   8,       //   (19)
+  ACTT,   8,       //   (20) Active Trip Point
+  PSVT,   8,       //   (21) Passive Trip Point
+  TC1V,   8,       //   (22) Passive Trip Point TC1 Value
+  TC2V,   8,       //   (23) Passive Trip Point TC2 Value
+  TSPV,   8,       //   (24) Passive Trip Point TSP Value
+  CRTT,   8,       //   (25) Critical Trip Point
+  DTSE,   8,       //   (26) Digital Thermal Sensor Enable
+  DTS1,   8,       //   (27) Digital Thermal Sensor 1 Reading
+  DTS2,   8,       //   (28) Digital Thermal Sensor 2 Reading
+  DTSF,   8,       //   (29) DTS SMI Function Call
+  Offset(30),      // Battery Support Registers:
+      ,   8,       //   (30)
+      ,   8,       //   (31)
+      ,   8,       //   (32)
+      ,   8,       //   (33)
+      ,   8,       //   (34)
+      ,   8,       //   (35)
+      ,   8,       //   (36)
+  Offset(40),      // CPU Identification Registers:
+  APIC,   8,       //   (40) APIC Enabled by SBIOS (APIC Enabled = 1)
+  MPEN,   8,       //   (41) Number of Logical Processors if MP Enabled != 0
+      ,   8,       //   (42)
+      ,   8,       //   (43)
+      ,   8,       //   (44)
+      ,   32,      //   (45)
+  Offset(50),      // SIO CMOS Configuration Registers:
+      ,   8,       //   (50)
+      ,   8,       //   (51)
+      ,   8,       //   (52)
+      ,   8,       //   (53)
+      ,   8,       //   (54)
+      ,   8,       //   (55)
+      ,   8,       //   (56)
+      ,   8,       //   (57)
+      ,   8,       //   (58)
+  Offset(60),      // Internal Graphics Registers:
+      ,   8,       //   (60)
+      ,   8,       //   (61)
+  CADL,   8,       //   (62) Current Attached Device List
+      ,   8,       //   (63)
+  CSTE,   16,      //   (64) Current Display State
+  NSTE,   16,      //   (66) Next Display State
+      ,   16,      //   (68)
+  NDID,   8,       //   (70) Number of Valid Device IDs
+  DID1,   32,      //   (71) Device ID 1
+  DID2,   32,      //   (75) Device ID 2
+  DID3,   32,      //   (79) Device ID 3
+  DID4,   32,      //   (83) Device ID 4
+  DID5,   32,      //   (87) Device ID 5
+      ,   32,      //   (91)
+      ,   8,       //   (95) Fifth byte of AKSV (mannufacturing mode)
+  Offset(103),     // Backlight Control Registers:
+      ,   8,       //   (103)
+  BRTL,   8,       //   (104) Brightness Level Percentage
+  Offset(105),     // Ambiant Light Sensor Registers:
+      ,   8,       //   (105)
+      ,   8,       //   (106)
+  LLOW,   8,       //   (107) LUX Low Value
+      ,   8,       //   (108)
+  Offset(110),     // EMA Registers:
+      ,   8,       //   (110)
+      ,   16,      //   (111)
+      ,   16,      //   (113)
+  Offset(116),     // MEF Registers:
+      ,   8,       //   (116) MEF Enable
+  Offset(117),     // PCIe Dock:
+      ,   8,       //   (117)
+  Offset(120),     // TPM Registers:
+      ,   8,       //   (120)
+      ,   8,       //   (121)
+      ,   8,       //   (122)
+      ,   8,       //   (123)
+      ,   32,      //   (124)
+      ,   8,       //   (125)
+      ,   8,       //   (129)
+  Offset(130),     //
+      ,   56,      //   (130)
+      ,   56,      //   (137)
+      ,   8,       //   (144)
+      ,   56,      //   (145)
+  Offset(170),     // IGD OpRegion/Software SCI base address
+  ASLB,   32,      //   (170) IGD OpRegion base address
+  Offset(174),     // IGD OpRegion/Software SCI shared data
+  IBTT,   8,       //   (174) IGD Boot Display Device
+  IPAT,   8,       //   (175) IGD Panel Type CMOs option
+  ITVF,   8,       //   (176) IGD TV Format CMOS option
+  ITVM,   8,       //   (177) IGD TV Minor Format CMOS option
+  IPSC,   8,       //   (178) IGD Panel Scaling
+  IBLC,   8,       //   (179) IGD BLC Configuration
+  IBIA,   8,       //   (180) IGD BIA Configuration
+  ISSC,   8,       //   (181) IGD SSC Configuration
+  I409,   8,       //   (182) IGD 0409 Modified Settings Flag
+  I509,   8,       //   (183) IGD 0509 Modified Settings Flag
+  I609,   8,       //   (184) IGD 0609 Modified Settings Flag
+  I709,   8,       //   (185) IGD 0709 Modified Settings Flag
+  IDMM,   8,       //   (186) IGD DVMT Mode
+  IDMS,   8,       //   (187) IGD DVMT Memory Size
+  IF1E,   8,       //   (188) IGD Function 1 Enable
+  HVCO,   8,       //   (189) HPLL VCO
+  NXD1,   32,      //   (190) Next state DID1 for _DGS
+  NXD2,   32,      //   (194) Next state DID2 for _DGS
+  NXD3,   32,      //   (198) Next state DID3 for _DGS
+  NXD4,   32,      //   (202) Next state DID4 for _DGS
+  NXD5,   32,      //   (206) Next state DID5 for _DGS
+  NXD6,   32,      //   (210) Next state DID6 for _DGS
+  NXD7,   32,      //   (214) Next state DID7 for _DGS
+  NXD8,   32,      //   (218) Next state DID8 for _DGS
+  GSMI,   8,       //   (222) GMCH SMI/SCI mode (0=SCI)
+  PAVP,   8,       //   (223) IGD PAVP data
+  Offset(225),
+  OSCC,   8,       //   (225) PCIE OSC Control
+  NEXP,   8,       //   (226) Native PCIE Setup Value
+  Offset(235), // Global Variables
+  DSEN,   8,       //   (235) _DOS Display Support Flag.
+  ECON,   8,       //   (236) Embedded Controller Availability Flag.
+  GPIC,   8,       //   (237) Global IOAPIC/8259 Interrupt Mode Flag.
+  CTYP,   8,       //   (238) Global Cooling Type Flag.
+  L01C,   8,       //   (239) Global L01 Counter.
+  VFN0,   8,       //   (240) Virtual Fan0 Status.
+  VFN1,   8,       //   (241) Virtual Fan1 Status.
+  Offset(256),
+  NVGA,   32,  //   (256) NVIG opregion address
+  NVHA,   32,  //   (260) NVHM opregion address
+  AMDA,   32,  //   (264) AMDA opregion address
+  DID6,   32,  //   (268) Device ID 6
+  DID7,   32,  //   (272) Device ID 7
+  DID8,   32,  //   (276) Device ID 8
+  Offset(332),
+  USEL,   8,    // (332) UART Selection
+  PU1E,   8,    // (333) PCU UART 1 Enabled
+  PU2E,   8,    // (334) PCU UART 2 Enabled
+
+  LPE0, 32,     // (335) LPE Bar0
+  LPE1, 32,     // (339) LPE Bar1
+  LPE2, 32,     // (343) LPE Bar2
+
+  Offset(347),
+      ,   8,    // (347)
+      ,   8,    // (348)
+  PFLV,   8,    // (349) Platform Flavor
+
+  Offset(351),
+  ICNF,   8,   //   (351) ISCT / AOAC Configuration
+  XHCI,   8,   //   (352) xHCI controller mode
+  PMEN,   8,   //   (353) PMIC enable/disable
+
+  LPEE,   8,   //   (354) LPE enable/disable
+  ISPA,   32,  //   (355) ISP Base Addr
+  ISPD,   8,    //  (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3
+
+  offset(360),  // ((4+8+6)*4+2)*4=296
+  //
+  // Lpss controllers
+  //
+  PCIB,     32,
+  PCIT,     32,
+  D10A,     32,  //DMA1
+  D10L,     32,
+  D11A,     32,
+  D11L,     32,
+  P10A,     32,  //  PWM1
+  P10L,     32,
+  P11A,     32,
+  P11L,     32,
+  P20A,     32,  //  PWM2
+  P20L,     32,
+  P21A,     32,
+  P21L,     32,
+  U10A,     32,  // UART1
+  U10L,     32,
+  U11A,     32,
+  U11L,     32,
+  U20A,     32,  // UART2
+  U20L,     32,
+  U21A,     32,
+  U21L,     32,
+  SP0A,     32,  // SPI
+  SP0L,     32,
+  SP1A,     32,
+  SP1L,     32,
+
+  D20A,     32,  //DMA2
+  D20L,     32,
+  D21A,     32,
+  D21L,     32,
+  I10A,     32,  //  I2C1
+  I10L,     32,
+  I11A,     32,
+  I11L,     32,
+  I20A,     32,  //  I2C2
+  I20L,     32,
+  I21A,     32,
+  I21L,     32,
+  I30A,     32,  //  I2C3
+  I30L,     32,
+  I31A,     32,
+  I31L,     32,
+  I40A,     32,  //  I2C4
+  I40L,     32,
+  I41A,     32,
+  I41L,     32,
+  I50A,     32,  //  I2C5
+  I50L,     32,
+  I51A,     32,
+  I51L,     32,
+  I60A,     32,  //  I2C6
+  I60L,     32,
+  I61A,     32,
+  I61L,     32,
+  I70A,     32,  //  I2C7
+  I70L,     32,
+  I71A,     32,
+  I71L,     32,
+  //
+  // Scc controllers
+  //
+  eM0A,     32,  //  EMMC
+  eM0L,     32,
+  eM1A,     32,
+  eM1L,     32,
+  SI0A,     32,  //  SDIO
+  SI0L,     32,
+  SI1A,     32,
+  SI1L,     32,
+  SD0A,     32,  //  SDCard
+  SD0L,     32,
+  SD1A,     32,
+  SD1L,     32,
+  MH0A,     32,  //
+  MH0L,     32,
+  MH1A,     32,
+  MH1L,     32,
+
+  offset(656),
+  SDRM,     8,
+  offset(657),
+  HLPS,     8,   //(657) Hide Devices
+  offset(658),
+  OSEL,     8,      //(658) OS Seletion - Windows/Android
+
+  offset(659),  // VLV1 DPTF
+  SDP1,     8,      //(659) An enumerated value corresponding to SKU
+  DPTE,     8,      //(660) DPTF Enable
+  THM0,     8,      //(661) System Thermal 0
+  THM1,     8,      //(662) System Thermal 1
+  THM2,     8,      //(663) System Thermal 2
+  THM3,     8,      //(664) System Thermal 3
+  THM4,     8,      //(665) System Thermal 3
+  CHGR,     8,      //(666) DPTF Changer Device
+  DDSP,     8,      //(667) DPTF Display Device
+  DSOC,     8,      //(668) DPTF SoC device
+  DPSR,     8,      //(669) DPTF Processor device
+  DPCT,     32,     //(670) DPTF Processor participant critical temperature
+  DPPT,     32,     //(674) DPTF Processor participant passive temperature
+  DGC0,     32,     //(678) DPTF Generic sensor0 participant critical temperature
+  DGP0,     32,     //(682) DPTF Generic sensor0 participant passive temperature
+  DGC1,     32,     //(686) DPTF Generic sensor1 participant critical temperature
+  DGP1,     32,     //(690) DPTF Generic sensor1 participant passive temperature
+  DGC2,     32,     //(694) DPTF Generic sensor2 participant critical temperature
+  DGP2,     32,     //(698) DPTF Generic sensor2 participant passive temperature
+  DGC3,     32,     //(702) DPTF Generic sensor3 participant critical temperature
+  DGP3,     32,     //(706) DPTF Generic sensor3 participant passive temperature
+  DGC4,     32,     //(710)DPTF Generic sensor3 participant critical temperature
+  DGP4,     32,     //(714)DPTF Generic sensor3 participant passive temperature
+  DLPM,     8,      //(718) DPTF Current low power mode setting
+  DSC0,     32,     //(719) DPTF Critical threshold0 for SCU
+  DSC1,     32,     //(723) DPTF Critical threshold1 for SCU
+  DSC2,     32,     //(727) DPTF Critical threshold2 for SCU
+  DSC3,     32,     //(731) DPTF Critical threshold3 for SCU
+  DSC4,     32,     //(735) DPTF Critical threshold3 for SCU
+  DDBG,     8,      //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled
+  LPOE,     32,     //(740) DPTF LPO Enable
+  LPPS,     32,     //(744) P-State start index
+  LPST,     32,     //(748) Step size
+  LPPC,     32,     //(752) Power control setting
+  LPPF,     32,     //(756) Performance control setting
+  DPME,     8,      //(760) DPTF DPPM enable/disable
+  BCSL,     8,      //(761) Battery charging solution 0-CLV 1-ULPMC
+  NFCS,     8,      //(762) NFCx Select 1: NFC1    2:NFC2
+  PCIM,     8,      //(763) EMMC device 0-ACPI mode, 1-PCI mode
+  TPMA,     32,     //(764)
+  TPML,     32,     //(768)
+  ITSA,      8,     //(772) I2C Touch Screen Address
+  S0IX,     8,      //(773) S0ix status
+  SDMD,     8,      //(774) SDIO Mode
+  EMVR,     8,      //(775) eMMC controller version
+  BMBD,     32,     //(776) BM Bound
+  FSAS,     8,      //(780) FSA Status
+  BDID,     8,      //(781) Board ID
+  FBID,     8,      //(782) FAB ID
+  OTGM,     8,      //(783) OTG mode
+  STEP,     8,      //(784) Stepping ID
+  WITT,     8,      //(785) Enable Test Device connected to I2C for WHCK test.
+  SOCS,     8,      //(786) provide the SoC stepping infomation
+  AMTE,     8,      //(787) Ambient Trip point change
+  UTS,      8,      //(788) Enable Test Device connected to URT for WHCK test.
+  SCPE,     8,      //(789) Allow higher performance on AC/USB - Enable/Disable
+  Offset(792),
+  EDPV,     8,      //(792) Check for eDP display device
+  DIDX,     32,     //(793) Device ID for eDP device
+  IOT,      8,      //(794) MinnowBoard Max JP1 is configured for MSFT IOT project.   
+}
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl

@@ -0,0 +1,105 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+// General Purpose Events.  This Scope handles the Run-time and
+// Wake-time SCIs.  The specific method called will be determined by
+// the _Lxx value, where xx equals the bit location in the General
+// Purpose Event register(s).
+
+Scope(\_GPE)
+{
+  //
+  // Software GPE caused the event.
+  //
+  Method(_L02)
+  {
+    // Clear GPE status bit.
+    Store(0,GPEC)
+    //
+    // Handle DTS Thermal Events.
+    //
+    External(DTSE, IntObj)
+    If(CondRefOf(DTSE))
+    {
+      If(LGreaterEqual(DTSE, 0x01))
+      {
+        Notify(\_TZ.TZ01,0x80)
+      }
+    }
+  }
+
+  //
+  // PUNIT SCI event.
+  //
+  Method(_L04)
+  {
+    // Clear the PUNIT Status Bit.
+    Store(1, PSCI)
+  }
+
+
+  //
+  // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).
+  //
+  Method(_L05)
+  {
+    If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI)))   // Graphics software SCI event?
+    {
+      \_SB.PCI0.GFX0.GSCI()     // Handle the SWSCI
+    }
+  }
+
+  //
+  // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities
+  // on bus 0 asserts the equivalent of the PME# signal.
+  //
+  Method(_L0D, 0)
+  {
+    If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES))
+    {
+      If(LNotEqual(OSEL, 1))
+      {
+        Store(1, \_SB.PCI0.EHC1.PMES) //Clear PME status
+        Store(0, \_SB.PCI0.EHC1.PMEE) //Disable PME
+      }
+      Notify(\_SB.PCI0.EHC1, 0x02)
+    }
+    If(LAnd(\_SB.PCI0.XHC1.PMEE, \_SB.PCI0.XHC1.PMES))
+    {
+      If(LNotEqual(OSEL, 1))
+      {
+        Store(1, \_SB.PCI0.XHC1.PMES) //Clear PME status
+        Store(0, \_SB.PCI0.XHC1.PMEE) //Disable PME
+      }
+      Notify(\_SB.PCI0.XHC1, 0x02)
+    }
+    If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES))
+    {
+      If(LNotEqual(OSEL, 1))
+      {
+        Store(1, \_SB.PCI0.HDEF.PMES) //Clear PME status
+        Store(0, \_SB.PCI0.HDEF.PMEE) //Disable PME
+      }
+      Notify(\_SB.PCI0.HDEF, 0x02)
+    }
+  }
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL

@@ -0,0 +1,353 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  HOST_BUS.ASL
+
+Abstract:
+
+  Baytrail PCI configuration space definition.
+
+---*/
+Device(VLVC)
+{
+  Name(_ADR, 0x00000000)           // Device 0, Function 0
+
+  // Define various MCH Controller PCI Configuration Space
+  // registers which will be used to dynamically produce all
+  // resources in the Host Bus _CRS.
+  OperationRegion(HBUS, PCI_Config, 0x00, 0xFF)
+  Field(HBUS, DWordAcc, NoLock, Preserve)
+  {
+    Offset(0xD0),
+    SMCR,   32,             // VLV Message Control Register (0xD0)
+    Offset(0xD4),
+    SMDR,   32,             // VLV Message Data Register (0xD4)
+    Offset(0xD8),
+    MCRX,   32,             // VLV Message Control Register Extension (0xD8)
+  }
+
+  // Define a method to read a 32-bit register on the VLV Message bus.
+  //  Arg0 = Port
+  //  Arg1 = Register
+  //
+  //  Returns 32-bit register value
+
+  Method(RMBR, 2, Serialized)
+  {
+
+    // Initiate regsiter read message on VLV Message Bus MCR
+
+    Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
+    Or(0x100000F0, Local0, SMCR)
+
+    // Read register value from Message Data Register
+
+    Return(SMDR)
+  }
+
+
+  // Define a method to write a 32-bit register on the VLV Message bus MDR.
+  //  Arg0 = Port
+  //  Arg1 = Register
+  //  Arg2 = 32-bit value
+
+  Method(WMBR, 3, Serialized)
+  {
+
+    // Write register value to Message Data Register
+
+    Store(Arg2, SMDR)
+
+    // Initiate register write message on VLV Message Bus
+
+    Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
+    Or(0x110000F0, Local0, SMCR)
+  }
+}
+
+//
+// BUS, I/O, and MMIO resources
+//
+Method(_CRS,0,Serialized)
+{
+  //Update ISP0 reserved memory
+  CreateDwordField(RES0, ^ISP0._MIN,ISMN)
+  CreateDwordField(RES0, ^ISP0._MAX,ISMX)
+  CreateDwordField(RES0, ^ISP0._LEN,ISLN)
+  If (LEqual(ISPD,1))
+  {
+    Store (ISPA, ISMN)
+    Add (ISMN, ISLN, ISMX)
+    Subtract(ISMX, 1, ISMX)
+  } Else
+  {
+    Store (0, ISMN)
+    Store (0, ISMX)
+    Store (0, ISLN)
+  }
+
+  //PCI MMIO SPACE
+  CreateDwordField(RES0, ^PM01._MIN,M1MN)
+  CreateDwordField(RES0, ^PM01._MAX,M1MX)
+  CreateDwordField(RES0, ^PM01._LEN,M1LN)
+
+  //Get dBMBOUND Base
+  And(BMBD, 0xFF000000, M1MN)
+
+  //Get ECBASE
+  Store(PCIT, M1MX)
+  Add(Subtract(M1MX, M1MN), 1, M1LN)
+  Subtract(M1MX, 1, M1MX)
+
+  // Create pointers to Gfx Stolen Memory Sizing values.
+  CreateDwordField(RES0, ^STOM._MIN,GSMN)
+  CreateDwordField(RES0, ^STOM._MAX,GSMX)
+  CreateDwordField(RES0, ^STOM._LEN,GSLN)
+
+  If (LNotEqual (\_SB.PCI0.GFX0.GSTM, 0xFFFFFFFF))
+  {
+    Store(0x00, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C
+  } else
+  {
+    Store(\_SB.PCI0.GFX0.GSTM, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C
+  }
+  If (LNotEqual (\_SB.PCI0.GFX0.GUMA, 0xFFFFFFFF))
+  {
+    Store(0x00, GSLN) //Read the Stolen memory base from B0:D2:F0:R5C
+  } else
+  {
+    ShiftLeft(\_SB.PCI0.GFX0.GUMA, 25, GSLN) //Read Stolen memory base form B0:D2:F0:R50
+  }
+  Add(GSMN, GSLN, GSMX) //Store the Stolen Memory Size
+  Subtract(GSMX, 1, GSMX)
+
+  Return(RES0)
+}
+
+Name( RES0,ResourceTemplate()
+{
+  WORDBusNumber (          // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+    ResourceProducer,      // bit 0 of general flags is 1
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    PosDecode,             // PosDecode
+    0x0000,                // Granularity
+    0x0000,                // Min
+    0x00FF,                // Max
+    0x0000,                // Translation
+    0x0100                 // Range Length = Max-Min+1
+  )
+
+  IO (Decode16, 0x70, 0x77, 0x01, 0x08)         //Consumed resource (0xCF8-0xCFF)
+  IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08)       //Consumed resource (0xCF8-0xCFF)
+
+  WORDIO (                 // Consumed-and-produced resource (all I/O below CF8)
+    ResourceProducer,      // bit 0 of general flags is 0
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    PosDecode,
+    EntireRange,
+    0x0000,                // Granularity
+    0x0000,                // Min
+    0x006F,                // Max
+    0x0000,                // Translation
+    0x0070                 // Range Length
+  )
+
+  WORDIO (                 // Consumed-and-produced resource
+    ResourceProducer,      // bit 0 of general flags is 0
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    PosDecode,
+    EntireRange,
+    0x0000,                // Granularity
+    0x0078,                // Min
+    0x0CF7,                // Max
+    0x0000,                // Translation
+    0x0C80                 // Range Length
+  )
+
+  WORDIO (                 // Consumed-and-produced resource (all I/O above CFF)
+    ResourceProducer,      // bit 0 of general flags is 0
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    PosDecode,
+    EntireRange,
+    0x0000,                // Granularity
+    0x0D00,                // Min
+    0xFFFF,                // Max
+    0x0000,                // Translation
+    0xF300                 // Range Length
+  )
+
+  DWORDMEMORY (            // Descriptor for legacy VGA video RAM
+    ResourceProducer,      // bit 0 of general flags is 0
+    PosDecode,
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    Cacheable,
+    ReadWrite,
+    0x00000000,            // Granularity
+    0x000A0000,            // Min
+    0x000BFFFF,            // Max
+    0x00000000,            // Translation
+    0x00020000             // Range Length
+  )
+
+  DWORDMEMORY (            // Descriptor for legacy OptionRom
+    ResourceProducer,      // bit 0 of general flags is 0
+    PosDecode,
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    Cacheable,
+    ReadWrite,
+    0x00000000,            // Granularity
+    0x000C0000,            // Min
+    0x000DFFFF,            // Max
+    0x00000000,            // Translation
+    0x00020000             // Range Length
+  )
+
+  DWORDMEMORY (            // Descriptor for BIOS Area
+    ResourceProducer,      // bit 0 of general flags is 0
+    PosDecode,
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    Cacheable,
+    ReadWrite,
+    0x00000000,            // Granularity
+    0x000E0000,            // Min
+    0x000FFFFF,            // Max
+    0x00000000,            // Translation
+    0x00020000             // Range Length
+  )
+
+  DWORDMEMORY (            // Descriptor for ISP0 reserved Mem
+    ResourceProducer,      // bit 0 of general flags is 0
+    PosDecode,
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    Cacheable,
+    ReadWrite,
+    0x00000000,            // Granularity
+    0x7A000000,            // Min
+    0x7A3FFFFF,            // Max
+    0x00000000,            // Translation
+    0x00400000             // Range Length
+    ,,,
+    ISP0
+  )
+
+  DWORDMEMORY (            // Descriptor for VGA Stolen Mem
+    ResourceProducer,      // bit 0 of general flags is 0
+    PosDecode,
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    Cacheable,
+    ReadWrite,
+    0x00000000,            // Granularity
+    0x7C000000,            // Min
+    0x7FFFFFFF,            // Max
+    0x00000000,            // Translation
+    0x04000000             // Range Length
+    ,,,
+    STOM
+  )
+
+  DWORDMEMORY (            // Descriptor for PCI MMIO
+    ResourceProducer,      // bit 0 of general flags is 0
+    PosDecode,
+    MinFixed,              // Range is fixed
+    MaxFixed,              // Range is fixed
+    Cacheable,
+    ReadWrite,
+    0x00000000,            // Granularity
+    0x80000000,            // Min
+    0xDFFFFFFF,            // Max
+    0x00000000,            // Translation
+    0x60000000             // Range Length
+    ,,,
+    PM01
+  )
+})
+
+//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
+Name(GUID,Buffer()
+{
+  0x5b, 0x4d, 0xdb, 0x33,
+  0xf7, 0x1f,
+  0x1c, 0x40,
+  0x96, 0x57,
+  0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66
+})
+
+
+Name(SUPP,0)    // PCI _OSC Support Field value
+Name(CTRL,0)    // PCI _OSC Control Field value
+
+Method(_OSC,4,Serialized)
+{
+  // Check for proper UUID
+  // Save the capabilities buffer
+  Store(Arg3,Local0)
+
+  // Create DWord-adressable fields from the Capabilties Buffer
+  CreateDWordField(Local0,0,CDW1)
+  CreateDWordField(Local0,4,CDW2)
+  CreateDWordField(Local0,8,CDW3)
+
+  // Check for proper UUID
+  If(LAnd(LEqual(Arg0,GUID),NEXP))
+  {
+    // Save Capabilities DWord2 & 3
+    Store(CDW2,SUPP)
+    Store(CDW3,CTRL)
+
+    If(Not(And(CDW1,1)))    // Query flag clear?
+    {
+      // Disable GPEs for features granted native control.
+      If(And(CTRL,0x02))
+      {
+        NHPG()
+      }
+      If(And(CTRL,0x04))      // PME control granted?
+      {
+        NPME()
+      }
+    }
+
+    If(LNotEqual(Arg1,One))
+    {
+      // Unknown revision
+      Or(CDW1,0x08,CDW1)
+    }
+
+    If(LNotEqual(CDW3,CTRL))
+    {
+      // Capabilities bits were masked
+      Or(CDW1,0x10,CDW1)
+    }
+    // Update DWORD3 in the buffer
+	And(CTRL,0xfe,CTRL)                
+    Store(CTRL,CDW3)
+    Store(CTRL,OSCC)
+    Return(Local0)
+  } Else
+  {
+    Or(CDW1,4,CDW1)         // Unrecognized UUID
+    Return(Local0)
+  }
+}       // End _OSC

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc

@@ -0,0 +1,69 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  Hpet.c
+
+Abstract:
+
+  This file contains a structure definition for the ACPI HPET Table.
+--*/
+
+//
+// Statements that include other files
+//
+#ifdef ECP_FLAG
+#include <Tiano.h>
+#endif
+#include <Hpet.h>
+#include "AcpiTablePlatform.h"
+
+// Hpet Table
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER HPET = {
+  {
+    EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,
+    sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),
+    EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,
+    0,                          // to make sum of entire table == 0
+    EFI_ACPI_OEM_ID,            // OEMID is a 6 bytes long field
+    EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)
+    EFI_ACPI_OEM_REVISION,      // OEM revision
+    EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID
+    EFI_ACPI_CREATOR_REVISION   // ASL compiler revision number
+  },
+  0x0,                          // EventTimerBlockId
+  {
+    0x00,                     // Address_Space_ID = System Memory
+    0x40,                     // Register_Bit_Width = 32 bits, mentioned about write failures when in 64bit in SCU HAS
+    0x00,                     // Register_Bit_offset
+    0x00,                     // Dword access
+    HPET_BASE_ADDRESS,        // Base addresse of HPET
+  },
+  0x0,                          // Only HPET's _UID in Namespace
+  MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS,
+  0x0
+};
+
+VOID*
+ReferenceAcpiTable (
+  VOID
+  )
+{
+  //
+  // Reference the table being generated to prevent the optimizer from
+  // removing the data structure from the executable
+  //
+  return (VOID*)&HPET;
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL

@@ -0,0 +1,885 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  INTELGFX.ASL
+
+Abstract:
+
+  IGD OpRegion/Software ACPI Reference Code for the Baytrail Family.
+
+--*/
+
+// Enable/Disable Output Switching.  In WIN2K/WINXP, _DOS = 0 will
+// get called during initialization to prepare for an ACPI Display
+// Switch Event.  During an ACPI Display Switch, the OS will call
+// _DOS = 2 immediately after a Notify=0x80 to temporarily disable
+// all Display Switching.  After ACPI Display Switching is complete,
+// the OS will call _DOS = 0 to re-enable ACPI Display Switching.
+
+Method(_DOS,1)
+{
+  // Store Display Switching and LCD brightness BIOS control bit
+  Store(And(Arg0,7),DSEN)
+}
+
+// Enumerate the Display Environment.  This method will return
+// valid addresses for all display device encoders present in the
+// system.  The Miniport Driver will reject the addresses for every
+// encoder that does not have an attached display device.  After
+// enumeration is complete, the OS will call the _DGS methods
+// during a display switch only for the addresses accepted by the
+// Miniport Driver.  For hot-insertion and removal of display
+// devices, a re-enumeration notification will be required so the
+// address of the newly present display device will be accepted by
+// the Miniport Driver.
+
+Method(_DOD, 0, Serialized)
+{
+  Store(0, NDID)
+  If(LNotEqual(DIDL, Zero))
+  {
+    Store(SDDL(DIDL),DID1)
+  }
+  If(LNotEqual(DDL2, Zero))
+  {
+    Store(SDDL(DDL2),DID2)
+  }
+  If(LNotEqual(DDL3, Zero))
+  {
+    Store(SDDL(DDL3),DID3)
+  }
+  If(LNotEqual(DDL4, Zero))
+  {
+    Store(SDDL(DDL4),DID4)
+  }
+  If(LNotEqual(DDL5, Zero))
+  {
+    Store(SDDL(DDL5),DID5)
+  }
+
+  // TODO - This level of flexibility is not needed for a true
+  //      OEM design.  Simply determine the greatest number of
+  //      encoders the platform will suppport then remove all
+  //      return packages beyond that value.  Note that for
+  //      current silicon, the maximum number of encoders
+  //      possible is 5.
+
+  If(LEqual(NDID,1))
+  {
+    If (LNOTEqual (ISPD, 0))
+    {
+      Name(TMP0,Package() {0xFFFFFFFF,0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP0,0))
+      //Add ISP device to GFX0
+      Store(0x00020F38, Index(TMP0,1))
+      Return(TMP0)
+    } Else
+    {
+      Name(TMP1,Package() {0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP1,0))
+      Return(TMP1)
+    }
+  }
+
+  If(LEqual(NDID,2))
+  {
+    If (LNOTEqual (ISPD, 0))
+    {
+      Name(TMP2,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP2,0))
+      Store(Or(0x10000,DID2),Index(TMP2,1))
+      //Add ISP device to GFX0
+      Store(0x00020F38, Index(TMP2,2))
+      Return(TMP2)
+    } Else
+    {
+      Name(TMP3,Package() {0xFFFFFFFF, 0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP3,0))
+      Store(Or(0x10000,DID2),Index(TMP3,1))
+      Return(TMP3)
+    }
+  }
+
+  If(LEqual(NDID,3))
+  {
+    If (LNOTEqual (ISPD, 0))
+    {
+      Name(TMP4,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP4,0))
+      Store(Or(0x10000,DID2),Index(TMP4,1))
+      Store(Or(0x10000,DID3),Index(TMP4,2))
+      //Add ISP device to GFX0
+      Store(0x00020F38, Index(TMP4,3))
+      Return(TMP4)
+    } Else
+    {
+      Name(TMP5,Package() {0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP5,0))
+      Store(Or(0x10000,DID2),Index(TMP5,1))
+      Store(Or(0x10000,DID3),Index(TMP5,2))
+      Return(TMP5)
+    }
+  }
+
+  If(LEqual(NDID,4))
+  {
+    If (LNOTEqual (ISPD, 0))
+    {
+      Name(TMP6,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP6,0))
+      Store(Or(0x10000,DID2),Index(TMP6,1))
+      Store(Or(0x10000,DID3),Index(TMP6,2))
+      Store(Or(0x10000,DID4),Index(TMP6,3))
+      //Add ISP device to GFX0
+      Store(0x00020F38, Index(TMP6,4))
+      Return(TMP6)
+    } Else
+    {
+      Name(TMP7,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP7,0))
+      Store(Or(0x10000,DID2),Index(TMP7,1))
+      Store(Or(0x10000,DID3),Index(TMP7,2))
+      Store(Or(0x10000,DID4),Index(TMP7,3))
+      Return(TMP7)
+    }
+  }
+
+  If(LGreater(NDID,4))
+  {
+    If (LNOTEqual (ISPD, 0))
+    {
+      Name(TMP8,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP8,0))
+      Store(Or(0x10000,DID2),Index(TMP8,1))
+      Store(Or(0x10000,DID3),Index(TMP8,2))
+      Store(Or(0x10000,DID4),Index(TMP8,3))
+      Store(Or(0x10000,DID5),Index(TMP8,4))
+      //Add ISP device to GFX0
+      Store(0x00020F38, Index(TMP8,5))
+      Return(TMP8)
+    } Else
+    {
+      Name(TMP9,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})
+      Store(Or(0x10000,DID1),Index(TMP9,0))
+      Store(Or(0x10000,DID2),Index(TMP9,1))
+      Store(Or(0x10000,DID3),Index(TMP9,2))
+      Store(Or(0x10000,DID4),Index(TMP9,3))
+      Store(Or(0x10000,DID5),Index(TMP9,4))
+      Return(TMP9)
+    }
+  }
+
+  // If nothing else, return Unknown LFP.
+  // (Prevents compiler warning.)
+
+  //Add ISP device to GFX0
+  If (LNOTEqual (ISPD, 0))
+  {
+    Return(Package() {0x00000400, 0x00020F38})
+  } Else
+  {
+    Return(Package() {0x00000400})
+  }
+}
+
+Device(DD01)
+{
+
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(And(0x0F00,DID1),0x400))
+    {
+      Store(0x1, EDPV)
+      Store(DID1, DIDX)
+      Return(1)
+    }
+    If(LEqual(DID1,0))
+    {
+      Return(1)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DID1))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    Return(CDDS(DID1))
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    Return(NDDS(DID1))
+  }
+
+  // Device Set State.
+
+  // _DSS Table:
+  //
+  //      BIT31   BIT30   Execution
+  //      0       0       Don't implement.
+  //      0       1       Cache change.  Nothing to Implement.
+  //      1       0       Don't Implement.
+  //      1       1       Display Switch Complete.  Implement.
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+
+      Store(NSTE,CSTE)
+    }
+  }
+}
+
+Device(DD02)
+{
+
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(And(0x0F00,DID2),0x400))
+    {
+      Store(0x2, EDPV)
+      Store(DID2, DIDX)
+      Return(2)
+    }
+    If(LEqual(DID2,0))
+    {
+      Return(2)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DID2))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    Return(CDDS(DID2))
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    // Return the Next State.
+    Return(NDDS(DID2))
+  }
+
+  // Device Set State. (See table above.)
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+
+      Store(NSTE,CSTE)
+    }
+  }
+}
+
+Device(DD03)
+{
+
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(And(0x0F00,DID3),0x400))
+    {
+      Store(0x3, EDPV)
+      Store(DID3, DIDX)
+      Return(3)
+    }
+    If(LEqual(DID3,0))
+    {
+      Return(3)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DID3))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    If(LEqual(DID3,0))
+    {
+      Return(0x0B)
+    }
+    Else
+    {
+      Return(CDDS(DID3))
+    }
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    Return(NDDS(DID3))
+  }
+
+  // Device Set State. (See table above.)
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+
+      Store(NSTE,CSTE)
+    }
+  }
+}
+
+Device(DD04)
+{
+
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(And(0x0F00,DID4),0x400))
+    {
+      Store(0x4, EDPV)
+      Store(DID4, DIDX)
+      Return(4)
+    }
+    If(LEqual(DID4,0))
+    {
+      Return(4)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DID4))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    If(LEqual(DID4,0))
+    {
+      Return(0x0B)
+    }
+    Else
+    {
+      Return(CDDS(DID4))
+    }
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    Return(NDDS(DID4))
+  }
+
+  // Device Set State. (See table above.)
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+
+      Store(NSTE,CSTE)
+    }
+  }
+}
+
+
+Device(DD05)
+{
+
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(And(0x0F00,DID5),0x400))
+    {
+      Store(0x5, EDPV)
+      Store(DID5, DIDX)
+      Return(5)
+    }
+    If(LEqual(DID5,0))
+    {
+      Return(5)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DID5))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    If(LEqual(DID5,0))
+    {
+      Return(0x0B)
+    }
+    Else
+    {
+      Return(CDDS(DID5))
+    }
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    Return(NDDS(DID5))
+  }
+
+  // Device Set State. (See table above.)
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+
+      Store(NSTE,CSTE)
+    }
+  }
+}
+
+
+Device(DD06)
+{
+
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(And(0x0F00,DID6),0x400))
+    {
+      Store(0x6, EDPV)
+      Store(DID6, DIDX)
+      Return(6)
+    }
+    If(LEqual(DID6,0))
+    {
+      Return(6)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DID6))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    If(LEqual(DID6,0))
+    {
+      Return(0x0B)
+    }
+    Else
+    {
+      Return(CDDS(DID6))
+    }
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    Return(NDDS(DID6))
+  }
+
+  // Device Set State. (See table above.)
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+
+      Store(NSTE,CSTE)
+    }
+  }
+}
+
+
+Device(DD07)
+{
+
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(And(0x0F00,DID7),0x400))
+    {
+      Store(0x7, EDPV)
+      Store(DID7, DIDX)
+      Return(7)
+    }
+    If(LEqual(DID7,0))
+    {
+      Return(7)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DID7))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    If(LEqual(DID7,0))
+    {
+      Return(0x0B)
+    }
+    Else
+    {
+      Return(CDDS(DID7))
+    }
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    Return(NDDS(DID7))
+  }
+
+  // Device Set State. (See table above.)
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+
+      Store(NSTE,CSTE)
+    }
+  }
+}
+
+
+Device(DD08)
+{
+
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(And(0x0F00,DID8),0x400))
+    {
+      Store(0x8, EDPV)
+      Store(DID8, DIDX)
+      Return(8)
+    }
+    If(LEqual(DID8,0))
+    {
+      Return(8)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DID8))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    If(LEqual(DID8,0))
+    {
+      Return(0x0B)
+    }
+    Else
+    {
+      Return(CDDS(DID8))
+    }
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    Return(NDDS(DID8))
+  }
+
+  // Device Set State. (See table above.)
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+
+      Store(NSTE,CSTE)
+    }
+  }
+}
+
+//device for eDP
+Device(DD1F)
+{
+  // Return Unique ID.
+
+  Method(_ADR,0,Serialized)
+  {
+    If(LEqual(EDPV, 0x0))
+    {
+      Return(0x1F)
+    }
+    Else
+    {
+      Return(And(0xFFFF,DIDX))
+    }
+  }
+
+  // Return the Current Status.
+
+  Method(_DCS,0)
+  {
+    If(LEqual(EDPV, 0x0))
+    {
+      Return(0x00)
+    }
+    Else
+    {
+      Return(CDDS(DIDX))
+    }
+  }
+
+  // Query Graphics State (active or inactive).
+
+  Method(_DGS,0)
+  {
+    Return(NDDS(DIDX))
+  }
+
+  // Device Set State. (See table above.)
+
+  Method(_DSS,1)
+  {
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+    {
+      // State change was performed by the
+      // Video Drivers.  Simply update the
+      // New State.
+      Store(NSTE,CSTE)
+    }
+  }
+  // Query List of Brightness Control Levels Supported.
+
+  Method(_BCL,0)
+  {
+    // List of supported brightness levels in the following sequence.
+
+    // Level when machine has full power.
+    // Level when machine is on batteries.
+    // Other supported levels.
+    Return(Package() {80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100})
+  }
+
+  // Set the Brightness Level.
+
+  Method (_BCM,1)
+  {
+    // Set the requested level if it is between 0 and 100%.
+
+    If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))
+    {
+      \_SB.PCI0.GFX0.AINT(1, Arg0)
+      Store(Arg0,BRTL)  // Store Brightness Level.
+    }
+  }
+
+  // Brightness Query Current level.
+
+  Method (_BQC,0)
+  {
+    Return(BRTL)
+  }
+}
+
+Method(SDDL,1)
+{
+  Increment(NDID)
+  Store(And(Arg0,0xF0F),Local0)
+  Or(0x80000000,Local0, Local1)
+  If(LEqual(DIDL,Local0))
+  {
+    Return(Local1)
+  }
+  If(LEqual(DDL2,Local0))
+  {
+    Return(Local1)
+  }
+  If(LEqual(DDL3,Local0))
+  {
+    Return(Local1)
+  }
+  If(LEqual(DDL4,Local0))
+  {
+    Return(Local1)
+  }
+  If(LEqual(DDL5,Local0))
+  {
+    Return(Local1)
+  }
+  If(LEqual(DDL6,Local0))
+  {
+    Return(Local1)
+  }
+  If(LEqual(DDL7,Local0))
+  {
+    Return(Local1)
+  }
+  If(LEqual(DDL8,Local0))
+  {
+    Return(Local1)
+  }
+  Return(0)
+}
+
+Method(CDDS,1)
+{
+  Store(And(Arg0,0xF0F),Local0)
+
+  If(LEqual(0, Local0))
+  {
+    Return(0x1D)
+  }
+  If(LEqual(CADL, Local0))
+  {
+    Return(0x1F)
+  }
+  If(LEqual(CAL2, Local0))
+  {
+    Return(0x1F)
+  }
+  If(LEqual(CAL3, Local0))
+  {
+    Return(0x1F)
+  }
+  If(LEqual(CAL4, Local0))
+  {
+    Return(0x1F)
+  }
+  If(LEqual(CAL5, Local0))
+  {
+    Return(0x1F)
+  }
+  If(LEqual(CAL6, Local0))
+  {
+    Return(0x1F)
+  }
+  If(LEqual(CAL7, Local0))
+  {
+    Return(0x1F)
+  }
+  If(LEqual(CAL8, Local0))
+  {
+    Return(0x1F)
+  }
+  Return(0x1D)
+}
+
+Method(NDDS,1)
+{
+  Store(And(Arg0,0xF0F),Local0)
+
+  If(LEqual(0, Local0))
+  {
+    Return(0)
+  }
+  If(LEqual(NADL, Local0))
+  {
+    Return(1)
+  }
+  If(LEqual(NDL2, Local0))
+  {
+    Return(1)
+  }
+  If(LEqual(NDL3, Local0))
+  {
+    Return(1)
+  }
+  If(LEqual(NDL4, Local0))
+  {
+    Return(1)
+  }
+  If(LEqual(NDL5, Local0))
+  {
+    Return(1)
+  }
+  If(LEqual(NDL6, Local0))
+  {
+    Return(1)
+  }
+  If(LEqual(NDL7, Local0))
+  {
+    Return(1)
+  }
+  If(LEqual(NDL8, Local0))
+  {
+    Return(1)
+  }
+  Return(0)
+}
+
+//
+// Include IGD OpRegion/Software SCI interrupt handler which is use by
+// the graphics drivers to request data from system BIOS.
+//
+include("IgdOpRn.ASL")

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL

@@ -0,0 +1,77 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  INTELISPDev2.ASL
+
+Abstract:
+
+  ISP Exist as B0D2F0 Software ACPI Reference Code for the Baytrail Family.
+
+--*/
+////Device ISP0
+Device(ISP0)
+{
+  Name(_ADR, 0x0F38)
+  //Name (_HID, "80860F38")
+  //Name (_CID, "80860F38")
+  Name(_DDN, "VLV2 ISP - 80860F38")
+  Name(_UID, 0x01)
+
+  Method (_STA, 0, NotSerialized)
+  {
+    If(LEqual(ISPD,1))   //Dev2 need report ISP0 as GFX0 child
+    {
+      Return (0xF)
+    }
+    Else
+    {
+      Return (0x0)
+    }
+  }
+  Name(SBUF,ResourceTemplate ()
+  {
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00400000, ISP0)
+  })
+  Method(_CRS, 0x0, NotSerialized)
+  {
+    Return (SBUF)
+  }
+  Method (_SRS, 0x1, NotSerialized)
+  {
+  }
+  Method (_DIS, 0x0, NotSerialized)
+  {
+  }
+  Method(_DSM, 0x4, NotSerialized)
+  {
+    If (LEqual (Arg0, 0x01))
+    {
+      ///Switch ISP to D3H
+      Return (0x01)
+    }
+    Elseif (LEqual (Arg0, 0x02))
+    {
+      //Switch ISP to D0
+      Return (0x02)
+    }
+    Else
+    {
+      //Do nothing
+      Return (0x0F)
+    }
+  }
+} ///End ISP0
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL

@@ -0,0 +1,161 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  IgdOGBDA.ASL
+
+Abstract:
+
+  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.
+  This file contains Get BIOS Data Area funciton support for
+  the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism.
+
+--*/
+
+
+Method (GBDA, 0, Serialized)
+{
+
+  // Supported calls: Sub-function 0
+
+  If (LEqual(GESF, 0))
+  {
+    //<TODO> Update implementation specific supported calls.  Reference
+    // code is set to Intel's validated implementation.
+
+    Store(0x0000279, PARM)
+
+    Store(Zero, GESF)               // Clear the exit parameter
+    Return(SUCC)                    // Success
+  }
+
+  // Requested callbacks: Sub-function 1
+
+  If (LEqual(GESF, 1))
+  {
+
+    //<TODO> Update implementation specific system BIOS requested call
+    // back functions.  Call back functions are where the driver calls the
+    // system BIOS at function indicated event.
+
+    Store(0x00000240, PARM)
+
+    Store(Zero, GESF)               // Clear the exit parameter
+    Return(SUCC)                    // Success
+  }
+
+  // Get Boot display Preferences: Sub-function 4
+
+  If (LEqual(GESF, 4))
+  {
+
+    //<TODO> Update the implementation specific Get Boot Display
+    // Preferences function.
+
+    And(PARM, 0xEFFF0000, PARM)     // PARM[30:16] = Boot device ports
+    And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM)
+    Or(IBTT, PARM, PARM)            // PARM[7:0] = Boot device type
+
+    Store(Zero, GESF)               // Clear the exit parameter
+    Return(SUCC)                    // Success
+  }
+
+  // Panel details: Sub-function 5
+
+  If (LEqual(GESF, 5))
+  {
+
+    //<TODO> Update the implementation specific Get Panel Details
+    // function.
+
+    Store(IPSC, PARM)               // Report the scaling setting
+    Or(PARM, ShiftLeft(IPAT, 8), PARM)
+    Add(PARM, 0x100, PARM)          // Adjust panel type, 0 = VBT default
+    Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state
+    Add(PARM, 0x10000, PARM)        // Adjust the lid state, 0 = Unknown
+    Or(PARM, ShiftLeft(IBLC, 18), PARM) // Report the BLC setting
+    Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting
+    Store(Zero, GESF)
+    Return(SUCC)
+  }
+
+  // TV-standard/Video-connector: Sub-function 6
+
+  If (LEqual(GESF, 6))
+  {
+
+    //<TODO> Update the implementation specific Get
+    // TV-standard/Video-connectorPanel function.
+
+    Store(ITVF, PARM)
+    Or(PARM, ShiftLeft(ITVM, 4), PARM)
+    Store(Zero, GESF)
+    Return(SUCC)
+  }
+
+  // Internal graphics: Sub-function 7
+
+  If (LEqual(GESF, 7))
+  {
+    Store(GIVD, PARM)               // PARM[0]      - VGA mode(1=VGA)
+    Xor(PARM, 1, PARM)              // Invert the VGA mode polarity
+    Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1]   - # IGD PCI functions-1
+    // PARM[3:2]    - Reserved
+    // PARM[4]      - IGD D3 support(0=cold)
+    // PARM[10:5]   - Reserved
+    Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0)
+
+    //
+    // Report DVMT 5.0 Total Graphics memory size.
+    //
+    Or(PARM, ShiftLeft(IDMS, 17), PARM)   // Bits 20:17 are for Gfx total memory size
+
+    // If the "Set Internal Graphics" call is supported, the modified
+    // settings flag must be programmed per the specification.  This means
+    // that the flag must be set to indicate that system BIOS requests
+    // these settings.  Once "Set Internal Graphics" is called, the
+    //  modified settings flag must be cleared on all subsequent calls to
+    // this function.
+
+    // Report the graphics frequency based on DISPLAY_CLOCK_FREQUENCY_ENCODING [MMADR+0x20C8]
+
+    Or(ShiftLeft(Derefof(Index(CDCT, \_SB.PCI0.GFX0.MCHK.DCFE)), 21),PARM, PARM)
+
+    Store(1, GESF)                  // Set the modified settings flag
+    Return(SUCC)
+  }
+
+  // Spread spectrum clocks: Sub-function 10
+
+  If (LEqual(GESF, 10))
+  {
+
+    Store(0, PARM)                  // Assume SSC is disabled
+
+    If(ISSC)
+    {
+      Or(PARM, 3, PARM)       // If SSC enabled, return SSC1+Enabled
+    }
+
+    Store(0, GESF)                  // Set the modified settings flag
+    Return(SUCC)                    // Success
+  }
+
+
+  // A call to a reserved "Get BIOS data" function was received.
+
+  Store(Zero, GESF)                     // Clear the exit parameter
+  Return(CRIT)                          // Reserved, "Critical failure"
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL

@@ -0,0 +1,491 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  IgdOMOBF.ASL
+
+Abstract:
+
+  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.
+  This file contains ASL code with the purpose of handling events
+  i.e. hotkeys and other system interrupts.
+
+--*/
+
+
+// Notes:
+// 1. The following routines are to be called from the appropriate event
+//    handlers.
+// 2. This code cannot comprehend the exact implementation in the OEM's BIOS.
+//    Therefore, an OEM must call these methods from the existing event
+//    handler infrastructure.  Details on when/why to call each method is
+//    included in the method header under the "usage" section.
+
+
+/************************************************************************;
+;* ACPI Notification Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name:        PDRD
+;*
+;* Description: Check if the graphics driver is ready to process
+;*              notifications and video extensions.
+;*
+;* Usage:       This method is to be called prior to performing any
+;*              notifications or handling video extensions.
+;*              Ex: If (PDRD()) {Return (FAIL)}
+;*
+;* Input:       None
+;*
+;* Output:      None
+;*
+;* References:  DRDY (Driver ready status), ASLP (Driver recommended
+;*              sleep timeout value).
+;*
+;************************************************************************/
+
+Method(PDRD)
+{
+  If(LNot(DRDY))
+  {
+
+    // Sleep for ASLP milliseconds if the driver is not ready.
+
+    Sleep(ASLP)
+  }
+
+  // If DRDY is clear, the driver is not ready.  If the return value is
+  // !=0, do not perform any notifications or video extension handling.
+
+  Return(LNot(DRDY))
+}
+
+
+/************************************************************************;
+;*
+;* Name:        PSTS
+;*
+;* Description: Check if the graphics driver has completed the previous
+;*              "notify" command.
+;*
+;* Usage:       This method is called before every "notify" command.  A
+;*              "notify" should only be set if the driver has completed the
+;*              previous command.  Else, ignore the event and exit the parent
+;*              method.
+;*              Ex: If (PSTS()) {Return (FAIL)}
+;*
+;* Input:       None
+;*
+;* Output:      None
+;*
+;* References:  CSTS (Notification status), ASLP (Driver recommended sleep
+;*              timeout value).
+;*
+;************************************************************************/
+
+Method(PSTS)
+{
+  If(LGreater(CSTS, 2))
+  {
+    // Sleep for ASLP milliseconds if the status is not "success,
+    // failure, or pending"
+    //
+    Sleep(ASLP)
+  }
+
+  Return(LEqual(CSTS, 3))         // Return True if still Dispatched
+}
+
+
+/************************************************************************;
+;*
+;* Name:        GNOT
+;*
+;* Description: Call the appropriate methods to query the graphics driver
+;*              status.  If all methods return success, do a notification of
+;*              the graphics device.
+;*
+;* Usage:       This method is to be called when a graphics device
+;*              notification is required (display switch hotkey, etc).
+;*
+;* Input:       Arg0 = Current event type:
+;*                      1 = display switch
+;*                      2 = lid
+;*                      3 = dock
+;*              Arg1 = Notification type:
+;*                      0 = Re-enumeration
+;*                      0x80 = Display switch
+;*
+;* Output:      Returns 0 = success, 1 = failure
+;*
+;* References:  PDRD and PSTS methods.  OSYS (OS version)
+;*
+;************************************************************************/
+
+Method(GNOT, 2)
+{
+  // Check for 1. Driver loaded, 2. Driver ready.
+  // If any of these cases is not met, skip this event and return failure.
+  //
+  If(PDRD())
+  {
+    Return(0x1)             // Return failure if driver not loaded.
+  }
+
+  Store(Arg0, CEVT)               // Set up the current event value
+  Store(3, CSTS)                  // CSTS=BIOS dispatched an event
+
+  If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0)))      // Do not re-enum if driver supports hotplug
+  {
+    If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006)))
+    {
+      //
+      // WINXP requires that the entire PCI Bridge be re-enumerated.
+      //
+      Notify(\_SB.PCI0, Arg1)
+    }
+    Else
+    {
+      //
+      // Re-enumerate the Graphics Device for non-XP operating systems.
+      //
+      Notify(\_SB.PCI0.GFX0, Arg1)
+    }
+  }
+
+  Notify(\_SB.PCI0.GFX0,0x80)
+
+
+  Return(0x0)                     // Return success
+}
+
+
+/************************************************************************;
+;*
+;* Name:        GHDS
+;*
+;* Description: Handle a hotkey display switching event (performs a
+;*              Notify(GFX0, 0).
+;*
+;* Usage:       This method must be called when a hotkey event occurs and the
+;*              purpose of that hotkey is to do a display switch.
+;*
+;* Input:       Arg0 = Toggle table number.
+;*
+;* Output:      Returns 0 = success, 1 = failure.
+;*              CEVT and TIDX are indirect outputs.
+;*
+;* References:  TIDX, GNOT
+;*
+;************************************************************************/
+
+Method(GHDS, 1)
+{
+  Store(Arg0, TIDX)               // Store the table number
+
+  // Call GNOT for CEVT = 1 = hotkey, notify value = 0
+
+  Return(GNOT(1, 0))              // Return stats from GNOT
+}
+
+
+/************************************************************************;
+;*
+;* Name:        GLID
+;*
+;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the
+;*              lid notify).
+;*
+;* Usage:       This method must be called when a lid event occurs.  A
+;*              Notify(LID0, 0x80) must follow the call to this method.
+;*
+;* Input:       Arg0 = Lid state:
+;*                      0 = All closed
+;*                      1 = internal LFP lid open
+;*                      2 = external lid open
+;*                      3 = both external and internal open
+;*
+;* Output:      Returns 0=success, 1=failure.
+;*              CLID and CEVT are indirect outputs.
+;*
+;* References:  CLID, GNOT
+;*
+;************************************************************************/
+
+Method(GLID, 1)
+{
+  Store(Arg0, CLID)               // Store the current lid state
+
+  // Call GNOT for CEVT=2=Lid, notify value = 0
+
+  Return(GNOT(2, 0))              // Return stats from GNOT
+}
+
+
+/************************************************************************;
+;*
+;* Name:        GDCK
+;*
+;* Description: Handle a docking event by updating the current docking status
+;*              and doing a notification.
+;*
+;* Usage:       This method must be called when a docking event occurs.
+;*
+;* Input:       Arg0 = Docking state:
+;*                      0 = Undocked
+;*                      1 = Docked
+;*
+;* Output:      Returns 0=success, 1=failure.
+;*              CDCK and CEVT are indirect outputs.
+;*
+;* References:  CDCK, GNOT
+;*
+;************************************************************************/
+
+Method(GDCK, 1)
+{
+  Store(Arg0, CDCK)               // Store the current dock state
+
+  // Call GNOT for CEVT=4=Dock, notify value = 0
+
+  Return(GNOT(4, 0))              // Return stats from GNOT
+}
+
+
+/************************************************************************;
+;* ASLE Interrupt Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name:        PARD
+;*
+;* Description: Check if the driver is ready to handle ASLE interrupts
+;*              generate by the system BIOS.
+;*
+;* Usage:       This method must be called before generating each ASLE
+;*              interrupt.
+;*
+;* Input:       None
+;*
+;* Output:      Returns 0 = success, 1 = failure.
+;*
+;* References:  ARDY (Driver readiness), ASLP (Driver recommended sleep
+;*              timeout value)
+;*
+;************************************************************************/
+
+Method(PARD)
+{
+  If(LNot(ARDY))
+  {
+
+    // Sleep for ASLP milliseconds if the driver is not ready.
+
+    Sleep(ASLP)
+  }
+
+  // If ARDY is clear, the driver is not ready.  If the return value is
+  // !=0, do not generate the ASLE interrupt.
+
+  Return(LNot(ARDY))
+}
+
+
+/************************************************************************;
+;*
+;* Name:        AINT
+;*
+;* Description: Call the appropriate methods to generate an ASLE interrupt.
+;*              This process includes ensuring the graphics driver is ready
+;*              to process the interrupt, ensuring the driver supports the
+;*              interrupt of interest, and passing information about the event
+;*              to the graphics driver.
+;*
+;* Usage:       This method must called to generate an ASLE interrupt.
+;*
+;* Input:       Arg0 = ASLE command function code:
+;*                      0 = Set ALS illuminance
+;*                      1 = Set backlight brightness
+;*                      2 = Do Panel Fitting
+;*              Arg1 = If Arg0 = 0, current ALS reading:
+;*                      0 = Reading below sensor range
+;*                      1-0xFFFE = Current sensor reading
+;*                      0xFFFF = Reading above sensor range
+;*              Arg1 = If Arg0 = 1, requested backlight percentage
+;*
+;* Output:      Returns 0 = success, 1 = failure
+;*
+;* References:  PARD method.
+;*
+;************************************************************************/
+
+Method(AINT, 2)
+{
+
+  // Return failure if the requested feature is not supported by the
+  // driver.
+
+  If(LNot(And(TCHE, ShiftLeft(1, Arg0))))
+  {
+    Return(0x1)
+  }
+
+  // Return failure if the driver is not ready to handle an ASLE
+  // interrupt.
+
+  If(PARD())
+  {
+    Return(0x1)
+  }
+
+  // Evaluate the first argument (Panel fitting, backlight brightness, or ALS).
+
+  If(LEqual(Arg0, 2))             // Arg0 = 2, so request a panel fitting mode change.
+  {
+    If(CPFM)                                        // If current mode field is non-zero use it.
+    {
+      And(CPFM, 0x0F, Local0)                 // Create variables without reserved
+      And(EPFM, 0x0F, Local1)                 // or valid bits.
+
+      If(LEqual(Local0, 1))                   // If current mode is centered,
+      {
+        If(And(Local1, 6))              // and if stretched is enabled,
+        {
+          Store(6, PFIT)          // request stretched.
+        }
+        Else                            // Otherwise,
+        {
+          If(And(Local1, 8))      // if aspect ratio is enabled,
+          {
+            Store(8, PFIT)  // request aspect ratio.
+          }
+          Else                    // Only centered mode is enabled
+          {
+            Store(1, PFIT)  // so request centered. (No change.)
+          }
+        }
+      }
+      If(LEqual(Local0, 6))                   // If current mode is stretched,
+      {
+        If(And(Local1, 8))              // and if aspect ratio is enabled,
+        {
+          Store(8, PFIT)          // request aspect ratio.
+        }
+        Else                            // Otherwise,
+        {
+          If(And(Local1, 1))      // if centered is enabled,
+          {
+            Store(1, PFIT)  // request centered.
+          }
+          Else                    // Only stretched mode is enabled
+          {
+            Store(6, PFIT)  // so request stretched. (No change.)
+          }
+        }
+      }
+      If(LEqual(Local0, 8))                   // If current mode is aspect ratio,
+      {
+        If(And(Local1, 1))              // and if centered is enabled,
+        {
+          Store(1, PFIT)          // request centered.
+        }
+        Else                            // Otherwise,
+        {
+          If(And(Local1, 6))      // if stretched is enabled,
+          {
+            Store(6, PFIT)  // request stretched.
+          }
+          Else                    // Only aspect ratio mode is enabled
+          {
+            Store(8, PFIT)  // so request aspect ratio. (No change.)
+          }
+        }
+      }
+    }
+
+    // The following code for panel fitting (within the Else condition) is retained for backward compatiblity.
+
+    Else                            // If CFPM field is zero use PFIT and toggle the
+    {
+      Xor(PFIT,7,PFIT)        // mode setting between stretched and centered only.
+    }
+
+    Or(PFIT,0x80000000,PFIT)        // Set the valid bit for all cases.
+
+    Store(4, ASLC)                  // Store "Panel fitting event" to ASLC[31:1]
+  }
+  Else
+  {
+    If(LEqual(Arg0, 1))             // Arg0=1, so set the backlight brightness.
+    {
+      Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255.
+
+      Or(BCLP, 0x80000000, BCLP)      // Set the valid bit.
+
+      Store(2, ASLC)                  // Store "Backlight control event" to ASLC[31:1]
+    }
+    Else
+    {
+      If(LEqual(Arg0, 0))             // Arg0=0, so set the ALS illuminace
+      {
+        Store(Arg1, ALSI)
+
+        Store(1, ASLC)          // Store "ALS event" to ASLC[31:1]
+      }
+      Else
+      {
+        Return(0x1) // Unsupported function
+      }
+    }
+  }
+
+  Store(0x01, ASLE)               // Generate ASLE interrupt
+  Return(0x0)                     // Return success
+}
+
+
+/************************************************************************;
+;*
+;* Name:        SCIP
+;*
+;* Description: Checks the presence of the OpRegion and SCI
+;*
+;* Usage:       This method is called before other OpRegion methods. The
+;*              former "GSMI True/False is not always valid.  This method
+;*              checks if the OpRegion Version is non-zero and if non-zero,
+;*              (present and readable) then checks the GSMI flag.
+;*
+;* Input:       None
+;*
+;* Output:      Boolean True = SCI present.
+;*
+;* References:  None
+;*
+;************************************************************************/
+
+Method(SCIP)
+{
+  If(LNotEqual(OVER,0))           // If OpRegion Version not 0.
+  {
+    Return(LNot(GSMI))      // Return True if SCI.
+  }
+
+  Return(0)                       // Else Return False.
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL

@@ -0,0 +1,280 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  IgdOSBCB.ASL
+
+Abstract:
+
+  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.
+  This file contains the system BIOS call back functionality for the
+  OpRegion/Software SCI mechanism.
+
+--*/
+
+
+Method (SBCB, 0, Serialized)
+{
+
+  // Supported Callbacks: Sub-function 0
+
+  If (LEqual(GESF, 0x0))
+  {
+
+    //<TODO> An OEM may support the driver->SBIOS status callbacks, but
+    // the supported callbacks value must be modified.  The code that is
+    // executed upon reception of the callbacks must be also be updated
+    // to perform the desired functionality.
+
+    Store(0x00000000, PARM)         // No callbacks supported
+
+    If(LEqual(PFLV,FMBL))
+    {
+      Store(0x000F87FD, PARM)         // Mobile
+    }
+    If(LEqual(PFLV,FDTP))
+    {
+      Store(0x000F87BD, PARM)         // Desktop
+    }
+
+    Store(Zero, GESF)               // Clear the exit parameter
+    Return(SUCC)                    // "Success"
+  }
+
+  // BIOS POST Completion: Sub-function 1
+
+  If (LEqual(GESF, 1))
+  {
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // Pre-Hires Set Mode: Sub-function 3
+
+  If (LEqual(GESF, 3))
+  {
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // Post-Hires Set Mode: Sub-function 4
+
+  If (LEqual(GESF, 4))
+  {
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // Display Switch: Sub-function 5
+
+  If (LEqual(GESF, 5))
+  {
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // Set TV format: Sub-function 6
+
+  If (LEqual(GESF, 6))
+  {
+
+    //<TODO> If implemented, the input values must be saved into
+    // non-volatile storage for parsing during the next boot.  The
+    // following Sample code is Intel validated implementation.
+
+    Store(And(PARM, 0x0F), ITVF)
+    Store(ShiftRight(And(PARM, 0xF0), 4), ITVM)
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)
+  }
+
+  // Adapter Power State: Sub-function 7
+
+  If (LEqual(GESF, 7))
+  {
+
+    // Upon notification from driver that the Adapter Power State = D0,
+    // check if previous lid event failed.  If it did, retry the lid
+    // event here.
+    If(LEqual(PARM, 0))
+    {
+      Store(CLID, Local0)
+      If(And(0x80000000,Local0))
+      {
+        And(CLID, 0x0000000F, CLID)
+        GLID(CLID)
+      }
+    }
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // Display Power State: Sub-function 8
+
+  If (LEqual(GESF, 8))
+  {
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // Set Boot Display: Sub-function 9
+
+  If (LEqual(GESF, 9))
+  {
+
+    //<TODO> An OEM may elect to implement this method.  In that case,
+    // the input values must be saved into non-volatile storage for
+    // parsing during the next boot.  The following Sample code is Intel
+    // validated implementation.
+
+    And(PARM, 0xFF, IBTT)           // Save the boot display to NVS
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Reserved, "Critical failure"
+  }
+
+  // Set Panel Details: Sub-function 10 (0Ah)
+
+  If (LEqual(GESF, 10))
+  {
+
+    //<TODO> An OEM may elect to implement this method.  In that case,
+    // the input values must be saved into non-volatile storage for
+    // parsing during the next boot.  The following Sample code is Intel
+    // validated implementation.
+
+    // Set the panel-related NVRAM variables based the input from the driver.
+
+    And(PARM, 0xFF, IPSC)
+
+    // Change panel type if a change is requested by the driver (Change if
+    // panel type input is non-zero).  Zero=No change requested.
+
+    If(And(ShiftRight(PARM, 8), 0xFF))
+    {
+      And(ShiftRight(PARM, 8), 0xFF, IPAT)
+      Decrement(IPAT)         // 0 = no change, so fit to CMOS map
+    }
+    And(ShiftRight(PARM, 18), 0x3, IBLC)
+    And(ShiftRight(PARM, 20), 0x7, IBIA)
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Success
+  }
+
+  // Set Internal Graphics: Sub-function 11 (0Bh)
+
+  If (LEqual(GESF, 11))
+  {
+
+    //<TODO> An OEM may elect to implement this method.  In that case,
+    // the input values must be saved into non-volatile storage for
+    // parsing during the next boot.  The following Sample code is Intel
+    // validated implementation.
+
+    And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option
+
+    // Fixed memory/DVMT memory
+
+    And(ShiftRight(PARM, 17), 0xF, IDMS) // Program DVMT/fixed memory size
+
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Success
+  }
+
+  // Post-Hires to DOS FS: Sub-function 16 (10h)
+
+  If (LEqual(GESF, 16))
+  {
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // APM Complete:  Sub-function 17 (11h)
+
+  If (LEqual(GESF, 17))
+  {
+
+    Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state
+    Add(PARM, 0x100, PARM)          // Adjust the lid state, 0 = Unknown
+
+    Store(Zero, GESF)               // Clear the exit parameter
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // Set Spread Spectrum Clocks: Sub-function 18 (12h)
+
+  If (LEqual(GESF, 18))
+  {
+
+    //<TODO> An OEM may elect to implement this method.  In that case,
+    // the input values must be saved into non-volatile storage for
+    // parsing during the next boot.  The following Sample code is Intel
+    // validated implementation.
+
+    If(And(PARM, 1))
+    {
+      If(LEqual(ShiftRight(PARM, 1), 1))
+      {
+        Store(1, ISSC)  // Enable HW SSC, only for clock 1
+      }
+      Else
+      {
+        Store(Zero, GESF)
+        Return(CRIT)    // Failure, as the SSC clock must be 1
+      }
+    }
+    Else
+    {
+      Store(0, ISSC)          // Disable SSC
+    }
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Success
+  }
+
+  // Post VBE/PM Callback: Sub-function 19 (13h)
+
+  If (LEqual(GESF, 19))
+  {
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Not supported, but no failure
+  }
+
+  // Set PAVP Data: Sub-function 20 (14h)
+
+  If (LEqual(GESF, 20))
+  {
+    And(PARM, 0xF, PAVP)    // Store PAVP info
+    Store(Zero, GESF)               // Clear the exit parameter
+    Store(Zero, PARM)
+    Return(SUCC)                    // Success
+  }
+
+  // A call to a reserved "System BIOS callbacks" function was received
+
+  Store(Zero, GESF)                     // Clear the exit parameter
+  Return(SUCC)                          // Reserved, "Critical failure"
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL

@@ -0,0 +1,305 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  IgdOpRn.ASL
+
+Abstract:
+
+  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.
+  This file contains the interrupt handler code for the Integrated
+  Graphics Device (IGD) OpRegion/Software SCI mechanism.
+
+--*/
+
+
+//NOTES:
+//
+// (1)  The code contained in this file inherits the scope in which it
+//      was included.  So BIOS developers must be sure to include this
+//      file in the scope associated with the graphics device
+//      (ex. \_SB.PCI0.GFX0).
+// (2)  Create a _L06 method under the GPE scope to handle the event
+//      generated by the graphics driver.  The _L06 method must call
+//      the GSCI method in this file.
+// (3)  The MCHP operation region assumes that _ADR and _BBN names
+//      corresponding to bus 0, device0, function 0 have been declared
+//      under the PCI0 scope.
+// (4)  Before the first execution of the GSCI method, the base address
+//      of the GMCH SCI OpRegion must be programmed where the driver can
+//      access it. A 32bit scratch register at 0xFC in the IGD PCI
+//      configuration space (B0/D2/F0/R0FCh) is used for this purpose.
+
+//  Define an OperationRegion to cover the GMCH PCI configuration space as
+//  described in the IGD OpRegion specificiation.
+
+//  Define an OperationRegion to cover the IGD PCI configuration space as
+//  described in the IGD OpRegion specificiation.
+
+OperationRegion(IGDP, PCI_Config,0x00,0x100)
+Field(IGDP, AnyAcc, NoLock, Preserve)
+{
+  Offset(0x10),  // GTTMMADR
+  MADR,   32,
+  Offset(0x50),  // GMCH Graphics Control Register
+  ,   1,
+  GIVD,   1,     // IGD VGA disable bit
+  ,   1,
+  GUMA,   5,     // Stolen memory size
+  ,   8,
+  Offset(0x54),
+  ,   4,
+  GMFN,   1,     // Gfx function 1 enable
+  ,   27,
+  Offset(0x5C),  // Stolen Memory Base Address
+  GSTM,   32,
+  Offset(0xE0),  // Reg 0xE8, SWSCI control register
+  GSSE,   1,     // Graphics SCI event (1=event pending)
+  GSSB,   14,    // Graphics SCI scratchpad bits
+  GSES,   1,     // Graphics event select (1=SCI)
+  Offset(0xE4),
+  ASLE,   8,     // Reg 0xE4, ASLE interrupt register
+  ,   24,    // Only use first byte of ASLE reg
+  Offset(0xFC),
+  ASLS,   32,    // Reg 0xFC, Address of the IGD OpRegion
+}
+
+Method (MCHK, 0, Serialized)
+{
+
+  If (LNotEqual (MADR, 0xFFFFFFFF))
+  {
+    OperationRegion(IGMM,SystemMemory,MADR,0x3000)
+    Field(IGMM,AnyAcc, NoLock, Preserve)
+    {
+      Offset(0X20C8),
+      ,    4,
+      DCFE,    4,                     // DISPLAY_CLOCK_FREQUENCY_ENCODING
+    }
+  }
+}
+
+
+//  Define an OperationRegion to cover the IGD OpRegion layout.
+
+OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)
+Field(IGDM, AnyAcc, NoLock, Preserve)
+{
+
+  // OpRegion Header
+
+  SIGN,   128,                    // Signature-"IntelGraphicsMem"
+  SIZE,   32,                     // OpRegion Size
+  OVER,   32,                     // OpRegion Version
+  SVER,   256,                    // System BIOS Version
+  VVER,   128,                    // VBIOS Version
+  GVER,   128,                    // Driver version
+  MBOX,   32,                     // Mailboxes supported
+  DMOD,   32,                     // Driver Model
+  PCON,   32,                     // 96, Platform Configuration
+
+  // OpRegion Mailbox 1 (Public ACPI Methods)
+  // Note: Mailbox 1 is normally reserved for desktop platforms.
+
+  Offset(0x100),
+  DRDY,   32,                     // Driver readiness (ACPI notification)
+  CSTS,   32,                     // Notification status
+  CEVT,   32,                     // Current event
+  Offset(0x120),
+  DIDL,   32,                     // Supported display device ID list
+  DDL2,   32,                     // Allows for 8 devices
+  DDL3,   32,
+  DDL4,   32,
+  DDL5,   32,
+  DDL6,   32,
+  DDL7,   32,
+  DDL8,   32,
+  CPDL,   32,                     // Currently present display list
+  CPL2,   32,                     // Allows for 8 devices
+  CPL3,   32,
+  CPL4,   32,
+  CPL5,   32,
+  CPL6,   32,
+  CPL7,   32,
+  CPL8,   32,
+  CAD1,   32,                     // Currently active display list
+  CAL2,   32,                     // Allows for 8 devices
+  CAL3,   32,
+  CAL4,   32,
+  CAL5,   32,
+  CAL6,   32,
+  CAL7,   32,
+  CAL8,   32,
+  NADL,   32,                     // Next active display list
+  NDL2,   32,                     // Allows for 8 devices
+  NDL3,   32,
+  NDL4,   32,
+  NDL5,   32,
+  NDL6,   32,
+  NDL7,   32,
+  NDL8,   32,
+  ASLP,   32,                     // ASL sleep timeout
+  TIDX,   32,                     // Toggle table index
+  CHPD,   32,                     // Current hot plug enable indicator
+  CLID,   32,                     // Current lid state indicator
+  CDCK,   32,                     // Current docking state indicator
+  SXSW,   32,                     // Display switch notify on resume
+  EVTS,   32,                     // Events supported by ASL (diag only)
+  CNOT,   32,                     // Current OS notifications (diag only)
+  NRDY,   32,
+
+  // OpRegion Mailbox 2 (Software SCI Interface)
+
+  Offset(0x200),                  // SCIC
+  SCIE,   1,                      // SCI entry bit (1=call unserviced)
+  GEFC,   4,                      // Entry function code
+  GXFC,   3,                      // Exit result
+  GESF,   8,                      // Entry/exit sub-function/parameter
+  ,   16,                     // SCIC[31:16] reserved
+  Offset(0x204),                  // PARM
+  PARM,   32,                     // PARM register (extra parameters)
+  DSLP,   32,                     // Driver sleep time out
+
+  // OpRegion Mailbox 3 (BIOS to Driver Notification)
+  // Note: Mailbox 3 is normally reserved for desktop platforms.
+
+  Offset(0x300),
+  ARDY,   32,                     // Driver readiness (power conservation)
+  ASLC,   32,                     // ASLE interrupt command/status
+  TCHE,   32,                     // Technology enabled indicator
+  ALSI,   32,                     // Current ALS illuminance reading
+  BCLP,   32,                     // Backlight brightness
+  PFIT,   32,                     // Panel fitting state or request
+  CBLV,   32,                     // Current brightness level
+  BCLM,   320,                    // Backlight brightness level duty cycle mapping table
+  CPFM,   32,                     // Current panel fitting mode
+  EPFM,   32,                     // Enabled panel fitting modes
+  PLUT,   592,                    // Optional. 74-byte Panel LUT Table
+  PFMB,   32,                     // Optional. PWM Frequency and Minimum Brightness
+  CCDV,   32,                     // Optional. Gamma, Brightness, Contrast values.
+  PCFT,   32,                     // Optional. Power Conservation Features
+
+  Offset(0x3B6),
+  STAT,   32,                     // Status register
+
+  // OpRegion Mailbox 4 (VBT)
+
+  Offset(0x400),
+  GVD1,   0xC000,                 // 6K bytes maximum VBT image
+
+  // OpRegion Mailbox 5 (BIOS to Driver Notification Extension)
+
+  Offset(0x1C00),
+  PHED,   32,                     // Panel Header
+  BDDC,   2048,                   // Panel EDID (Max 256 bytes)
+
+}
+
+
+
+// Convert boot display type into a port mask.
+
+Name (DBTB, Package()
+{
+  0x0000,                         // Automatic
+  0x0007,                         // Port-0 : Integrated CRT
+  0x0038,                         // Port-1 : DVO-A, or Integrated LVDS
+  0x01C0,                         // Port-2 : SDVO-B, or SDVO-B/C
+  0x0E00,                         // Port-3 : SDVO-C
+  0x003F,                         // [CRT + DVO-A / Integrated LVDS]
+  0x01C7,                         // [CRT + SDVO-B] or [CRT + SDVO-B/C]
+  0x0E07,                         // [CRT + SDVO-C]
+  0x01F8,                         // [DVO-A / Integrated LVDS + SDVO-B]
+  0x0E38,                         // [DVO-A / Integrated LVDS + SDVO-C]
+  0x0FC0,                         // [SDVO-B + SDVO-C]
+  0x0000,                         // Reserved
+  0x0000,                         // Reserved
+  0x0000,                         // Reserved
+  0x0000,                         // Reserved
+  0x0000,                         // Reserved
+  0x7000,                         // Port-4: Integrated TV
+  0x7007,                         // [Integrated TV + CRT]
+  0x7038,                         // [Integrated TV + LVDS]
+  0x71C0,                         // [Integrated TV + DVOB]
+  0x7E00                          // [Integrated TV + DVOC]
+})
+
+// Core display clock value table.
+
+Name (CDCT, Package()
+{
+  Package() {160},
+  Package() {200},
+  Package() {267},
+  Package() {320},
+  Package() {356},
+  Package() {400},
+})
+
+// Defined exit result values:
+
+Name (SUCC, 1)                          // Exit result: Success
+Name (NVLD, 2)                          // Exit result: Invalid parameter
+Name (CRIT, 4)                          // Exit result: Critical failure
+Name (NCRT, 6)                          // Exit result: Non-critical failure
+
+
+/************************************************************************;
+;*
+;* Name: GSCI
+;*
+;* Description: Handles an SCI generated by the graphics driver.  The
+;*              PARM and SCIC input fields are parsed to determine the
+;*              functionality requested by the driver.  GBDA or SBCB
+;*              is called based on the input data in SCIC.
+;*
+;* Usage:       The method must be called in response to a GPE 06 event
+;*              which will be generated by the graphics driver.
+;*              Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())}
+;*
+;* Input:       PARM and SCIC are indirect inputs
+;*
+;* Output:      PARM and SIC are indirect outputs
+;*
+;* References:  GBDA (Get BIOS Data method), SBCB (System BIOS Callback
+;*              method)
+;*
+;************************************************************************/
+
+Method (GSCI, 0, Serialized)
+{
+  Include("IgdOGBDA.ASL") // "Get BIOS Data" Functions
+  Include("IgdOSBCB.ASL") // "System BIOS CallBacks"
+
+  If (LEqual(GEFC, 4))
+  {
+    Store(GBDA(), GXFC)     // Process Get BIOS Data functions
+  }
+
+  If (LEqual(GEFC, 6))
+  {
+    Store(SBCB(), GXFC)     // Process BIOS Callback functions
+  }
+
+  Store(0, GEFC)                  // Wipe out the entry function code
+  Store(1, SCIS)                  // Clear the GUNIT SCI status bit in PCH ACPI I/O space.
+  Store(0, GSSE)                  // Clear the SCI generation bit in PCI space.
+  Store(0, SCIE)                  // Clr SCI serviced bit to signal completion
+
+  Return(Zero)
+}
+
+// Include MOBLFEAT.ASL for mobile systems only.  Remove for desktop.
+Include("IgdOMOBF.ASL")     // IGD SCI mobile features

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl

@@ -0,0 +1,177 @@
+/** @file
+Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Device(IOTD) { 
+  Name(_HID, "MSFT8000")
+  Name(_CID, "MSFT8000")
+  
+  Name(_CRS, ResourceTemplate() {  
+    // Index 0 
+    SPISerialBus(            // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI
+      1,                     // Device selection
+      PolarityLow,           // Device selection polarity
+      FourWireMode,          // wiremode
+      8,                     // databit len
+      ControllerInitiated,   // slave mode
+      8000000,               // Connection speed
+      ClockPolarityLow,      // Clock polarity
+      ClockPhaseSecond,      // clock phase
+      "\\_SB.SPI1",          // ResourceSource: SPI bus controller name
+      0,                     // ResourceSourceIndex
+      ResourceConsumer,      // Resource usage
+      JSPI,                  // DescriptorName: creates name for offset of resource descriptor
+      )                      // Vendor Data  
+    
+    // Index 1     
+    I2CSerialBus(            // Pin 13, 15 of JP1, for SIO_I2C5 (signal)
+      0x00,                  // SlaveAddress: bus address (TBD)
+      ,                      // SlaveMode: default to ControllerInitiated
+      400000,                // ConnectionSpeed: in Hz
+      ,                      // Addressing Mode: default to 7 bit
+      "\\_SB.I2C6",          // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))
+      ,
+      ,
+      JI2C,                  // Descriptor Name: creates name for offset of resource descriptor
+      )                      // VendorData
+    
+    // Index 2
+    UARTSerialBus(           // Pin 17, 19 of JP1, for SIO_UART2
+      115200,                // InitialBaudRate: in bits ber second
+      ,                      // BitsPerByte: default to 8 bits
+      ,                      // StopBits: Defaults to one bit
+      0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled
+      ,                      // IsBigEndian: default to LittleEndian
+      ,                      // Parity: Defaults to no parity
+      ,                      // FlowControl: Defaults to no flow control
+      32,                    // ReceiveBufferSize
+      32,                    // TransmitBufferSize
+      "\\_SB.URT2",          // ResourceSource: UART bus controller name
+      ,
+      ,
+      UAR2,                  // DescriptorName: creates name for offset of resource descriptor
+      )                      
+    
+    // Index 3
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0}  // Pin 21 of JP1 (GPIO_S5[00])
+    // Index 4
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} 
+    
+    // Index 5
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1}  // Pin 23 of JP1 (GPIO_S5[01])
+    // Index 6
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}
+    
+    // Index 7
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2}  // Pin 25 of JP1 (GPIO_S5[02])
+    // Index 8
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} 
+    
+    // Index 9
+    UARTSerialBus(           // Pin 6, 8, 10, 12 of JP1, for SIO_UART1
+      115200,                // InitialBaudRate: in bits ber second
+      ,                      // BitsPerByte: default to 8 bits
+      ,                      // StopBits: Defaults to one bit
+      0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled
+      ,                      // IsBigEndian: default to LittleEndian
+      ,                      // Parity: Defaults to no parity
+      FlowControlHardware,   // FlowControl: Defaults to no flow control
+      32,                    // ReceiveBufferSize
+      32,                    // TransmitBufferSize
+      "\\_SB.URT1",          // ResourceSource: UART bus controller name
+      ,
+      ,
+      UAR1,              // DescriptorName: creates name for offset of resource descriptor
+      )  
+    
+    // Index 10
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62}  // Pin 14 of JP1 (GPIO_SC[62])
+    // Index 11
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} 
+    
+    // Index 12
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63}  // Pin 16 of JP1 (GPIO_SC[63])
+    // Index 13
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} 
+    
+    // Index 14
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65}  // Pin 18 of JP1 (GPIO_SC[65])
+    // Index 15
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} 
+    
+    // Index 16
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64}  // Pin 20 of JP1 (GPIO_SC[64])
+    // Index 17
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} 
+    
+    // Index 18
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94}  // Pin 22 of JP1 (GPIO_SC[94])
+    // Index 19
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} 
+    
+    // Index 20
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95}  // Pin 24 of JP1 (GPIO_SC[95])
+    // Index 21
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} 
+    
+    // Index 22
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54}  // Pin 26 of JP1 (GPIO_SC[54])
+    // Index 23
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}
+  })
+
+  Name(_DSD, Package() {
+    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+    Package(1) {	  // Just one Property for IOT (at this time) 
+      Package(2) {	//The <20>symbolic-identifiers<72> property
+        "symbolic-identifiers", 
+        Package() {	//Contains all the <resource index, symbolic-identifier> pairs       
+          0, "SPI0",	  
+          1, "I2C5",		
+          2, "UART2",
+          3, 21,       // Pin 21 of JP1 (GPIO_S5[00])
+          4, 21,       // Pin 21 for separate resource. 
+          5, 23,       // Pin 23 of JP1 (GPIO_S5[01])
+          6, 23,
+          7, 25,       // Pin 25 of JP1 (GPIO_S5[02])
+          8, 25,
+          9, "UART1",
+          10, 14,      // Pin 14 of JP1 (GPIO_SC[62])
+          11, 14,
+          12, 16,      // Pin 16 of JP1 (GPIO_SC[63])
+          13, 16,
+          14, 18,      // Pin 18 of JP1 (GPIO_SC[65])
+          15, 18,
+          16, 20,      // Pin 20 of JP1 (GPIO_SC[64])
+          17, 20,
+          18, 22,      // Pin 22 of JP1 (GPIO_SC[94])
+          19, 22,
+          20, 24,      // Pin 24 of JP1 (GPIO_SC[95])
+          21, 24,
+          22, 26,      // Pin 26 of JP1 (GPIO_SC[54])
+          23, 26
+        }
+      } 
+    }
+  })
+  
+  Method(_STA,0,Serialized) {
+    
+    //
+    // Only report IoT virtual device when all pins' configuration follows MSFT's datasheet.
+    //
+    If (LEqual(IOT, 1)) {
+      Return (0xF)
+    }
+    
+    Return (0x0)
+  }
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL

@@ -0,0 +1,157 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+Device(FWHD) // Firmware Hub Device
+{
+  Name(_HID,EISAID("INT0800"))
+
+  Name(_CRS,ResourceTemplate()
+  {
+    Memory32Fixed(ReadOnly,0xFF000000,0x1000000)
+  })
+}
+
+Device(IPIC) // 8259 PIC
+{
+  Name(_HID,EISAID("PNP0000"))
+
+  Name(_CRS,ResourceTemplate()
+  {
+    IO(Decode16,0x20,0x20,0x01,0x02)
+    IO(Decode16,0x24,0x24,0x01,0x02)
+    IO(Decode16,0x28,0x28,0x01,0x02)
+    IO(Decode16,0x2C,0x2C,0x01,0x02)
+    IO(Decode16,0x30,0x30,0x01,0x02)
+    IO(Decode16,0x34,0x34,0x01,0x02)
+    IO(Decode16,0x38,0x38,0x01,0x02)
+    IO(Decode16,0x3C,0x3C,0x01,0x02)
+    IO(Decode16,0xA0,0xA0,0x01,0x02)
+    IO(Decode16,0xA4,0xA4,0x01,0x02)
+    IO(Decode16,0xA8,0xA8,0x01,0x02)
+    IO(Decode16,0xAC,0xAC,0x01,0x02)
+    IO(Decode16,0xB0,0xB0,0x01,0x02)
+    IO(Decode16,0xB4,0xB4,0x01,0x02)
+    IO(Decode16,0xB8,0xB8,0x01,0x02)
+    IO(Decode16,0xBC,0xBC,0x01,0x02)
+    IO(Decode16,0x4D0,0x4D0,0x01,0x02)
+    IRQNoFlags() {2}
+  })
+}
+
+Device(LDRC) // LPC Device Resource Consumption
+{
+  Name(_HID,EISAID("PNP0C02"))
+
+  Name(_UID,2)
+
+  Name(_CRS,ResourceTemplate()
+  {
+    IO(Decode16,0x4E,0x4E,0x1,0x02)         // LPC Slot Access.
+    IO(Decode16,0x61,0x61,0x1,0x1)          // NMI Status.
+    IO(Decode16,0x63,0x63,0x1,0x1)          // Processor I/F.
+    IO(Decode16,0x65,0x65,0x1,0x1)          // Processor I/F.
+    IO(Decode16,0x67,0x67,0x1,0x1)          // Processor I/F.
+    IO(Decode16,0x70,0x70,0x1,0x1)          // NMI Enable.
+    IO(Decode16,0x80,0x80,0x1,0x10)         // Postcode.
+    IO(Decode16,0x92,0x92,0x1,0x1)          // Processor I/F.
+    IO(Decode16,0xB2,0xB2,0x01,0x02)        // Software SMI.
+    IO(Decode16,0x680,0x680,0x1,0x20)       // 32 Byte I/O.
+    IO(Decode16,0x400,0x400,0x1,0x80)       // ACPI Base.
+    IO(Decode16,0x500,0x500,0x1,0xFF)       // GPIO Base.
+  })
+}
+
+Device(TIMR) // 8254 Timer
+{
+  Name(_HID,EISAID("PNP0100"))
+
+  Name(_CRS,ResourceTemplate()
+  {
+    IO(Decode16,0x40,0x40,0x01,0x04)
+    IO(Decode16,0x50,0x50,0x10,0x04)
+    IRQNoFlags() {0}
+  })
+}
+
+Device(IUR3) // Internal UART
+{
+  Name(_HID, EISAID("PNP0501"))
+
+  Name(_UID,1)
+
+  // Status Method for internal UART
+
+  Method(_STA,0,Serialized)
+  {
+    // Only report resources to the OS if internal UART is
+    // not set to Disabled in BIOS Setup.
+
+    If(LEqual(USEL,0))
+    {
+      If(LEqual(PU1E,1))
+      {
+        Store(1,UI3E) // Enable IRQ3 for UART
+        Store(1,UI4E) // Enable IRQ4 for UART
+        Store(1,C1EN) // Enable UART
+        Return(0x000F)
+      }
+    }
+
+    Return(0x0000)
+  }
+
+  // Disable Method for internal UART
+
+  Method(_DIS,0,Serialized)
+  {
+    Store(0,UI3E)
+    Store(0,UI4E)
+    Store(0,C1EN)
+  }
+
+  // Current Resource Setting Method for internal UART
+
+  Method(_CRS,0,Serialized)
+  {
+    // Create the Buffer that stores the Resources to
+    // be returned.
+
+    Name(BUF0,ResourceTemplate()
+    {
+      IO(Decode16,0x03F8,0x03F8,0x01,0x08)
+      IRQNoFlags() {3}
+    })
+
+    Name(BUF1,ResourceTemplate()
+    {
+      IO(Decode16,0x03F8,0x03F8,0x01,0x08)
+      IRQNoFlags() {4}
+    })
+
+    If (LLessEqual(SRID, 0x04))
+    {
+      Return(BUF0)
+    } Else
+    {
+      Return(BUF1)
+    }
+  }
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl

@@ -0,0 +1,65 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+// LPC Bridge - Device 31, Function 0
+// Define the needed LPC registers used by ASL.
+
+scope(\_SB)
+{
+  OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C)
+  Field(ILBR, AnyAcc, NoLock, Preserve)
+  {
+    Offset(0x08), // 0x08
+    PARC,   8,
+    PBRC,   8,
+    PCRC,   8,
+    PDRC,   8,
+    PERC,   8,
+    PFRC,   8,
+    PGRC,   8,
+    PHRC,   8,
+    Offset(0x88), // 0x88
+    ,       3,
+    UI3E,   1,
+    UI4E,   1
+  }
+
+  Include ("98_LINK.ASL")
+}
+
+OperationRegion(LPC0, PCI_Config, 0x00, 0xC0)
+Field(LPC0, AnyAcc, NoLock, Preserve)
+{
+  Offset(0x08), // 0x08
+  SRID,   8,  // Revision ID
+  Offset(0x080), // 0x80
+  C1EN,   1, // COM1 Enable
+  ,      31
+}
+
+
+Include ("LPC_DEV.ASL")
+
+
+
+
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc

@@ -0,0 +1,229 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+--*/
+
+//
+// Include files
+//
+
+#include <PiDxe.h>
+#include <IndustryStandard/Acpi50.h>
+
+
+
+//
+// LPIT Definitions
+//
+
+#define EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION 0x1
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+typedef union _EFI_ACPI_LPI_STATE_FLAGS {
+  struct {
+    UINT32 Disabled           :1;
+    UINT32 CounterUnavailable :1;
+    UINT32 Reserved           :30;
+  };
+  UINT32 AsUlong;
+} EFI_ACPI_LPI_STATE_FLAGS, *PEFI_ACPI_LPI_STATE_FLAGS;
+
+// Only Mwait LPI here:
+
+typedef struct _EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR {
+  UINT32 Type;        // offset: 0
+  UINT32 Length;      // offset: 4
+  UINT16 UniqueId;    // offset: 8
+  UINT8 Reserved[2];  // offset: 9
+  EFI_ACPI_LPI_STATE_FLAGS Flags; // offset: 12
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EntryTrigger; // offset: 16
+  UINT32 Residency;   // offset: 28
+  UINT32 Latency;     // offset: 32
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; // offset: 36
+  UINT64 ResidencyCounterFrequency; //offset: 48
+} EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR;
+
+
+//
+// Defines for LPIT table, some are VLV specific
+//
+
+
+// signature "LPIT"
+#define EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE  0x5449504c
+
+#define EFI_ACPI_OEM_LPIT_REVISION                      0x00000000
+
+#define EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE    0x0
+#define EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG  0x0
+#define EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K   0x8000    // 32768
+
+//
+// LPI state count (4 on VLV: S0ir, S0i1, S0i2, S0i3)
+//
+
+#define EFI_ACPI_VLV_LPI_STATE_COUNT          0x4
+
+//
+// LPI TRIGGER (HW C7 on VLV),
+// TOFIX!!!
+//
+#define EFI_ACPI_VLV_LPI_TRIGGER {0x7F,0x1,0x2,0x0,0x64}
+
+//
+// LPI residency counter (MMIO)
+//
+#define  EFI_ACPI_VLV_LPI_RES_COUNTER0   {0x0,32,0x0,0x03,0xFED03080}
+#define  EFI_ACPI_VLV_LPI_RES_COUNTER1   {0x0,32,0x0,0x03,0xFED03084}
+#define  EFI_ACPI_VLV_LPI_RES_COUNTER2   {0x0,32,0x0,0x03,0xFED03088}
+#define  EFI_ACPI_VLV_LPI_RES_COUNTER3   {0x0,32,0x0,0x03,0xFED0308C}
+
+//
+// LPI break-even residency in us - all match S0i3 residency
+// Residency estimate: Latency x 3
+//
+#define  EFI_ACPI_VLV_LPI_MIN_RES0   15000
+#define  EFI_ACPI_VLV_LPI_MIN_RES1   15000
+#define  EFI_ACPI_VLV_LPI_MIN_RES2   15000
+#define  EFI_ACPI_VLV_LPI_MIN_RES3   15000
+
+//
+// LPI latency in us - all match S0i3 latency
+//
+#define  EFI_ACPI_VLV_LPI_LATENCY0   5000
+#define  EFI_ACPI_VLV_LPI_LATENCY1   5000
+#define  EFI_ACPI_VLV_LPI_LATENCY2   5000
+#define  EFI_ACPI_VLV_LPI_LATENCY3   5000
+
+
+//
+// LPI ID
+//
+#define  EFI_ACPI_VLV_LPI_UNIQUE_ID0   0
+#define  EFI_ACPI_VLV_LPI_UNIQUE_ID1   1
+#define  EFI_ACPI_VLV_LPI_UNIQUE_ID2   2
+#define  EFI_ACPI_VLV_LPI_UNIQUE_ID3   3
+
+//
+//  LPI ACPI table header
+//
+
+
+typedef struct _EFI_ACPI_LOW_POWER_IDLE_TABLE {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR     LpiStates[EFI_ACPI_VLV_LPI_STATE_COUNT];
+} EFI_ACPI_LOW_POWER_IDLE_TABLE;
+
+#pragma pack()
+
+EFI_ACPI_LOW_POWER_IDLE_TABLE Lpit = {
+
+  //
+  // Header
+  //
+
+
+  EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE,
+  sizeof (EFI_ACPI_LOW_POWER_IDLE_TABLE),
+  EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION ,
+
+  //
+  // Checksum will be updated at runtime
+  //
+  0x00,
+
+  //
+  // It is expected that these values will be updated at runtime
+  //
+  ' ', ' ', ' ', ' ', ' ', ' ',
+
+  0,
+  EFI_ACPI_OEM_LPIT_REVISION,
+  0,
+  0,
+
+
+
+  //
+  // Descriptor
+  //
+  {
+    {
+      EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,
+      sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),
+      EFI_ACPI_VLV_LPI_UNIQUE_ID0,
+      {0,0},
+      {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG},   // Flags
+      EFI_ACPI_VLV_LPI_TRIGGER,  //EntryTrigger
+      EFI_ACPI_VLV_LPI_MIN_RES0, //Residency
+      EFI_ACPI_VLV_LPI_LATENCY0, //Latency
+      EFI_ACPI_VLV_LPI_RES_COUNTER0, //ResidencyCounter
+      EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency
+    },
+    {
+      EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,
+      sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),
+      EFI_ACPI_VLV_LPI_UNIQUE_ID1,
+      {0,0},
+      {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG},   // Flags
+      EFI_ACPI_VLV_LPI_TRIGGER,  //EntryTrigger
+      EFI_ACPI_VLV_LPI_MIN_RES1, //Residency
+      EFI_ACPI_VLV_LPI_LATENCY1, //Latency
+      EFI_ACPI_VLV_LPI_RES_COUNTER1, //ResidencyCounter
+      EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency
+    },
+    {
+      EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,
+      sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),
+      EFI_ACPI_VLV_LPI_UNIQUE_ID2,
+      {0,0},
+      {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG},   // Flags
+      EFI_ACPI_VLV_LPI_TRIGGER,  //EntryTrigger
+      EFI_ACPI_VLV_LPI_MIN_RES2, //Residency
+      EFI_ACPI_VLV_LPI_LATENCY2, //Latency
+      EFI_ACPI_VLV_LPI_RES_COUNTER2, //ResidencyCounter
+      EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency
+    },
+    {
+      EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,
+      sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),
+      EFI_ACPI_VLV_LPI_UNIQUE_ID3,
+      {0,0},
+      {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG},   // Flags
+      EFI_ACPI_VLV_LPI_TRIGGER,  //EntryTrigger
+      EFI_ACPI_VLV_LPI_MIN_RES3, //Residency
+      EFI_ACPI_VLV_LPI_LATENCY3, //Latency
+      EFI_ACPI_VLV_LPI_RES_COUNTER3, //ResidencyCounter
+      EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency
+    }
+  }
+
+};
+
+
+VOID*
+ReferenceAcpiTable (
+  VOID
+  )
+{
+  //
+  // Reference the table being generated to prevent the optimizer from
+  // removing the data structure from the executable
+  //
+  return (VOID*)&Lpit;
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h

@@ -0,0 +1,195 @@
+/*++
+
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+  Madt.h
+
+Abstract:
+
+  This file describes the contents of the ACPI Multiple APIC Description
+  Table (MADT).  Some additional ACPI values are defined in Acpi1_0.h and
+  Acpi2_0.h.
+  To make changes to the MADT, it is necessary to update the count for the
+  APIC structure being updated, and to modify table found in Madt.c.
+
+--*/
+
+#ifndef _MADT_H
+#define _MADT_H
+
+//
+// Statements that include other files
+//
+#include "AcpiTablePlatform.h"
+#include <IndustryStandard/Acpi10.h>
+#include <IndustryStandard/Acpi20.h>
+#include <IndustryStandard/Acpi30.h>
+#include "Platform.h"
+
+//
+// MADT Definitions
+//
+#define EFI_ACPI_OEM_MADT_REVISION                      0x00000000
+//
+// Multiple APIC Flags are defined in AcpiX.0.h
+//
+#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS  (EFI_ACPI_1_0_PCAT_COMPAT)
+#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS  (EFI_ACPI_2_0_PCAT_COMPAT)
+#define EFI_ACPI_3_0_MULTIPLE_APIC_FLAGS  (EFI_ACPI_3_0_PCAT_COMPAT)
+#define EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS  (EFI_ACPI_4_0_PCAT_COMPAT)
+
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT             MAX_CPU_NUM
+#define EFI_ACPI_LOCAL_APIC_NMI_COUNT                   MAX_CPU_NUM
+#define EFI_ACPI_IO_APIC_COUNT                          1
+#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT        2
+#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT    0
+#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT      0
+#define EFI_ACPI_IO_SAPIC_COUNT                         0
+#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT            0
+#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT       0
+
+//
+// MADT structure
+//
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// ACPI 1.0 Table structure
+//
+typedef struct {
+  EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
+  EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE           LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0
+  EFI_ACPI_1_0_IO_APIC_STRUCTURE                        IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
+  EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE      Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
+  EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE  NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
+  EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE                 LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
+  EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE    LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];
+#endif
+
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+//
+// ACPI 2.0 Table structure
+//
+typedef struct {
+  EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
+  EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE           LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0
+  EFI_ACPI_2_0_IO_APIC_STRUCTURE                        IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
+  EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE      Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
+  EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE  NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
+  EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE                 LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
+  EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE    LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_IO_SAPIC_COUNT > 0
+  EFI_ACPI_2_0_IO_SAPIC_STRUCTURE                       IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0
+  EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE          LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0
+  EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE     PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
+#endif
+
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+//
+// ACPI 3.0 Table structure
+//
+typedef struct {
+  EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0           // Type 0x00
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE           LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0                        // Type 0x01
+  EFI_ACPI_3_0_IO_APIC_STRUCTURE                        IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0      // Type 0x02
+  EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE      Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0  // Type 0x03
+  EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE  NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0                 // Type 0x04
+  EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE                 LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0    // Type 0x05
+  EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE    LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_IO_SAPIC_COUNT > 0                       // Type 0x06
+  EFI_ACPI_3_0_IO_SAPIC_STRUCTURE                       IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0          // Type 0x07 : This table changes in madt 2.0
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE          LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0     // Type 0x08
+  EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE     PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
+#endif
+
+} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack()
+
+#endif

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc

@@ -0,0 +1,184 @@
+/*++
+
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  Madt3.0.c
+
+Abstract:
+
+  This file contains a structure definition for the ACPI 2.0 Multiple APIC
+  Description Table (MADT).  Any changes to the MADT table require updating the
+  respective structure count in Madt.h and then adding the structure to the
+  MADT defined in this file.  The table layout is defined in Madt.h and the
+  table contents are defined in Acpi3_0.h and Madt.h.
+
+--*/
+
+//
+// Statements that include other files
+//
+#include "Madt.h"
+#include <IndustryStandard/Acpi50.h>
+
+//
+// Multiple APIC Description Table
+//
+EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE  Madt = {
+  EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, // **Signatures are the same 1.0-3.0 because it says "APIC".
+  sizeof (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE),  // **Length
+  EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+  //
+  // EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,  // **Table Revision must be 2.0 for ACPI 3.0
+  // Checksum will be updated at runtime
+  //
+  0x00, // **Check sum
+  //
+  // It is expected that these values will be programmed at runtime
+  //
+  ' ',                        // OEMID
+  ' ',                        // Creative way to
+  ' ',                        // make six bytes
+  ' ',                        // of space in
+  ' ',                        // a table for
+  ' ',                        // **OEMID
+  0,                          // **OEM Table ID
+  EFI_ACPI_OEM_MADT_REVISION, // **OEM Revision
+  0,                          // **Creator ID
+  0,                          // **Creator Revision
+  //
+  // MADT specific fields
+  //
+  LOCAL_APIC_ADDRESS,               // **Local APIC Address
+  EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS, // **Flags
+  //
+  // Processor Local APIC Structure
+  // Correct processor order, Primary threads first then Hyper threads
+  // And correct APIC-ids
+  // This text below is included as a reference until Thurley is 100%:
+  // According to EDS the Local APIC ID is determined based of a bit structure
+  // Bit 24: Core ID Bit 25: Core Pair ID Bit 26-27: Reserved Bit 28-30: Socket ID Bit 31: Reserved
+  // 4 Sockets and 4 Cores per Socket.
+  // So possible LAPIC IDs 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33
+  // Static Entries 00, 10, 20, 30, 01, 11, 21, 31, 02, 12, 22, 32, 03, 13, 23, 33
+  // BSP needs to be first entry in table. Check before boot. If BSP non zero need to rotate the entries.
+  // Suppore BSP is LAPIC ID xy. Rotate the table by using formula [x + (y * 4)]
+  // So if BSP LAPIC ID is 21 then table rotated 6 times.
+  // End of Reference Text.
+  // Thurley is supposed to be 2 sockets, 4 cores, and hyperthreading available per each core.
+  // 2 (sockets) x 4 (cores) = 8 (processors non-HT), 8 (processors non-HT) x 2 (HT/proc) = 16 (HT procs)
+  // Rhyme & reason of the ordering below.  This is a best guess ordering for now,
+  // Thurley EPS may give better info on LAPIC numbers.
+  // Ordering was established to help dissipate heat across two sockets evenly.
+  // Since logical processor number only has to be unique, I followed
+  // a similar approach to high end servers and have the first digit of the LAPIC
+  // id the socket number.
+  //
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC,                    // Type 0x00
+  sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+  0x01,                                                 // Processor ID
+  0x00,                                                 // Local APIC ID
+  0x00000001,                                           // Flags - Disabled (until initialized by platform driver)
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC,                    // Type
+  sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+  0x02,                                                 // Processor ID
+  0x02,                                                 // Local APIC ID //Todo: Temp change APIC ID order for fixing VLV X0 not enable 2 CPU in Windows.
+  0x00000001,                                           // Flags - Disabled (until initialized by platform driver)
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC,                    // Type
+  sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+  0x03,                                                 // Processor ID
+  0x04,                                                 // Local APIC ID
+  0x00000001,                                           // Flags - Disabled (until initialized by platform driver)
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC,                    // Type
+  sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+  0x04,                                                 // Processor ID
+  0x06,                                                 // Local APIC ID
+  0x00000001,                                           // Flags - Disabled (until initialized by platform driver)
+  //
+  // ***************   IO APIC Structure ******************
+  //
+  //
+  //
+  // **************************  I/O APIC  **************
+  //
+  EFI_ACPI_3_0_IO_APIC,                     // Type 0x01
+  sizeof (EFI_ACPI_3_0_IO_APIC_STRUCTURE),  // Length
+  ICH_IOAPIC_ID,                            // IO APIC ID
+  EFI_ACPI_RESERVED_BYTE,                   // Reserved    EFI_ACPI_RESERVED_BYTE
+  IO_APIC_ADDRESS,                          // IO APIC Address (physical)   0xFEC00000
+  0x18 * 0,                                 // Global System Interrupt Base
+
+  //
+  // Interrupt Source Override Structure: Sample
+  //
+  // EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE,                   // Type  0x02
+  // sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+  // 0x00,                                                     // Bus
+  // 0x00,                                                     // Source
+  // 0x00000000,                                               // Global System Interrupt
+  // 0x0000,                                                   // Flags
+  //
+  // IRQ0=>IRQ2 Interrupt Source Override Structure
+  //
+  EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type  0x02
+  sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),  // Length
+  0x00,       // Bus - ISA
+  0x00,       // Source - IRQ0
+  0x00000002, // Global System Interrupt - IRQ2
+  0x0000,     // Flags - Conforms to specifications of the bus
+  //
+  // ISO (SCI Active High) Interrupt Source Override Structure
+  //
+  EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type  0x02
+  sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),  // Length
+  0x00,       // Bus - ISA
+  0x09,       // Source - IRQ0
+  0x00000009, // Global System Interrupt - IRQ2
+  0x000D,     // Flags - Level-tiggered, Active High
+
+
+
+  EFI_ACPI_3_0_LOCAL_APIC_NMI,                    // Type
+  sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length
+  0x01,                                           // ACPI Processor ID
+  0x000D,                                         // Flags - Level-tiggered, Active High
+  0x01,                                           // Local APIC LINT#
+  EFI_ACPI_3_0_LOCAL_APIC_NMI,                    // Type
+  sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length
+  0x02,                                           // ACPI Processor ID
+  0x000D,                                         // Flags - Level-tiggered, Active High
+  0x01,                                           // Local APIC LINT#
+  EFI_ACPI_3_0_LOCAL_APIC_NMI,                    // Type
+  sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length
+  0x03,                                           // ACPI Processor ID
+  0x000D,                                         // Flags - Level-tiggered, Active High
+  0x01,                                           // Local APIC LINT#
+  EFI_ACPI_3_0_LOCAL_APIC_NMI,                    // Type
+  sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length
+  0x04,                                           // ACPI Processor ID
+  0x000D,                                         // Flags - Level-tiggered, Active High
+  0x01,                                           // Local APIC LINT#
+};
+
+VOID*
+ReferenceAcpiTable (
+  VOID
+  )
+{
+  //
+  // Reference the table being generated to prevent the optimizer from
+  // removing the data structure from the executable
+  //
+  return (VOID*)&Madt;
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc

@@ -0,0 +1,92 @@
+/*++
+
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  Mcfg.c
+
+Abstract:
+
+  This file contains a structure definition for the ACPI Memory mapped
+  configuration space base address Description Table (MCFG).  Any changes
+  to the MCFG table require updating the respective structure count in
+  Mcfg.h and then adding the structure to the MCFG defined in this file.
+  The table layout is defined in Mcfg.h and the table contents are defined
+  in McfgTable.h and Mcfg.h.
+
+--*/
+
+//
+// Statements that include other files
+//
+#include <Mcfg.h>
+
+//
+// MCFG Table definition
+//
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE MCFG = {
+  EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE,
+  sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE),
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION,
+  //
+  // Checksum will be updated at runtime
+  //
+  0x00,
+  //
+  // It is expected that these values will be programmed at runtime
+  //
+  ' ',
+  ' ',
+  ' ',
+  ' ',
+  ' ',
+  ' ',
+
+  0,
+  EFI_ACPI_OEM_MCFG_REVISION,
+  0,
+  0,
+  //
+  // Beginning of MCFG specific fields
+  //
+  EFI_ACPI_RESERVED_QWORD,
+  //
+  // Sample Memory Mapped Configuration Space Base Address Structure
+  //
+  // 0x0,                                                              // Base Address
+  // 0x0,                                                              // PCI Segment Group Number
+  // 0x0,                                                              // Start Bus Number
+  // 0x0,                                                              // End Bus Number
+  // EFI_ACPI_RESERVED_DWORD,                                          // Reserved
+  //
+  // Memory Mapped Configuration Space Base Address Structure
+  //
+  0x0,                      // Base Address, will be updated by AcpiPlatform
+  0x0,                      // PCI Segment Group Number
+  0x0,                      // Start Bus Number
+  PLATFORM_MAX_BUS_NUM,     // End Bus Number
+  EFI_ACPI_RESERVED_DWORD,  // Reserved
+};
+
+VOID*
+ReferenceAcpiTable (
+  VOID
+  )
+{
+  //
+  // Reference the table being generated to prevent the optimizer from
+  // removing the data structure from the executable
+  //
+  return (VOID*)&MCFG;
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL

@@ -0,0 +1,96 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+
+Scope (\_SB.PCI0)
+{
+
+  Device(PDRC)   // PCI Device Resource Consumption
+  {
+    Name(_HID,EISAID("PNP0C02"))
+
+    Name(_UID,1)
+
+    Name(BUF0,ResourceTemplate()
+    {
+      //
+      // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
+      // Forced hard code at the moment.
+      //
+      //Memory32Fixed(ReadWrite,0,0,PCIX)       // PCIEX BAR
+      Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX)
+
+      //
+      // SPI BAR. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR
+
+      //
+      // PMC BAR. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR
+
+      //
+      // SMB BAR. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR
+
+      //
+      // IO BAR. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR
+
+      //
+      // ILB BAR. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR
+
+      //
+      // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h
+      //
+      Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR
+
+      //
+      // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
+      //
+      Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH)
+
+      //
+      // MPHY BAR. Check if the hard code meets the real configuration.
+      // If not, dynamically update it like the _CRS method below.
+      //
+      Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB)       // MPHY BAR
+    })
+
+    Method(_CRS,0,Serialized)
+    {
+
+      Return(BUF0)
+    }
+
+  }
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl

@@ -0,0 +1,685 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+Scope(\)
+{
+  //
+  // Define VLV ABASE I/O as an ACPI operating region. The base address
+  // can be found in Device 31, Registers 40-43h.
+  //
+  OperationRegion(PMIO, SystemIo, \PMBS, 0x46)
+  Field(PMIO, ByteAcc, NoLock, Preserve)
+  {
+    ,      8,
+    PWBS,  1,       // Power Button Status
+    Offset(0x20),
+    ,      13,
+    PMEB,  1,     // PME_B0_STS
+    Offset(0x42),     // General Purpose Control
+    ,      1,
+    GPEC,  1
+  }
+  Field(PMIO, ByteAcc, NoLock, WriteAsZeros)
+  {
+    Offset(0x20),     // GPE0 Status
+    ,      4,
+    PSCI,  1,       // PUNIT SCI Status
+    SCIS,  1        // GUNIT SCI Status
+  }
+
+
+
+  //
+  // Define a Memory Region that will allow access to the PMC
+  // Register Block.  Note that in the Intel Reference Solution, the PMC
+  // will get fixed up dynamically during POST.
+  //
+  OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register
+  Field(PMCR,DWordAcc,Lock,Preserve)
+  {
+    Offset(0x00),   //  Function Disable Register
+    L10D,  1,         //  (0) LPIO1 DMA Disable
+    L11D,  1,         //  (1) LPIO1 PWM #1 Disable
+    L12D,  1,         //  (2) LPIO1 PWM #2 Disable
+    L13D,  1,         //  (3) LPIO1 HS-UART #1 Disable
+    L14D,  1,         //  (4) LPIO1 HS-UART #2 Disable
+    L15D,  1,         //  (5) LPIO1 SPI Disable
+    ,          2,     //  (6:7) Reserved
+    SD1D,  1,         //  (8) SCC SDIO #1 Disable
+    SD2D,  1,         //  (9) SCC SDIO #2 Disable
+    SD3D,  1,         //  (10) SCC SDIO #3 Disable
+    HSID,  1,         //  (11)
+    HDAD,  1,         //  (12) Azalia Disable
+    LPED,  1,         //  (13) LPE Disable
+    OTGD,  1,         //  (14) USB OTG Disable
+    ,          1,     //  (15) USH Disable
+    ,          1,     //  (16)
+    ,          1,     //  (17)
+    ,          1,     //  (18) USB Disable
+    ,          1,     //  (19) SEC Disable
+    RP1D,  1,         //  (20) Root Port 0 Disable
+    RP2D,  1,         //  (21) Root Port 1 Disable
+    RP3D,  1,         //  (22) Root Port 2 Disable
+    RP4D,  1,         //  (23) Root Port 3 Disable
+    L20D,  1,         //  (24) LPIO2 DMA Disable
+    L21D,  1,         //  (25) LPIO2 I2C #1 Disable
+    L22D,  1,         //  (26) LPIO2 I2C #2 Disable
+    L23D,  1,         //  (27) LPIO2 I2C #3 Disable
+    L24D,  1,         //  (28) LPIO2 I2C #4 Disable
+    L25D,  1,         //  (29) LPIO2 I2C #5 Disable
+    L26D,  1,         //  (30) LPIO2 I2C #6 Disable
+    L27D,  1          //  (31) LPIO2 I2C #7 Disable
+  }
+
+
+  OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers
+  Field(CLKC,DWordAcc,Lock,Preserve)
+  {
+    Offset(0x00),   //  PLT_CLK_CTL_0
+    CKC0, 2,
+    CKF0, 1,
+    ,     29,
+    Offset(0x04),   //  PLT_CLK_CTL_1
+    CKC1, 2,
+    CKF1, 1,
+    ,     29,
+    Offset(0x08),   //  PLT_CLK_CTL_2
+    CKC2,  2,
+    CKF2, 1,
+    ,     29,
+    Offset(0x0C),   //  PLT_CLK_CTL_3
+    CKC3,  2,
+    CKF3, 1,
+    ,     29,
+    Offset(0x10),   //  PLT_CLK_CTL_4
+    CKC4,  2,
+    CKF4, 1,
+    ,     29,
+    Offset(0x14),   //  PLT_CLK_CTL_5
+    CKC5,  2,
+    CKF5, 1,
+    ,     29,
+  }
+} //end Scope(\)
+
+scope (\_SB)
+{
+  Device(LPEA)
+  {
+    Name (_ADR, 0)
+    Name (_HID, "80860F28")
+    Name (_CID, "80860F28")
+    //Name (_CLS, Package (3) {0x04, 0x01, 0x00})
+    Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")
+    Name (_SUB, "80867270")
+    Name (_UID, 1)
+    Name (_DEP, Package() {\_SB.I2C2.RTEK})
+    Name(_PR0,Package() {PLPE})
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))
+      {
+        Return (0xF)
+      }
+      Return (0x0)
+    }
+
+    Method (_DIS, 0x0, NotSerialized)
+    {
+      //Add a dummy disable function
+    }
+
+    Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0)  // MMIO 1 - LPE MMIO
+        Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1)  // MMIO 2 - Shadowed PCI Config Space
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2)  // LPE Memory Bar Allocate during post
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
+        GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} //  Audio jack interrupt
+      }
+    )
+
+    Method (_CRS, 0x0, NotSerialized)
+    {
+      CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)
+      Store(LPE0, B0BA)
+      CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
+      Store(LPE1, B1BA)
+      CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
+      Store(LPE2, B2BA)
+      Return (RBUF)
+    }
+
+    OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
+    Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+    {
+      Offset (0x84),
+      PSAT,   32
+    }
+
+    PowerResource(PLPE, 0, 0)   // Power Resource for LPEA
+    {
+      Method (_STA)
+      {
+        Return (1)      // Power Resource is always available.
+      }
+
+      Method (_ON)
+      {
+        And(PSAT, 0xfffffffC, PSAT)
+        OR(PSAT, 0X00000000, PSAT)
+      }
+
+      Method (_OFF)
+      {
+        OR(PSAT, 0x00000003, PSAT)
+        OR(PSAT, 0X00000000, PSAT)
+      }
+    } // End PLPE
+  } // End "Low Power Engine Audio"
+
+  Device(LPA2)
+  {
+    Name (_ADR, 0)
+    Name (_HID, "LPE0F28")  // _HID: Hardware ID
+    Name (_CID, "LPE0F28")  // _CID: Compatible ID
+    Name (_DDN, "Intel(R) SST Audio - LPE0F28")  // _DDN: DOS Device Name
+    Name (_SUB, "80867270")
+    Name (_UID, 1)
+    Name (_DEP, Package() {\_SB.I2C2.RTEK})
+    Name(_PR0,Package() {PLPE})
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))
+      {
+        Return (0xF)
+      }
+      Return (0x0)
+    }
+
+    Method (_DIS, 0x0, NotSerialized)
+    {
+      //Add a dummy disable function
+    }
+
+    Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2)  // LPE Memory Bar Allocate during post
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
+        Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1)  // MMIO 2 - Shadowed PCI Config Space
+      }
+    )
+
+    Method (_CRS, 0x0, NotSerialized)
+    {
+      CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
+      Add(LPE0, 0x140000, SHBA)
+      CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)
+      Add(LPE0, 0x144000, MBBA)
+      CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)
+      Add(LPE0, 0xC0000, IRBA)
+      CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)
+      Add(LPE0, 0x100000, DRBA)
+      CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
+      Store(LPE1, B1BA)
+      CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
+      Store(LPE2, B2BA)
+      Return (RBUF)
+    }
+
+    OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
+    Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+    {
+      Offset (0x84),
+      PSAT,   32
+    }
+
+    PowerResource(PLPE, 0, 0)   // Power Resource for LPEA
+    {
+      Method (_STA)
+      {
+        Return (1)      // Power Resource is always available.
+      }
+
+      Method (_ON)
+      {
+        And(PSAT, 0xfffffffC, PSAT)
+        OR(PSAT, 0X00000000, PSAT)
+      }
+
+      Method (_OFF)
+      {
+        OR(PSAT, 0x00000003, PSAT)
+        OR(PSAT, 0X00000000, PSAT)
+      }
+    } // End PLPE
+
+    Device (ADMA)
+    {
+      Name (_ADR, Zero)  // _ADR: Address
+      Name (_HID, "DMA0F28")  // _HID: Hardware ID
+      Name (_CID, "DMA0F28")  // _CID: Compatible ID
+      Name (_DDN, "Intel(R) Audio  DMA0 - DMA0F28")  // _DDN: DOS Device Name
+      Name (_UID, One)  // _UID: Unique ID
+      Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0)  // LPE BASE + LPE DMA0 offset
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM)  // LPE BASE + LPE SHIM offset
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
+      })
+
+      Method (_CRS, 0, NotSerialized)   // _CRS: Current Resource Settings
+      {
+        CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)
+        Add(LPE0, 0x98000, D0BA)
+        CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
+        Add(LPE0, 0x140000, SHBA)
+        Return (RBUF)
+      }
+    }
+  } // End "Low Power Engine Audio" for Android
+}
+
+scope (\_SB.PCI0)
+{
+
+  //
+  // Serial ATA Host Controller - Device 19, Function 0
+  //
+
+  Device(SATA)
+  {
+    Name(_ADR,0x00130000)
+    //
+    // SATA Methods pulled in via SSDT.
+    //
+
+    OperationRegion(SATR, PCI_Config, 0x74,0x4)
+    Field(SATR,WordAcc,NoLock,Preserve)
+    {
+      Offset(0x00), // 0x74, PMCR
+      ,   8,
+      PMEE,   1,    //PME_EN
+      ,   6,
+      PMES,   1     //PME_STS
+    }
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return(0xf)
+    }
+
+    Method(_DSW, 3)
+    {
+    } // End _DSW
+  }
+
+  //
+  // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment
+  //
+  Device(EM41)
+  {
+    Name(_ADR,0x00100000)
+    OperationRegion(SDIO, PCI_Config, 0x84,0x4)
+    Field(SDIO,WordAcc,NoLock,Preserve)
+    {
+      Offset(0x00), // 0x84, PMCR
+      ,   8,
+      PMEE,   1,    //PME_EN
+      ,   6,
+      PMES,   1     //PME_STS
+    }
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))
+      {
+        Return(0xF)
+      }
+      Else
+      {
+        Return(0x0)
+      }
+    }
+
+    Method(_DSW, 3)
+    {
+    } // End _DSW
+
+    Device (CARD)
+    {
+      Name (_ADR, 0x00000008)
+      Method(_RMV, 0x0, NotSerialized)
+      {
+        Return (0)
+      } // End _DSW
+    }
+  }
+
+  //
+  // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment
+  //
+  Device(EM45)
+  {
+    Name(_ADR,0x00170000)
+    OperationRegion(SDIO, PCI_Config, 0x84,0x4)
+    Field(SDIO,WordAcc,NoLock,Preserve)
+    {
+      Offset(0x00), // 0x84, PMCR
+      ,   8,
+      PMEE,   1,    //PME_EN
+      ,   6,
+      PMES,   1     //PME_STS
+    }
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))
+      {
+        Return(0xF)
+      }
+      Else
+      {
+        Return(0x0)
+      }
+    }
+
+    Method(_DSW, 3)
+    {
+    } // End _DSW
+
+    Device (CARD)
+    {
+      Name (_ADR, 0x00000008)
+      Method(_RMV, 0x0, NotSerialized)
+      {
+        Return (0)
+      } // End _DSW
+    }
+  }
+  //
+  // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment
+  //
+  Device(SD12)
+  {
+    Name(_ADR,0x00120000)
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      //
+      // PCIM>> 0:ACPI mode           1:PCI mode
+      //
+      If (LEqual(PCIM, 0)) {
+        Return (0x0)
+      }
+
+      //
+      // If device is disabled.
+      //
+      If (LEqual(SD3D, 1))
+      {
+        Return (0x0)
+      }
+
+      Return (0xF)
+    }
+
+    Device (CARD)
+    {
+      Name (_ADR, 0x00000008)
+      Method(_RMV, 0x0, NotSerialized)
+      {
+        // SDRM = 0 non-removable;
+        If (LEqual(SDRM, 0))
+        {
+          Return (0)
+        }
+
+        Return (1)
+      }
+    }
+  }
+
+  // xHCI Controller - Device 20, Function 0
+  include("PchXhci.asl")
+
+  //
+  // High Definition Audio Controller - Device 27, Function 0
+  //
+  Device(HDEF)
+  {
+    Name(_ADR, 0x001B0000)
+    include("PchAudio.asl")
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      If (LEqual(HDAD, 0))
+      {
+        Return(0xf)
+      }
+      Return(0x0)
+    }
+
+    Method(_DSW, 3)
+    {
+    } // End _DSW
+  } // end "High Definition Audio Controller"
+
+
+
+  //
+  // PCIE Root Port #1
+  //
+  Device(RP01)
+  {
+    Name(_ADR, 0x001C0000)
+    include("PchPcie.asl")
+    Name(_PRW, Package() {9, 4})
+
+    Method(_PRT,0)
+    {
+      If(PICM) { Return(AR04) }// APIC mode
+      Return (PR04) // PIC Mode
+    } // end _PRT
+  } // end "PCIE Root Port #1"
+
+  //
+  // PCIE Root Port #2
+  //
+  Device(RP02)
+  {
+    Name(_ADR, 0x001C0001)
+    include("PchPcie.asl")
+    Name(_PRW, Package() {9, 4})
+
+    Method(_PRT,0)
+    {
+      If(PICM) { Return(AR05) }// APIC mode
+      Return (PR05) // PIC Mode
+    } // end _PRT
+
+  } // end "PCIE Root Port #2"
+
+  //
+  // PCIE Root Port #3
+  //
+  Device(RP03)
+  {
+    Name(_ADR, 0x001C0002)
+    include("PchPcie.asl")
+    Name(_PRW, Package() {9, 4})
+    Method(_PRT,0)
+    {
+      If(PICM) { Return(AR06) }// APIC mode
+      Return (PR06) // PIC Mode
+    } // end _PRT
+
+  } // end "PCIE Root Port #3"
+
+  //
+  // PCIE Root Port #4
+  //
+  Device(RP04)
+  {
+    Name(_ADR, 0x001C0003)
+    include("PchPcie.asl")
+    Name(_PRW, Package() {9, 4})
+    Method(_PRT,0)
+    {
+      If(PICM) { Return(AR07) }// APIC mode
+      Return (PR07) // PIC Mode
+    } // end _PRT
+
+  } // end "PCIE Root Port #4"
+
+
+  Scope(\_SB)
+  {
+    //
+    // Dummy power resource for USB D3 cold support
+    //
+    PowerResource(USBC, 0, 0)
+    {
+      Method(_STA) { Return (0xF) }
+      Method(_ON) {}
+      Method(_OFF) {}
+    }
+  }
+  //
+  // EHCI Controller - Device 29, Function 0
+  //
+  Device(EHC1)
+  {
+    Name(_ADR, 0x001D0000)
+    Name(_DEP, Package(0x1)
+    {
+      PEPD
+    })
+    include("PchEhci.asl")
+    Name(_PRW, Package() {0x0D, 4})
+
+    OperationRegion(USBR, PCI_Config, 0x54,0x4)
+    Field(USBR,WordAcc,NoLock,Preserve)
+    {
+      Offset(0x00), // 0x54, PMCR
+      ,   8,
+      PMEE,   1,    //PME_EN
+      ,   6,
+      PMES,   1     //PME_STS
+    }
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      If(LEqual(XHCI, 0))      //XHCI is not present. It means EHCI is there
+      {
+        Return (0xF)
+      } Else
+      {
+        Return (0x0)
+      }
+    }
+
+    Method (_RMV, 0, NotSerialized)
+    {
+      Return (0x0)
+    }
+    //
+    // Create a dummy PR3 method to indicate to the PCI driver
+    // that the device is capable of D3 cold
+    //
+    Method(_PR3, 0x0, NotSerialized)
+    {
+      return (Package() {\_SB.USBC})
+    }
+
+  } // end "EHCI Controller"
+
+  //
+  // SMBus Controller - Device 31, Function 3
+  //
+  Device(SBUS)
+  {
+    Name(_ADR,0x001F0003)
+    Include("PchSmb.asl")
+  }
+
+  Device(SEC0)
+  {
+    Name (_ADR, 0x001a0000)                     // Device 0x1a, Function 0
+    Name(_DEP, Package(0x1)
+    {
+      PEPD
+    })
+
+
+    OperationRegion (PMEB, PCI_Config, 0x84, 0x04)  //PMECTRLSTATUS
+    Field (PMEB, WordAcc, NoLock, Preserve)
+    {
+      ,   8,
+      PMEE,   1,    //bit8 PMEENABLE
+      ,   6,
+      PMES,   1     //bit15 PMESTATUS
+    }
+
+    // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)
+    // Arg1 -- integer that contains target system state (0-4)
+    // Arg2 -- integer that contains the target device state
+    Method (_DSW, 3, NotSerialized)   // _DSW: Device Sleep Wake
+    {
+    }
+
+    Method (_CRS, 0, NotSerialized)
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)
+      })
+
+      If (LEqual(PAVP, 2))
+      {
+        Return (RBUF)
+      }
+      Return (ResourceTemplate() {})
+    }
+
+    Method (_STA)
+    {
+      If (LNotEqual(PAVP, 0))
+      {
+        Return (0xF)
+      }
+      Return (0x0)
+    }
+  }   // Device(SEC0)
+
+} // End scope (\_SB.PCI0)

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl

@@ -0,0 +1,42 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  2011  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+//
+// High Definition Audio - Device 27, Function 0
+//
+OperationRegion(HDAR, PCI_Config, 0x4C,0x10)
+Field(HDAR,WordAcc,NoLock,Preserve)
+{
+  Offset(0x00), // 0x4C, Dock Control Register
+  DCKA,    1,   // Dock Attach
+  ,    7,
+  Offset(0x01), // 04Dh, Dock Status Register
+  DCKM,    1,   // Dock Mated
+  ,    6,
+  DCKS,    1,   // Docking Supported
+  Offset(0x08), // 0x54, Power Management Control and Status Register
+  ,    8,
+  PMEE,    1,   // PME_EN
+  ,    6,
+  PMES,    1    // PME Status
+}
+
+
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl

@@ -0,0 +1,275 @@
+/***************************************************************************************;
+;*                                                                                     *;
+;*                                                                                     *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail                         *;
+;*    Family of Customer Reference Boards.                                             *;
+;*                                                                                     *;
+;*                                                                                     *;
+;*    Copyright (c)  2011  - 2014, Intel Corporation. All rights reserved              *;
+;*                                                                                     *;
+;*   This program and the accompanying materials are licensed and made available under *;
+;*   the terms and conditions of the BSD License that accompanies this distribution.   *;
+;*   The full text of the license may be found at                                      *;
+;*   http://opensource.org/licenses/bsd-license.php.                                   *;
+;*                                                                                     *;
+;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,             *;
+;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.     *;
+;*                                                                                     *;
+;*                                                                                     *;
+;*                                                                                     *;
+;***************************************************************************************/
+
+OperationRegion(PWKE,PCI_Config,0x62,0x04)
+
+Field(PWKE,DWordAcc,NoLock,Preserve)
+{
+  , 1,
+  PWUC, 8 // Port Wake Up Capability Mask
+}
+
+Method(_PSW,1)
+{
+  If(Arg0)
+  {
+    Store(Ones,PWUC)
+  }
+  Else
+  {
+    Store(0,PWUC)
+  }
+}
+
+// Leaves the USB ports on in S3/S4 to allow
+// the ability to Wake from USB.  Therefore, define
+// the below control methods to state D2 entry during
+// the given S-State.
+
+Method(_S3D,0)
+{
+  Return(2)
+}
+
+Method(_S4D,0)
+{
+  Return(2)
+}
+
+Device(HUBN)
+{
+  Name(_ADR, Zero)
+  Device(PR01)
+  {
+    Name(_ADR, One)
+
+    //
+    // There will have "Generic USB Hub" existed at Port 1 of each EHCI controller
+    // in Windows "Device Manager" while RMH is enabled, so need to add _UPC
+    // and _PLD to report OS that it's not user visible to pass WHQL: Single Computer
+    // Display Object test in Win7
+    //
+    Name(_UPC, Package()
+    {
+      0xFF,                       // Port is connectable
+      0x00,                       // Connector type - Type "A"
+      0x00000000,                 // Reserved 0 - must be zero
+      0x00000000
+    })                // Reserved 1 - must be zero
+
+    Name(_PLD, Package()
+    {
+      Buffer (0x10)
+      {
+        0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+        0x00, 0x00, 0x00, 0x00,
+        0x30, 0x1C, 0x00, 0x00,     // Panel Unknown, Shape Unknown
+        0x00, 0x00, 0x00, 0x00
+      }
+    })
+
+    Device(PR11)
+    {
+      Name(_ADR, One)
+      Name(_UPC, Package()
+      {
+        0xFF,                       // Port is connectable
+        0xFF,                       // Proprietary connector
+        0x00000000,                 // Reserved 0 - must be zero
+        0x00000000
+      })                // Reserved 1 - must be zero
+      Name(_PLD, Package()
+      {
+        Buffer (0x10)
+        {
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+          0x00, 0x00, 0x00, 0x00,
+          0xE1, 0x1C, 0x00, 0x00,     // Front Panel, Vertical Upper, Horz. Left, Shape Unknown
+          0x00, 0x00, 0x00, 0x00
+        }
+      })
+    }
+
+    Device(PR12)
+    {
+      Name(_ADR, 0x02)
+      Name(_UPC, Package()
+      {
+        0xFF,                       // Port is connectable
+        0xFF,                       // Proprietary connector
+        0x00000000,                 // Reserved 0 - must be zero
+        0x00000000
+      })                // Reserved 1 - must be zero
+      Name(_PLD, Package()
+      {
+        Buffer (0x10)
+        {
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+          0x00, 0x00, 0x00, 0x00,
+          0xE1, 0x1D, 0x00, 0x00,     // Front Panel, Vertical Center, Horz. Left, Shape Unknown
+          0x00, 0x00, 0x00, 0x00
+        }
+      })
+    }
+
+    Device(PR13)
+    {
+      Name(_ADR, 0x03)
+      Name(_UPC, Package()
+      {
+        0xFF,                       // Port is connectable
+        0xFF,                       // Proprietary connector
+        0x00000000,                 // Reserved 0 - must be zero
+        0x00000000
+      })                // Reserved 1 - must be zero
+      Name(_PLD, Package()
+      {
+        Buffer (0x10)
+        {
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+          0x00, 0x00, 0x00, 0x00,
+          0xE1, 0x1D, 0x00, 0x00,     // Front Panel, Vertical Center, Horz. Left, Shape Unknown
+          0x00, 0x00, 0x00, 0x00
+        }
+      })
+    }
+
+    Device(PR14)
+    {
+      Name(_ADR, 0x04)
+      Name(_UPC, Package()
+      {
+        0xFF,                       // Port is connectable
+        0xFF,                       // Proprietary connector
+        0x00000000,                 // Reserved 0 - must be zero
+        0x00000000
+      })                // Reserved 1 - must be zero
+
+      Name(_PLD, Package()
+      {
+        Buffer (0x10)
+        {
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+          0x00, 0x00, 0x00, 0x00,
+          0xE1, 0x1E, 0x00, 0x00,     // Front Panel, Vertical Lower, Horz. Left, Shape Unknown
+          0x00, 0x00, 0x00, 0x00
+        }
+      })
+
+      // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method
+      Include("UsbSbd.asl")
+    }
+
+    Device(PR15)
+    {
+      Name(_ADR, 0x05)
+      Name(_UPC, Package()
+      {
+        0xFF,                       // Port is connectable
+        0xFF,                       // Proprietary connector
+        0x00000000,                 // Reserved 0 - must be zero
+        0x00000000
+      })                // Reserved 1 - must be zero
+      Name(_PLD, Package()
+      {
+        Buffer (0x10)
+        {
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+          0x00, 0x00, 0x00, 0x00,
+          0xB1, 0x1E, 0x00, 0x00,     // Panel Unknown, Shape Unknown
+          0x00, 0x00, 0x00, 0x00
+        }
+      })
+      // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method
+      Include("UsbSbd.asl")
+    }
+
+    Device(PR16)
+    {
+      Name(_ADR, 0x06)
+      Name(_UPC, Package()
+      {
+        0xFF,                       // Port is connectable
+        0xFF,                       // Proprietary connector
+        0x00000000,                 // Reserved 0 - must be zero
+        0x00000000
+      })                // Reserved 1 - must be zero
+      Name(_PLD, Package()
+      {
+        Buffer (0x10)
+        {
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+          0x00, 0x00, 0x00, 0x00,
+          0xB1, 0x1E, 0x00, 0x00,     // Panel Unknown, Shape Unknown
+          0x00, 0x00, 0x00, 0x00
+        }
+      })
+      // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method
+      Include("UsbSbd.asl")
+    }
+
+    Device(PR17)
+    {
+      Name(_ADR, 0x07)
+      Name(_UPC, Package()
+      {
+        0xFF,                       // Port is connectable
+        0xFF,                       // Proprietary connector
+        0x00000000,                 // Reserved 0 - must be zero
+        0x00000000
+      })                // Reserved 1 - must be zero
+      Name(_PLD, Package()
+      {
+        Buffer (0x10)
+        {
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+          0x00, 0x00, 0x00, 0x00,
+          0xB1, 0x1E, 0x00, 0x00,     // Panel Unknown, Shape Unknown
+          0x00, 0x00, 0x00, 0x00
+        }
+      })
+      // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method
+      Include("UsbSbd.asl")
+    }
+
+    Device(PR18)
+    {
+      Name(_ADR, 0x08)
+      Name(_UPC, Package()
+      {
+        0xFF,                       // Port is connectable
+        0xFF,                       // Proprietary connector
+        0x00000000,                 // Reserved 0 - must be zero
+        0x00000000
+      })                // Reserved 1 - must be zero
+      Name(_PLD, Package()
+      {
+        Buffer (0x10)
+        {
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color
+          0x00, 0x00, 0x00, 0x00,
+          0xB1, 0x1E, 0x00, 0x00,     // Panel Unknown, Shape Unknown
+          0x00, 0x00, 0x00, 0x00
+        }
+      })
+    }
+  } // End of PR01
+} // End of HUBN

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl

@@ -0,0 +1,56 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  2011  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+OperationRegion(PXCS,PCI_Config,0x40,0xC0)
+Field(PXCS,AnyAcc, NoLock, Preserve)
+{
+  Offset(0x10), // LCTL - Link Control Register
+  L0SE, 1,      // 0, L0s Entry Enabled
+  , 7,
+  Offset(0x12), // LSTS - Link Status Register
+  , 13,
+  LASX, 1,      // 0, Link Active Status
+  Offset(0x1A), // SLSTS[7:0] - Slot Status Register
+  ABPX, 1,      // 0, Attention Button Pressed
+  , 2,
+  PDCX, 1,      // 3, Presence Detect Changed
+  , 2,
+  PDSX, 1,      // 6, Presence Detect State
+  , 1,
+  Offset(0x20), // RSTS - Root Status Register
+  , 16,
+  PSPX, 1,      // 16,        PME Status
+}
+
+
+Device(PXSX)
+{
+  Name(_ADR, 0x00000000)
+
+  // NOTE:  Any PCIE Hot-Plug dependency for this port is
+  // specific to the CRB.  Please modify the code based on
+  // your platform requirements.
+
+  Name(_PRW, Package() {9,4})
+}
+
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl

@@ -0,0 +1,616 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+Device (PEPD)
+{
+  Name (_HID, "INT3396")
+  Name(_CID, 0x800dd041)
+  Name (_UID, 0x1)
+
+  // Indicates if the platform PEP has loaded
+  Name(PEPP, Zero)
+
+  // Devices score-boarded by the PEP, Rev0 format
+  Name (DEVS, Package() {0})
+
+  // Devices score-boarded by the PEP, Rev1 format
+  Name(DEVX, Package()
+  {
+    Package () {"\\_SB.PCI0.XHC1", 0x1},
+    Package () {"\\_SB.PCI0.EHC1", 0x1},
+    Package () {"\\_SB.PCI0.GFX0", 0x1},
+    Package () {"\\_SB.PCI0.GFX0.ISP0", 0x1},
+    Package () {"\\_SB.PCI0.SEC0", 0x1},
+    Package () {"\\_SB.I2C1", 0x1},
+    Package () {"\\_SB.I2C2", 0x1},
+    Package () {"\\_SB.I2C3", 0x1},
+    Package () {"\\_SB.I2C4", 0x1},
+    Package () {"\\_SB.I2C5", 0x1},
+    Package () {"\\_SB.I2C6", 0x1},
+    Package () {"\\_SB.I2C7", 0x1},
+    Package () {"\\_SB.SDHA", 0x1},
+    Package () {"\\_SB.SDHB", 0x1},
+    Package () {"\\_SB.SDHC", 0x1},
+    Package () {"\\_SB.SPI1", 0x1},
+    Package () {"\\_SB.URT1", 0x1},
+    Package () {"\\_SB.URT2", 0x1},
+  })
+  // Crashdump device package
+  Name(CDMP, Package(2) {})
+  // Device dependency for uPEP
+  Name(DEVY, Package()
+  {
+    Package() {"\\_PR.CPU0", 0x1, Package() {Package() {0xFF, 0}}},
+    Package() {"\\_PR.CPU1", 0x1, Package() {Package() {0xFF, 0}}},
+    Package() {"\\_PR.CPU2", 0x1, Package() {Package() {0xFF, 0}}},
+    Package() {"\\_PR.CPU3", 0x1, Package() {Package() {0xFF, 0}}},
+    Package() {"\\_SB.I2C1", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.I2C2", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.I2C3", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.I2C4", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.I2C5", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.I2C6", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.I2C7", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.PCI0.GFX0", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.PCI0.SEC0", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.PCI0.XHC1", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.PCI0.GFX0.ISP0", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.LPEA", 0x1, Package() {Package() {0x0,3}, Package() {0x1,0}, Package() {0x2,3}, Package() {0x3,3}}},
+    Package() {"\\_SB.SDHA", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.SDHB", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.SDHC", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.SPI1", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.URT1", 0x1, Package() {Package() {0xFF,3}}},
+    Package() {"\\_SB.URT2", 0x1, Package() {Package() {0xFF,3}}}
+  })
+  // BCCD crashdump information
+  Name(BCCD, Package()
+  {
+    Package()
+    {
+      "\\_SB.SDHA",
+      Package()
+      {
+        Package() { Package() {0, 32, 0,  3, 0xFFFFFFFFFFFFFFFF}, Package() {0xFFFFFFFC, 0x0, 0x4}, 0}
+      }
+    }
+  })
+
+  Method(_STA, 0x0, NotSerialized)
+  {
+    Return(0xf)
+  }
+
+  Method(_DSM, 0x4, Serialized)
+  {
+    If(LEqual(Arg0,ToUUID("B8FEBFE0-BAF8-454b-AECD-49FB91137B21")))
+    {
+
+      // Number of fn IDs supported
+      If(LEqual(Arg2, Zero))
+      {
+        Return(Buffer(One)
+        {
+          0xf
+        })
+      }
+
+      // Pep presence
+      If(LEqual(Arg2, One))
+      {
+        Store(0x1, PEPP)
+        Return(0xf)
+      }
+
+      // Mitigation devices
+      If(LEqual(Arg2, 0x2))
+      {
+        If(LEqual(Arg1, 0x0))
+        {
+          // Rev0
+          Return(DEVS)
+        }
+        If(LEqual(Arg1, 0x1))
+        {
+          // Rev1
+          Return(DEVX)
+        }
+      }
+
+      // Crashdump device data
+      If(LEqual(Arg2, 0x3))
+      {
+        Store("\\_SB.SDHA", Index(CDMP,0))
+        Store(EM1A, Index(CDMP,1))
+        Return(CDMP)
+      }
+    }
+    // New UUID for built-in uPEP
+    If(LEqual(Arg0,ToUUID("C4EB40A0-6CD2-11E2-BCFD-0800200C9A66")))
+    {
+
+      // Number of fn IDs supported
+      If(LEqual(Arg2, Zero))
+      {
+        Return(Buffer(One)
+        {
+          0x7
+        })
+      }
+      // LPI device dependencies
+      If(LEqual(Arg2, 0x1))
+      {
+        Return(DEVY)
+      }
+      // Crashdump device data
+      If(LEqual(Arg2, 0x2))
+      {
+        Store(EM1A, Local0)
+        Add(Local0, 0x84, Local0)
+        Store(Local0, Index(DerefOf(Index(DerefOf(Index(DerefOf(Index(DerefOf(Index(BCCD, Zero, )), One, )), Zero, )), Zero, )), 0x4, ))
+        Return(BCCD)
+      }
+    }
+
+    Return(One)
+  }
+}
+
+//
+// eMMC 4.41
+//
+Device(SDHA)
+{
+  Name (_ADR, 0)
+  Name (_HID, "80860F14")
+  Name (_CID, "PNP0D40")
+  Name (_DDN, "Intel(R) eMMC Controller - 80860F14")
+  Name (_UID, 1)
+  Name(_DEP, Package(0x1)
+  {
+    PEPD
+  })
+
+  Name (RBF1, ResourceTemplate ()
+  {
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {45}  // eMMC 4.41 IRQ
+  })
+
+  Method (_CRS, 0x0, NotSerialized)
+  {
+    // Update the Base address for BAR0 of eMMC 4.41
+    CreateDwordField(^RBF1, ^BAR0._BAS, B0B1)
+    CreateDwordField(^RBF1, ^BAR0._LEN, B0L1)
+    Store(eM0A, B0B1)
+    Store(eM0L, B0L1)
+    Return (RBF1)
+  }
+  Method (_STA, 0x0, NotSerialized)
+  {
+    //
+    // PCIM>> 0:ACPI mode            1:PCI mode
+    // SD1D>> 0:eMMC 4.41 enable     1:eMMC 4.41 disable
+    //
+    If (LAnd(LEqual(PCIM, 0), LEqual(SD1D, 0)))
+    {
+      Return (0xF)
+    }
+    Else
+    {
+      Return (0x0)
+    }
+  }
+
+
+  Method (_PS3, 0, NotSerialized)
+  {
+    OR(PSAT, 0x00000003, PSAT)
+    OR(PSAT, 0X00000000, PSAT)
+    //
+    // If not B1, still keep 2 ms w/a
+    //
+    If(LLess(SOCS, 0x03))
+    {
+      Sleep(2)
+    }
+  }
+  Method (_PS0, 0, NotSerialized)
+  {
+    And(PSAT, 0xfffffffC, PSAT)
+    OR(PSAT, 0X00000000, PSAT)
+    //
+    // If not B1, still keep 2 ms w/a
+    //
+    If(LLess(SOCS, 0x03))
+    {
+      Sleep(2)
+    }
+  }
+
+  OperationRegion (KEYS, SystemMemory, eM1A, 0x100)
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+  {
+    Offset (0x84),
+           PSAT,  32
+  }
+
+         Method (_DIS, 0x0, NotSerialized)
+  {
+    //Adding dummy disable methods for device EMM0
+  }
+
+  Device (EMMD)
+  {
+    Name (_ADR, 0x00000008) // Slot 0, Function 8
+    Method (_RMV, 0, NotSerialized)
+    {
+      Return (0x0)
+    }
+  }
+}
+
+
+//
+// eMMC 4.5
+//
+Device(SDHD)
+{
+  Name (_ADR, 0)
+  Name (_HID, "80860F14")
+  Name (_CID, "PNP0D40")
+  Name (_DDN, "Intel(R) eMMC Controller - 80860F14")
+  Name (_UID, 1)
+  Name(_DEP, Package(0x1)
+  {
+    PEPD
+  })
+
+  Name (RBF1, ResourceTemplate ()
+  {
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {44}  // eMMC 4.5 IRQ
+  })
+  Method (_CRS, 0x0, NotSerialized)
+  {
+    CreateDwordField(^RBF1, ^BAR0._BAS, B0B1)
+    CreateDwordField(^RBF1, ^BAR0._LEN, B0L1)
+    Store(eM0A, B0B1)
+    Store(eM0L, B0L1)
+    Return (RBF1)
+  }
+  Method (_STA, 0x0, NotSerialized)
+  {
+    //
+    // PCIM>> 0:ACPI mode           1:PCI mode
+    // HSID>> 0:eMMC 4.5 enable     1:eMMC 4.5 disable
+    //
+    If (LAnd(LEqual(PCIM, 0), LEqual(HSID, 0)))
+    {
+      Return (0xF)
+    }
+    Else
+    {
+      Return (0x0)
+    }
+  }
+
+
+  Method (_PS3, 0, NotSerialized)
+  {
+    OR(PSAT, 0x00000003, PSAT)
+    OR(PSAT, 0X00000000, PSAT)
+    //
+    // If not B1, still keep 2 ms w/a
+    //
+    If(LLess(SOCS, 0x03))
+    {
+      Sleep(2)
+    }
+  }
+  Method (_PS0, 0, NotSerialized)
+  {
+    And(PSAT, 0xfffffffC, PSAT)
+    OR(PSAT, 0X00000000, PSAT)
+    //
+    // If not B1, still keep 2 ms w/a
+    //
+    If(LLess(SOCS, 0x03))
+    {
+      Sleep(2)
+    }
+  }
+
+  OperationRegion (KEYS, SystemMemory, eM1A, 0x100)
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+  {
+    Offset (0x84),
+           PSAT,  32
+  }
+
+         Method (_DIS, 0x0, NotSerialized)
+  {
+    //Adding dummy disable methods for device EMM0
+  }
+
+  Device (EM45)
+  {
+    Name (_ADR, 0x00000008) // Slot 0, Function 8
+    Method (_RMV, 0, NotSerialized)
+    {
+      Return (0x0)
+    }
+  }
+}
+
+
+//
+// SDIO
+//
+Device(SDHB)
+{
+  Name (_ADR, 0)
+  Name (_HID, "INT33BB")
+  Name (_CID, "PNP0D40")
+  Name (_DDN, "Intel(R) SDIO Controller - 80860F15")
+  Name (_UID, 2)
+  Name (_HRV, 2)
+  Name(_DEP, Package(0x01)
+  {
+    PEPD
+  })
+  Name (PSTS, 0x0)
+
+  Name (RBUF, ResourceTemplate ()
+  {
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {46}  // SDIO IRQ
+  })
+
+  Method (_CRS, 0x0, NotSerialized)
+  {
+
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)
+    Store(SI0A, B0BA)
+    Store(SI0L, B0LN)
+    Return (RBUF)
+  }
+  Method (_STA, 0x0, NotSerialized)
+  {
+    If (LLessEqual(STEP, 0x04))
+    {
+      //A stepping
+      Store(SDMD, _HRV)
+    }
+
+    //
+    // PCIM>> 0:ACPI mode           1:PCI mode
+    //
+    If (LEqual(PCIM, 1)) {
+      Return (0x0)
+    }
+
+    If (LOr(LEqual(SI0A, 0), LEqual(SD2D, 1)))
+    {
+      Return (0x0)
+    }
+    Return (0xF)
+  }
+  Method (_DIS, 0x0, NotSerialized)
+  {
+    //Adding dummy disable methods for device EMM0
+  }
+
+  Method (_PS3, 0, NotSerialized)
+  {
+    OR(PSAT, 0x00000003, PSAT)
+    OR(PSAT, 0X00000000, PSAT)
+  }
+  Method (_PS0, 0, NotSerialized)
+  {
+    And(PSAT, 0xfffffffC, PSAT)
+    OR(PSAT, 0X00000000, PSAT)
+
+    if(LEqual(\_SB.SDHB.PSTS,0x0))
+    {
+      if(LEqual (\_SB.GPO2.AVBL, 1))
+      {
+        Store( 0x01, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 1 put the device to normal state
+        Store( 0x01, \_SB.SDHB.PSTS)  // indicates that the device powered ON
+      }
+    }
+
+
+  }
+  OperationRegion (KEYS, SystemMemory, SI1A, 0x100)
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+  {
+    Offset (0x84),
+           PSAT,   32
+  }
+
+
+         Device (BRCM)
+  {
+    Name (_ADR, 0x01)                 //SlotNumber + Function
+    Name (_DEP, Package() {\_SB.GPO2})
+
+    Method (_RMV, 0, NotSerialized)
+    {
+      Return (0x0)
+    }
+    Name (_PRW, Package() {0, 0})
+    Name (_S4W, 2)
+
+    Method (_CRS, 0, Serialized)
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {73}
+      })
+      Return (RBUF)
+    }
+
+    Method (_PS3, 0, NotSerialized)
+    {
+      if(LEqual (\_SB.GPO2.AVBL, 1))
+      {
+        Store( 0x00, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 0 puts the device in reset state
+        Store( 0x00, \_SB.SDHB.PSTS) //Indicates that the device is powered off
+      }
+
+    }
+    Method (_PS0, 0, NotSerialized)
+    {
+      if(LEqual(\_SB.SDHB.PSTS,0x0))
+      {
+        if(LEqual (\_SB.GPO2.AVBL, 1))
+        {
+          Store( 0x01, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 1 put the device to normal state
+          Store( 0x01, \_SB.SDHB.PSTS)     // indicates that the device powered ON
+        }
+      }
+    }
+  } // Device (BRCM)
+  //
+  // Secondary Broadcom WIFI function
+  //
+  Device(BRC2)
+  {
+    Name(_ADR, 0x2) // function 2
+    Name(_STA, 0xf)
+    //
+    // The device is not removable. This must be a method.
+    //
+    Method(_RMV, 0x0, NotSerialized)
+    {
+      Return(0x0)
+    }
+
+    //
+    // Describe a vendor-defined connection between this device and the
+    // primary wifi device
+    //
+
+    Method(_CRS)
+    {
+      Name(NAM, Buffer() {"\\_SB.SDHB.BRCM"})
+      Name(SPB, Buffer()
+      {
+        0x8E,       // SPB Descriptor
+        0x18, 0x00, // Length including NAM above
+        0x01,       // +0x00 SPB Descriptor Revision
+        0x00,       // +0x01 Resource Source Index
+        0xc0,       // +0x02 Bus type - vendor defined
+        0x02,       // +0x03 Consumer + controller initiated
+        0x00, 0x00, // +0x04 Type specific flags
+        0x01,       // +0x06 Type specific revision
+        0x00, 0x00  // +0x07 type specific data length
+        // +0x09 - 0xf bytes for NULL-terminated NAM
+        // Length = 0x18
+      })
+
+      Name(END, Buffer() {0x79, 0x00})
+      Concatenate(SPB, NAM, Local0)
+      Concatenate(Local0, END, Local1)
+      Return(Local1)
+    }
+  }
+
+}
+
+//
+// SD Card
+//
+Device(SDHC)
+{
+  Name (_ADR, 0)
+  Name (_HID, "80860F16")
+  Name (_CID, "PNP0D40")
+  Name (_DDN, "Intel(R) SD Card Controller - 80860F16")
+  Name (_UID, 3)
+  Name(_DEP, Package(0x01)
+  {
+    PEPD
+  })
+  Name (RBUF, ResourceTemplate ()
+  {
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {47}  // SD Card IRQ
+  })
+  Method (_CRS, 0x0, NotSerialized)
+  {
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)
+    Store(SD0A, B0BA)
+    Store(SD0L, B0LN)
+    Return (RBUF)
+  }
+  Method (_STA, 0x0, NotSerialized)
+  {
+    //
+    // PCIM>> 0:ACPI mode           1:PCI mode
+    //
+    If (LEqual(PCIM, 1)) {
+      Return (0x0)
+    }
+
+    If (LOr(LEqual(SD0A, 0), LEqual(SD3D, 1)))
+    {
+      Return (0x0)
+    }
+    Return (0xF)
+  }
+
+  Method (_PS3, 0, NotSerialized)
+  {
+    OR(PSAT, 0x00000003, PSAT)
+    OR(PSAT, 0X00000000, PSAT)
+  }
+  Method (_PS0, 0, NotSerialized)
+  {
+    And(PSAT, 0xfffffffC, PSAT)
+    OR(PSAT, 0X00000000, PSAT)
+  }
+  OperationRegion (KEYS, SystemMemory, SD1A, 0x100)
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+  {
+    Offset (0x84),
+           PSAT,   32
+  }
+
+  Device (CARD)
+  {
+    Name (_ADR, 0x00000008)
+    Method(_RMV, 0x0, NotSerialized)
+    {
+      // SDRM = 0 non-removable;
+      If (LEqual(SDRM, 0))
+      {
+        Return (0)
+      }
+
+      Return (1)
+    }
+  }
+
+}
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl

@@ -0,0 +1,839 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+// Define various SMBus PCI Configuration Space Registers.
+
+OperationRegion(SMBP,PCI_Config,0x40,0xC0)
+Field(SMBP,DWordAcc,NoLock,Preserve)
+{
+  ,     2,
+  I2CE, 1
+}
+
+// SMBus Send Byte - This function will write a single byte of
+// data to a specific Slave Device per SMBus Send Byte Protocol.
+//      Arg0 = Address
+//      Arg1 = Data
+//      Return: Success = 1
+//              Failure = 0
+
+      Method(SSXB,2,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+    Offset(0x02),
+    HCON, 8,        // 2 - Host Control
+    HCOM, 8,        // 3 - Host Command
+    TXSA, 8,        // 4 - Transmit Slave Address
+    DAT0, 8,        // 5 - Host Data 0
+    DAT1, 8,        // 6 - Host Data 1
+    HBDR, 8,        // 7 - Host Block Data
+    PECR, 8,        // 8 - Packer Error Check
+    RXSA, 8,        // 9 - Receive Slave Address
+    SDAT, 16,       // A - Slave Data
+  }
+
+  // Step 1:  Confirm the ICHx SMBus is ready to perform
+  // communication.
+
+  If(STRT())
+  {
+    Return(0)
+  }
+
+  // Step 2:  Initiate a Send Byte.
+
+  Store(0,I2CE)                           // Ensure SMbus Mode.
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
+  Store(Arg0,TXSA)                        // Write Address in TXSA.
+  Store(Arg1,HCOM)                        // Data in HCOM.
+
+  // Set the SMBus Host control register to 0x48.
+  //   Bit 7:    =  0  = reserved
+  //   Bit 6:    =  1  = start
+  //   Bit 5:    =  0  = disregard, I2C related bit
+  //   Bits 4:2: = 001 = Byte Protocol
+  //   Bit 1:    =  0  = Normal Function
+  //   Bit 0:    =  0  = Disable interrupt generation
+
+  Store(0x48,HCON)
+
+  // Step 3:  Exit the Method correctly.
+
+  If(COMP)
+  {
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
+    Return(1)                       // Return Success.
+  }
+
+  Return(0)
+}
+
+// SMBus Receive Byte - This function will write a single byte
+// of data to a specific Slave Device per SMBus Receive Byte
+// Protocol.
+//      Arg0 = Address
+//      Return: Success = Byte-Size Value
+//              Failure = Word-Size Value = FFFFh.
+
+Method(SRXB,1,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+    Offset(0x02),
+    HCON, 8,        // 2 - Host Control
+    HCOM, 8,        // 3 - Host Command
+    TXSA, 8,        // 4 - Transmit Slave Address
+    DAT0, 8,        // 5 - Host Data 0
+    DAT1, 8,        // 6 - Host Data 1
+    HBDR, 8,        // 7 - Host Block Data
+    PECR, 8,        // 8 - Packer Error Check
+    RXSA, 8,        // 9 - Receive Slave Address
+    SDAT, 16,       // A - Slave Data
+  }
+  // Step 1:  Confirm the ICHx SMBus is ready to perform
+  // communication.
+
+  If(STRT())
+  {
+    Return(0xFFFF)
+  }
+
+  // Step 2:  Initiate a Receive Byte.
+
+  Store(0,I2CE)                           // Ensure SMbus Mode.
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
+  Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
+
+  // Set the SMBus Host control register to 0x48.
+  //   Bit 7:    =  0  = reserved
+  //   Bit 6:    =  1  = start
+  //   Bit 5:    =  0  = disregard, I2C related bit
+  //   Bits 4:2: = 001 = Byte Protocol
+  //   Bit 1:    =  0  = Normal Function
+  //   Bit 0:    =  0  = Disable interrupt generation
+
+  Store(0x44,HCON)
+
+  // Step 3:  Exit the Method correctly.
+
+  If(COMP)
+  {
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
+    Return(DAT0)                    // Return Success.
+  }
+
+  Return(0xFFFF)                          // Return Failure.
+}
+
+// SMBus Write Byte - This function will write a single byte
+// of data to a specific Slave Device per SMBus Write Byte
+// Protocol.
+//      Arg0 = Address
+//      Arg1 = Command
+//      Arg2 = Data
+//      Return: Success = 1
+//              Failure = 0
+
+Method(SWRB,3,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+    Offset(0x02),
+    HCON, 8,        // 2 - Host Control
+    HCOM, 8,        // 3 - Host Command
+    TXSA, 8,        // 4 - Transmit Slave Address
+    DAT0, 8,        // 5 - Host Data 0
+    DAT1, 8,        // 6 - Host Data 1
+    HBDR, 8,        // 7 - Host Block Data
+    PECR, 8,        // 8 - Packer Error Check
+    RXSA, 8,        // 9 - Receive Slave Address
+    SDAT, 16,       // A - Slave Data
+  }
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
+
+  If(STRT())
+  {
+    Return(0)
+  }
+
+  // Step 2:  Initiate a Write Byte.
+
+  Store(0,I2CE)                           // Ensure SMbus Mode.
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
+  Store(Arg0,TXSA)                        // Write Address in TXSA.
+  Store(Arg1,HCOM)                        // Command in HCOM.
+  Store(Arg2,DAT0)                        // Data in DAT0.
+
+  // Set the SMBus Host control register to 0x48.
+  //   Bit 7:    =  0  = reserved
+  //   Bit 6:    =  1  = start
+  //   Bit 5:    =  0  = disregard, I2C related bit
+  //   Bits 4:2: = 010 = Byte Data Protocol
+  //   Bit 1:    =  0  = Normal Function
+  //   Bit 0:    =  0  = Disable interrupt generation
+
+  Store(0x48,HCON)
+
+  // Step 3:  Exit the Method correctly.
+
+  If(COMP)
+  {
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
+    Return(1)                       // Return Success.
+  }
+
+  Return(0)                               // Return Failure.
+}
+
+// SMBus Read Byte - This function will read a single byte of data
+// from a specific slave device per SMBus Read Byte Protocol.
+//      Arg0 = Address
+//      Arg1 = Command
+//      Return: Success = Byte-Size Value
+//              Failure = Word-Size Value
+
+Method(SRDB,2,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+    Offset(0x02),
+    HCON, 8,        // 2 - Host Control
+    HCOM, 8,        // 3 - Host Command
+    TXSA, 8,        // 4 - Transmit Slave Address
+    DAT0, 8,        // 5 - Host Data 0
+    DAT1, 8,        // 6 - Host Data 1
+    HBDR, 8,        // 7 - Host Block Data
+    PECR, 8,        // 8 - Packer Error Check
+    RXSA, 8,        // 9 - Receive Slave Address
+    SDAT, 16,       // A - Slave Data
+  }
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
+
+  If(STRT())
+  {
+    Return(0xFFFF)
+  }
+
+  // Step 2:  Initiate a Read Byte.
+
+  Store(0,I2CE)                           // Ensure SMbus Mode.
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
+  Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
+  Store(Arg1,HCOM)                        // Command in HCOM.
+
+  // Set the SMBus Host control register to 0x48.
+  //   Bit 7:    =  0  = reserved
+  //   Bit 6:    =  1  = start
+  //   Bit 5:    =  0  = disregard, I2C related bit
+  //   Bits 4:2: = 010 = Byte Data Protocol
+  //   Bit 1:    =  0  = Normal Function
+  //   Bit 0:    =  0  = Disable interrupt generation
+
+  Store(0x48,HCON)
+
+  // Step 3:  Exit the Method correctly.
+
+  If(COMP)
+  {
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
+    Return(DAT0)                    // Return Success.
+  }
+
+  Return(0xFFFF)                          // Return Failure.
+}
+
+// SMBus Write Word - This function will write a single word
+// of data to a specific Slave Device per SMBus Write Word
+// Protocol.
+//      Arg0 = Address
+//      Arg1 = Command
+//      Arg2 = Data (16 bits in size)
+//      Return: Success = 1
+//              Failure = 0
+
+Method(SWRW,3,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+    Offset(0x02),
+	HCON, 8,        // 2 - Host Control
+	HCOM, 8,        // 3 - Host Command
+	TXSA, 8,        // 4 - Transmit Slave Address
+	DAT0, 8,        // 5 - Host Data 0
+	DAT1, 8,        // 6 - Host Data 1
+	HBDR, 8,        // 7 - Host Block Data
+	PECR, 8,        // 8 - Packer Error Check
+	RXSA, 8,        // 9 - Receive Slave Address
+	SDAT, 16,       // A - Slave Data
+  }
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
+
+  If(STRT())
+  {
+    Return(0)
+  }
+
+  // Step 2:  Initiate a Write Word.
+
+  Store(0,I2CE)                           // Ensure SMbus Mode.
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
+  Store(Arg0,TXSA)                        // Write Address in TXSA.
+  Store(Arg1,HCOM)                        // Command in HCOM.
+  And(Arg2,0xFF,DAT1)                     // Low byte Data in DAT1.
+  And(ShiftRight(Arg2,8),0xFF,DAT0)       // High byte Data in DAT0.
+
+  // Set the SMBus Host control register to 0x4C.
+  //   Bit 7:    =  0  = reserved
+  //   Bit 6:    =  1  = start
+  //   Bit 5:    =  0  = disregard, I2C related bit
+  //   Bits 4:2: = 011 = Word Data Protocol
+  //   Bit 1:    =  0  = Normal Function
+  //   Bit 0:    =  0  = Disable interrupt generation
+
+  Store(0x4C,HCON)
+
+  // Step 3:  Exit the Method correctly.
+
+  If(COMP())
+  {
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others.
+    Return(1)                       // Return Success.
+  }
+
+  Return(0)                               // Return Failure.
+}
+
+// SMBus Read Word - This function will read a single byte of data
+// from a specific slave device per SMBus Read Word Protocol.
+//      Arg0 = Address
+//      Arg1 = Command
+//      Return: Success = Word-Size Value
+//              Failure = Dword-Size Value
+
+Method(SRDW,2,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+	Offset(0x02),
+	HCON, 8,        // 2 - Host Control
+	HCOM, 8,        // 3 - Host Command
+	TXSA, 8,        // 4 - Transmit Slave Address
+	DAT0, 8,        // 5 - Host Data 0
+	DAT1, 8,        // 6 - Host Data 1
+	HBDR, 8,        // 7 - Host Block Data
+	PECR, 8,        // 8 - Packer Error Check
+	RXSA, 8,        // 9 - Receive Slave Address
+	SDAT, 16,       // A - Slave Data
+  }
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
+
+  If(STRT())
+  {
+    Return(0xFFFF)
+  }
+
+  // Step 2:  Initiate a Read Word.
+
+  Store(0,I2CE)                           // Ensure SMbus Mode.
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
+  Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
+  Store(Arg1,HCOM)                        // Command in HCOM.
+
+  // Set the SMBus Host control register to 0x4C.
+  //   Bit 7:    =  0  = reserved
+  //   Bit 6:    =  1  = start
+  //   Bit 5:    =  0  = disregard, I2C related bit
+  //   Bits 4:2: = 011 = Word Data Protocol
+  //   Bit 1:    =  0  = Normal Function
+  //   Bit 0:    =  0  = Disable interrupt generation
+
+  Store(0x4C,HCON)
+
+  // Step 3:  Exit the Method correctly.
+
+  If(COMP())
+  {
+    Or(HSTS,0xFF,HSTS)                      // Clear INUSE_STS and others.
+    Return(Or(ShiftLeft(DAT0,8),DAT1))      // Return Success.
+  }
+
+  Return(0xFFFFFFFF)                      // Return Failure.
+}
+
+// SMBus Block Write - This function will write an entire block of data
+// to a specific slave device per SMBus Block Write Protocol.
+//      Arg0 = Address
+//      Arg1 = Command
+//      Arg2 = Buffer of Data to Write
+//      Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write
+//      Return: Success = 1
+//              Failure = 0
+
+Method(SBLW,4,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+	Offset(0x02),
+	HCON, 8,        // 2 - Host Control
+	HCOM, 8,        // 3 - Host Command
+	TXSA, 8,        // 4 - Transmit Slave Address
+	DAT0, 8,        // 5 - Host Data 0
+	DAT1, 8,        // 6 - Host Data 1
+	HBDR, 8,        // 7 - Host Block Data
+	PECR, 8,        // 8 - Packer Error Check
+	RXSA, 8,        // 9 - Receive Slave Address
+	SDAT, 16,       // A - Slave Data
+  }
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
+
+  If(STRT())
+  {
+    Return(0)
+  }
+
+  // Step 2:  Initiate a Block Write.
+
+  Store(Arg3,I2CE)                        // Select the proper protocol.
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
+  Store(Arg0,TXSA)                        // Write Address in TXSA.
+  Store(Arg1,HCOM)                        // Command in HCOM.
+  Store(Sizeof(Arg2),DAT0)                // Count in DAT0.
+  Store(0,Local1)                         // Init Pointer to Buffer.
+  Store(DerefOf(Index(Arg2,0)),HBDR)      // First Byte in HBD Register.
+
+  // Set the SMBus Host control register to 0x48.
+  //   Bit 7:    =  0  = reserved
+  //   Bit 6:    =  1  = start
+  //   Bit 5:    =  0  = disregard, I2C related bit
+  //   Bits 4:2: = 101 = Block Protocol
+  //   Bit 1:    =  0  = Normal Function
+  //   Bit 0:    =  0  = Disable interrupt generation
+
+  Store(0x54,HCON)
+
+  // Step 3:  Send the entire Block of Data.
+
+  While(LGreater(Sizeof(Arg2),Local1))
+  {
+    // Wait up to 200ms for Host Status to get set.
+
+    Store(4000,Local0)              // 4000 * 50us = 200ms.
+
+    While(LAnd(LNot(And(HSTS,0x80)),Local0))
+    {
+      Decrement(Local0)       // Decrement Count.
+      Stall(50)               // Delay = 50us.
+    }
+
+    If(LNot(Local0))                // Timeout?
+    {
+      KILL()                  // Yes.  Kill Communication.
+      Return(0)               // Return failure.
+    }
+
+    Store(0x80,HSTS)                // Clear Host Status.
+    Increment(Local1)               // Point to Next Byte.
+
+    // Place next byte in HBDR if last byte has not been sent.
+
+    If(LGreater(Sizeof(Arg2),Local1))
+    {
+      Store(DerefOf(Index(Arg2,Local1)),HBDR)
+    }
+  }
+
+  // Step 4:  Exit the Method correctly.
+
+  If(COMP())
+  {
+    Or(HSTS,0xFF,HSTS)              // Clear all status bits.
+    Return(1)                       // Return Success.
+  }
+
+  Return(0)                               // Return Failure.
+}
+
+// SMBus Block Read - This function will read a block of data from
+// a specific slave device per SMBus Block Read Protocol.
+//      Arg0 = Address
+//      Arg1 = Command
+//      Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write
+//      Return: Success = Data Buffer (First Byte = length)
+//              Failure = 0
+
+Method(SBLR,3,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+	Offset(0x02),
+	HCON, 8,        // 2 - Host Control
+	HCOM, 8,        // 3 - Host Command
+	TXSA, 8,        // 4 - Transmit Slave Address
+	DAT0, 8,        // 5 - Host Data 0
+	DAT1, 8,        // 6 - Host Data 1
+	HBDR, 8,        // 7 - Host Block Data
+	PECR, 8,        // 8 - Packer Error Check
+	RXSA, 8,        // 9 - Receive Slave Address
+	SDAT, 16,       // A - Slave Data
+  }
+  Name(TBUF, Buffer(256) {})
+
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
+
+  If(STRT())
+  {
+    Return(0)
+  }
+
+  // Step 2:  Initiate a Block Read.
+
+  Store(Arg2,I2CE)                        // Select the proper protocol.
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
+  Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
+  Store(Arg1,HCOM)                        // Command in HCOM.
+
+  // Set the SMBus Host control register to 0x48.
+  //   Bit 7:    =  0  = reserved
+  //   Bit 6:    =  1  = start
+  //   Bit 5:    =  0  = disregard, I2C related bit
+  //   Bits 4:2: = 101 = Block Protocol
+  //   Bit 1:    =  0  = Normal Function
+  //   Bit 0:    =  0  = Disable interrupt generation
+
+  Store(0x54,HCON)
+
+  // Step 3:  Wait up to 200ms to get the Data Count.
+
+  Store(4000,Local0)                      // 4000 * 50us = 200ms.
+
+  While(LAnd(LNot(And(HSTS,0x80)),Local0))
+  {
+    Decrement(Local0)               // Decrement Count.
+    Stall(50)                       // Delay = 50us.
+  }
+
+  If(LNot(Local0))                        // Timeout?
+  {
+    KILL()                          // Yes.  Kill Communication.
+    Return(0)                       // Return failure.
+  }
+
+  Store(DAT0,Index(TBUF,0))               // Get the Data Count.
+  Store(0x80,HSTS)                        // Clear Host Status.
+  Store(1,Local1)                         // Local1 = Buffer Pointer.
+
+  // Step 4:  Get the Block Data and store it.
+
+  While(LLess(Local1,DerefOf(Index(TBUF,0))))
+  {
+    // Wait up to 200ms for Host Status to get set.
+
+    Store(4000,Local0)              // 4000 * 50us = 200ms.
+
+    While(LAnd(LNot(And(HSTS,0x80)),Local0))
+    {
+      Decrement(Local0)       // Decrement Count.
+      Stall(50)               // Delay = 50us.
+    }
+
+    If(LNot(Local0))                // Timeout?
+    {
+      KILL()                  // Yes.  Kill Communication.
+      Return(0)               // Return failure.
+    }
+
+    Store(HBDR,Index(TBUF,Local1))  // Place into Buffer.
+    Store(0x80,HSTS)                // Clear Host Status.
+    Increment(Local1)
+  }
+
+  // Step 5:  Exit the Method correctly.
+
+  If(COMP())
+  {
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others.
+    Return(TBUF)                    // Return Success.
+  }
+
+  Return(0)                               // Return Failure.
+}
+
+
+// SMBus Start Check
+//      Return: Success = 0
+//              Failure = 1
+
+Method(STRT,0,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+	Offset(0x02),
+	HCON, 8,        // 2 - Host Control
+	HCOM, 8,        // 3 - Host Command
+	TXSA, 8,        // 4 - Transmit Slave Address
+	DAT0, 8,        // 5 - Host Data 0
+	DAT1, 8,        // 6 - Host Data 1
+	HBDR, 8,        // 7 - Host Block Data
+	PECR, 8,        // 8 - Packer Error Check
+	RXSA, 8,        // 9 - Receive Slave Address
+	SDAT, 16,       // A - Slave Data
+  }
+  // Wait up to 200ms to confirm the SMBus Semaphore has been
+  // released (In Use Status = 0).  Note that the Sleep time may take
+  // longer as the This function will yield the Processor such that it
+  // may perform different tasks during the delay.
+
+  Store(200,Local0)                       // 200 * 1ms = 200ms.
+
+  While(Local0)
+  {
+    If(And(HSTS,0x40))              // In Use Set?
+    {
+      Decrement(Local0)       // Yes.  Decrement Count.
+      Sleep(1)                // Delay = 1ms.
+      If(LEqual(Local0,0))    // Count = 0?
+      {
+        Return(1)       // Return failure.
+      }
+    }
+    Else
+    {
+      Store(0,Local0)         // In Use Clear.  Continue.
+    }
+  }
+
+  // In Use Status = 0 during last read, which will make subsequent
+  // reads return In Use Status = 1 until software clears it.  All
+  // software using ICHx SMBus should check this bit before initiating
+  // any SMBus communication.
+
+  // Wait up to 200ms to confirm the Host Interface is
+  // not processing a command.
+
+  Store(4000,Local0)                      // 4000 * 50us = 200ms.
+
+  While(Local0)
+  {
+    If(And(HSTS,0x01))              // Host Busy Set?
+    {
+      Decrement(Local0)       // Decrement Count.
+      Stall(50)               // Delay = 50us.
+      If(LEqual(Local0,0))    // Count = 0?
+      {
+        KILL()          // Yes.  Kill Communication.
+      }
+    }
+    Else
+    {
+      Return(0)
+    }
+  }
+
+  Return(1)                               // Timeout.  Return failure.
+}
+
+// SMBus Completion Check
+//      Return: Success = 1
+//              Failure = 0
+
+Method(COMP,0,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+	Offset(0x02),
+	HCON, 8,        // 2 - Host Control
+	HCOM, 8,        // 3 - Host Command
+	TXSA, 8,        // 4 - Transmit Slave Address
+	DAT0, 8,        // 5 - Host Data 0
+	DAT1, 8,        // 6 - Host Data 1
+	HBDR, 8,        // 7 - Host Block Data
+	PECR, 8,        // 8 - Packer Error Check
+	RXSA, 8,        // 9 - Receive Slave Address
+	SDAT, 16,       // A - Slave Data
+  }
+  // Wait for up to 200ms for the Completion Command
+  // Status to get set.
+
+  Store(4000,Local0)                      // 4000 * 50us = 200ms.
+
+  While(Local0)
+  {
+    If(And(HSTS,0x02))              // Completion Status Set?
+    {
+      Return(1)               // Yes.  We are done.
+    }
+    Else
+    {
+      Decrement(Local0)       // Decrement Count.
+      Stall(50)               // Delay 50us.
+      If(LEqual(Local0,0))    // Count = 0?
+      {
+        KILL()          // Yes.  Kill Communication.
+      }
+    }
+  }
+
+  Return(0)                               // Timeout.  Return Failure.
+}
+
+// SMBus Kill Command
+
+Method(KILL,0,Serialized)
+{
+  OperationRegion(SMPB,PCI_Config,0x20,4)
+  Field(SMPB,DWordAcc,NoLock,Preserve)
+  {
+    ,     5,
+    SBAR, 11
+  }
+
+  // Define various SMBus IO Mapped Registers.
+
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
+  Field(SMBI,ByteAcc,NoLock,Preserve)
+  {
+    HSTS, 8,        // 0 - Host Status Register
+	Offset(0x02),
+	HCON, 8,        // 2 - Host Control
+	HCOM, 8,        // 3 - Host Command
+	TXSA, 8,        // 4 - Transmit Slave Address
+	DAT0, 8,        // 5 - Host Data 0
+	DAT1, 8,        // 6 - Host Data 1
+	HBDR, 8,        // 7 - Host Block Data
+	PECR, 8,        // 8 - Packer Error Check
+	RXSA, 8,        // 9 - Receive Slave Address
+	SDAT, 16,       // A - Slave Data
+  }
+  Or(HCON,0x02,HCON)                      // Yes.  Send Kill command.
+  Or(HSTS,0xFF,HSTS)                      // Clear all status.
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl

@@ -0,0 +1,385 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Haswell             *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+//scope is \_SB.PCI0.XHC
+Device(XHC1)
+{
+  Name(_ADR, 0x00140000)                     //Device 20, Function 0
+
+  //When it is in Host mode, USH core is connected to USB3 microAB(USB3 P1 and USB2 P0)
+  Name (_DDN, "Baytrail XHCI controller (CCG core/Host only)" )
+
+  Method(XDEP, 0)
+  {
+    If(LEqual(OSYS,2013))
+    {
+      Name(_DEP, Package(0x1)
+      {
+        PEPD
+      })
+    }
+  }
+
+  Name (_STR, Unicode ("Baytrail XHCI controller (CCG core/Host only)"))
+  Name(_PRW, Package() {0xD,4})
+
+  Method(_PSW,1)
+  {
+    If (LAnd (PMES, PMEE)) {
+       Store (0, PMEE)
+       Store (1, PMES)
+    }
+  }
+
+  OperationRegion (PMEB, PCI_Config, 0x74, 0x04)  // Power Management Control/Status
+  Field (PMEB, WordAcc, NoLock, Preserve)
+  {
+    ,   8,
+    PMEE,   1,   //bit8 PME_En
+    ,   6,
+    PMES,   1    //bit15 PME_Status
+  }
+
+  Method(_STA, 0)
+  {
+    If(LNotEqual(XHCI, 0))      //NVS variable controls present of XHCI controller
+    {
+      Return (0xF)
+    } Else
+    {
+      Return (0x0)
+    }
+  }
+
+  OperationRegion(XPRT,PCI_Config,0xD0,0x10)
+  Field(XPRT,DWordAcc,NoLock,Preserve)       //usbx_top.doc.xml
+  {
+    PR2,  32,                              //bit[8:0] USB2HCSEL
+    PR2M, 32,                              //bit[8:0] USB2HCSELM
+    PR3,  32,                              //bit[3:0] USB3SSEN
+    PR3M, 32                               //bit[3:0] USB3SSENM
+  }
+
+  Device(RHUB)
+  {
+    Name(_ADR, Zero)         //address 0 is reserved for root hub
+
+    //
+    // Super Speed Ports - must match _UPC declarations of the coresponding Full Speed Ports.
+    //   Paired with Port 1
+    Device(SSP1)
+    {
+      Name(_ADR, 0x07)
+
+      Method(_UPC,0,Serialized)
+      {
+        Name(UPCP, Package()
+        {
+          0xFF,                                      // Port is connectable if non-zero
+          0x06,                                      // USB3 uAB connector
+          0x00,
+          0x00
+        })
+        Return(UPCP)
+      }
+
+      Method(_PLD,0,Serialized)
+      {
+        Name(PLDP, Package()       //pls check ACPI 5.0 section 6.1.8
+        {
+          Buffer(0x14)
+          {
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
+            0x82, 0x00, 0x00, 0x00,
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000
+            0x00, 0x00, 0x00, 0x00,
+            //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center  bit[73:72]=b'01 Center
+            //           bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
+            0x4B, 0x19, 0x00, 0x00,
+            //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
+            0x03, 0x00, 0x00, 0x00,
+            //159:128  Vert. and Horiz. Offsets not supplied
+            0xFF, 0xFF, 0xFF, 0xFF
+          }
+        })
+        Return (PLDP)
+      }
+    }
+    //
+    // High Speed Ports
+    // pair port with port 7 (SS)
+    //    The UPC declarations for LS/FS/HS and SS ports that are paired to form a USB3.0 compatible connector.
+    //    A "pair" is defined by two ports that declare _PLDs with identical Panel, Vertical Position, Horizontal Postion, Shape, Group Orientation
+    //    and Group Token
+    Device(HS01)
+    {
+      Name(_ADR, 0x01)
+
+      Method(_UPC,0,Serialized)
+      {
+        Name(UPCP, Package() { 0xFF,0x06,0x00,0x00 })
+        Return(UPCP)
+      }
+
+      Method(_PLD,0,Serialized)
+      {
+        Name(PLDP, Package()       //pls check ACPI 5.0 section 6.1.8
+        {
+          Buffer(0x14)
+          {
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
+            0x82, 0x00, 0x00, 0x00,
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000
+            0x00, 0x00, 0x00, 0x00,
+            //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center  bit[73:72]=b'01 Center
+            //           bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
+            0x4B, 0x19, 0x00, 0x00,
+            //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
+            0x03, 0x00, 0x00, 0x00,
+            //159:128  Vert. and Horiz. Offsets not supplied
+            0xFF, 0xFF, 0xFF, 0xFF
+          }
+        })
+        Return (PLDP)
+      }
+    }//end of HS01
+
+    // USB2 Type-A/USB2 only
+    // EHCI debug capable
+    Device(HS02)
+    {
+      Name(_ADR, 0x02)                                   // 0 is for root hub so physical port index starts from 1 (it is port1 in schematic)
+
+      Method(_UPC,0,Serialized)
+      {
+        Name(UPCP, Package()
+        {
+          0xFF,                     // connectable
+          0xFF,                     //
+          0x00,
+          0x00
+        })
+
+        Return(UPCP)
+      }
+
+      Method(_PLD,0,Serialized)
+      {
+        Name(PLDP, Package()
+        {
+          Buffer(0x14)
+          {
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
+            0x82, 0x00, 0x00, 0x00,
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000
+            0x00, 0x00, 0x00, 0x00,
+            //95:64 - bit[66:64]=b'000 not visiable/no docking/no lid bit[69:67]=b'000 top bit[71:70]=b'01 Center  bit[73:72]=b'00 Left
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
+            0x40, 0x08, 0x00, 0x00,
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 no OSPM Ejection required Bit[105:98]=0 no Cabinet Number
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
+            0x00, 0x00, 0x00, 0x00,
+            //159:128  Vert. and Horiz. Offsets not supplied
+            0xFF, 0xFF, 0xFF, 0xFF
+          }
+        })
+
+        Return (PLDP)
+      }
+    }//end of HS02
+    // high speed port 3
+    Device(HS03)
+    {
+      Name(_ADR, 0x03)
+
+      Method(_UPC,0,Serialized)
+      {
+        Name(UPCP, Package()
+        {
+          0xFF,                     //  connectable
+          0xFF,
+          0x00,
+          0x00
+        })
+
+        Return(UPCP)
+      }
+
+      Method(_RMV, 0)                                    // for XHCICV debug purpose
+      {
+        Return(0x0)
+      }
+
+      Method(_PLD,0,Serialized)
+      {
+        Name(PLDP, Package()
+        {
+          Buffer(0x14)
+          {
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
+            0x82, 0x00, 0x00, 0x00,
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000
+            0x00, 0x00, 0x00, 0x00,
+            //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and  Horizontal Position will be ignored)
+            //           bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
+            0x30, 0x08, 0x00, 0x00,
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
+            0x00, 0x00, 0x00, 0x00,
+            //159:128  Vert. and Horiz. Offsets not supplied
+            0xFF, 0xFF, 0xFF, 0xFF
+          }
+        })
+        Return (PLDP)
+      }
+    }
+
+    Device(HS04)
+    {
+      Name(_ADR, 0x04)
+
+      Method(_UPC,0,Serialized)
+      {
+        Name(UPCP, Package()
+        {
+          0xFF,                     //connectable
+          0xFF,                     //Proprietary connector (FPC connector)
+          0x00,
+          0x00
+        })
+
+        Return(UPCP)
+      }
+      Method(_PLD,0,Serialized)
+      {
+        Name(PLDP, Package()
+        {
+          Buffer(0x14)
+          {
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
+            0x82, 0x00, 0x00, 0x00,
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000
+            0x00, 0x00, 0x00, 0x00,
+            //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and  Horizontal Position will be ignored)
+            //           bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
+            0x30, 0x08, 0x00, 0x00,
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
+            0x00, 0x00, 0x00, 0x00,
+            //159:128  Vert. and Horiz. Offsets not supplied
+            0xFF, 0xFF, 0xFF, 0xFF
+          }
+        })
+
+        Return (PLDP)
+      }
+    }
+
+
+    Device(HSC1)                                           // USB2 HSIC 01
+    {
+      Name(_ADR, 0x05)
+
+      Method(_UPC,0,Serialized)
+      {
+        Name(UPCP, Package()
+        {
+          0xFF,                     //connectable
+          0xFF,                     //Proprietary connector (FPC connector)
+          0x00,
+          0x00
+        })
+
+        Return(UPCP)
+      }
+      Method(_PLD,0,Serialized)
+      {
+        Name(PLDP, Package()
+        {
+          Buffer(0x14)
+          {
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
+            0x82, 0x00, 0x00, 0x00,
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000
+            0x00, 0x00, 0x00, 0x00,
+            //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and  Horizontal Position will be ignored)
+            //           bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
+            0x30, 0x08, 0x00, 0x00,
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
+            0x00, 0x00, 0x00, 0x00,
+            //159:128  Vert. and Horiz. Offsets not supplied
+            0xFF, 0xFF, 0xFF, 0xFF
+          }
+        })
+        Return (PLDP)
+      }
+    }
+
+    Device(HSC2)                                           // USB2 HSIC 02
+    {
+      Name(_ADR, 0x06)
+
+      Method(_UPC,0,Serialized)
+      {
+        Name(UPCP, Package()
+        {
+          0xFF,                     //connectable
+          0xFF,                     //Proprietary connector (FPC connector)
+          0x00,
+          0x00
+        })
+
+        Return(UPCP)
+      }
+      Method(_PLD,0,Serialized)
+      {
+        Name(PLDP, Package()
+        {
+          Buffer(0x14)
+          {
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored
+            0x82, 0x00, 0x00, 0x00,
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000
+            0x00, 0x00, 0x00, 0x00,
+            //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and  Horizontal Position will be ignored)
+            //           bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay
+            0x30, 0x08, 0x00, 0x00,
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order
+            0x00, 0x00, 0x00, 0x00,
+            //159:128  Vert. and Horiz. Offsets not supplied
+            0xFF, 0xFF, 0xFF, 0xFF
+          }
+        })
+        Return (PLDP)
+      }
+    }
+  }  //end of root hub
+
+} // end of XHC1
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl

@@ -0,0 +1,373 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+Scope(\_SB)
+{
+
+//RTC
+  Device(RTC)    // RTC
+  {
+    Name(_HID,EISAID("PNP0B00"))
+
+    Name(_CRS,ResourceTemplate()
+    {
+      IO(Decode16,0x70,0x70,0x01,0x08)
+    })
+  }
+//RTC
+
+  Device(HPET)   // High Performance Event Timer
+  {
+    Name (_HID, EisaId ("PNP0103"))
+    Name (_UID, 0x00)
+    Method (_STA, 0, NotSerialized)
+    {
+      Return (0x0F)
+    }
+
+    Method (_CRS, 0, Serialized)
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite,
+                       0xFED00000,         // Address Base
+                       0x00000400,         // Address Length
+                      )
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+        {
+          0x00000008,   //0xB HPET-2
+        }
+      })
+      Return (RBUF)
+    }
+  }
+//HPET
+
+  Name(PR00, Package()
+  {
+// SD Host #0 - eMMC
+    Package() {0x0010FFFF, 0, LNKA, 0 },
+// SD Host #1 - SDIO
+    Package() {0x0011FFFF, 0, LNKB, 0 },
+// SD Host #2 - SD Card
+    Package() {0x0012FFFF, 0, LNKC, 0 },
+// SATA Controller
+    Package() {0x0013FFFF, 0, LNKD, 0 },
+// xHCI Host
+    Package() {0x0014FFFF, 0, LNKE, 0 },
+// Low Power Audio Engine
+    Package() {0x0015FFFF, 0, LNKF, 0 },
+// USB OTG
+    Package() {0x0016FFFF, 0, LNKG, 0 },
+// MIPI-HSI/eMMC4.5
+    Package() {0x0017FFFF, 0, LNKH, 0 },
+// LPSS2 DMA
+// LPSS2 I2C #4
+    Package() {0x0018FFFF, 0, LNKB, 0 },
+// LPSS2 I2C #1
+// LPSS2 I2C #5
+    Package() {0x0018FFFF, 2, LNKD, 0 },
+// LPSS2 I2C #2
+// LPSS2 I2C #6
+    Package() {0x0018FFFF, 3, LNKC, 0 },
+// LPSS2 I2C #3
+// LPSS2 I2C #7
+    Package() {0x0018FFFF, 1, LNKA, 0 },
+// SeC
+    Package() {0x001AFFFF, 0, LNKF, 0 },
+//
+// High Definition Audio Controller
+    Package() {0x001BFFFF, 0, LNKG, 0 },
+//
+// EHCI Controller
+    Package() {0x001DFFFF, 0, LNKH, 0 },
+// LPSS DMA
+    Package() {0x001EFFFF, 0, LNKD, 0 },
+// LPSS I2C #0
+    Package() {0x001EFFFF, 3, LNKA, 0 },
+// LPSS I2C #1
+    Package() {0x001EFFFF, 1, LNKB, 0 },
+// LPSS PCM
+    Package() {0x001EFFFF, 2, LNKC, 0 },
+// LPSS I2S
+// LPSS HS-UART #0
+// LPSS HS-UART #1
+// LPSS SPI
+// LPC Bridge
+//
+// SMBus Controller
+    Package() {0x001FFFFF, 1, LNKC, 0 },
+//
+// PCIE Root Port #1
+    Package() {0x001CFFFF, 0, LNKA, 0 },
+// PCIE Root Port #2
+    Package() {0x001CFFFF, 1, LNKB, 0 },
+// PCIE Root Port #3
+    Package() {0x001CFFFF, 2, LNKC, 0 },
+// PCIE Root Port #4
+    Package() {0x001CFFFF, 3, LNKD, 0 },
+
+// Host Bridge
+// Mobile IGFX
+    Package() {0x0002FFFF, 0, LNKA, 0 },
+  })
+
+  Name(AR00, Package()
+  {
+// SD Host #0 - eMMC
+    Package() {0x0010FFFF, 0, 0, 16 },
+// SD Host #1 - SDIO
+    Package() {0x0011FFFF, 0, 0, 17 },
+// SD Host #2 - SD Card
+    Package() {0x0012FFFF, 0, 0, 18 },
+// SATA Controller
+    Package() {0x0013FFFF, 0, 0, 19 },
+// xHCI Host
+    Package() {0x0014FFFF, 0, 0, 20 },
+// Low Power Audio Engine
+    Package() {0x0015FFFF, 0, 0, 21 },
+// USB OTG
+    Package() {0x0016FFFF, 0, 0, 22 },
+//
+// MIPI-HSI
+    Package() {0x0017FFFF, 0, 0, 23 },
+//
+// LPSS2 DMA
+// LPSS2 I2C #4
+    Package() {0x0018FFFF, 0, 0, 17 },
+// LPSS2 I2C #1
+// LPSS2 I2C #5
+    Package() {0x0018FFFF, 2, 0, 19 },
+// LPSS2 I2C #2
+// LPSS2 I2C #6
+    Package() {0x0018FFFF, 3, 0, 18 },
+// LPSS2 I2C #3
+// LPSS2 I2C #7
+    Package() {0x0018FFFF, 1, 0, 16 },
+
+// SeC
+    Package() {0x001AFFFF, 0, 0, 21 },
+//
+// High Definition Audio Controller
+    Package() {0x001BFFFF, 0, 0, 22 },
+//
+// EHCI Controller
+    Package() {0x001DFFFF, 0, 0, 23 },
+// LPSS DMA
+    Package() {0x001EFFFF, 0, 0, 19 },
+// LPSS I2C #0
+    Package() {0x001EFFFF, 3, 0, 16 },
+// LPSS I2C #1
+    Package() {0x001EFFFF, 1, 0, 17 },
+// LPSS PCM
+    Package() {0x001EFFFF, 2, 0, 18 },
+// LPSS I2S
+// LPSS HS-UART #0
+// LPSS HS-UART #1
+// LPSS SPI
+// LPC Bridge
+//
+// SMBus Controller
+    Package() {0x001FFFFF, 1, 0, 18 },
+//
+// PCIE Root Port #1
+    Package() {0x001CFFFF, 0, 0, 16 },
+// PCIE Root Port #2
+    Package() {0x001CFFFF, 1, 0, 17 },
+// PCIE Root Port #3
+    Package() {0x001CFFFF, 2, 0, 18 },
+// PCIE Root Port #4
+    Package() {0x001CFFFF, 3, 0, 19 },
+// Host Bridge
+// Mobile IGFX
+    Package() {0x0002FFFF, 0, 0, 16 },
+  })
+
+  Name(PR04, Package()
+  {
+// PCIE Port #1 Slot
+    Package() {0x0000FFFF, 0, LNKA, 0 },
+    Package() {0x0000FFFF, 1, LNKB, 0 },
+    Package() {0x0000FFFF, 2, LNKC, 0 },
+    Package() {0x0000FFFF, 3, LNKD, 0 },
+  })
+
+  Name(AR04, Package()
+  {
+// PCIE Port #1 Slot
+    Package() {0x0000FFFF, 0, 0, 16 },
+    Package() {0x0000FFFF, 1, 0, 17 },
+    Package() {0x0000FFFF, 2, 0, 18 },
+    Package() {0x0000FFFF, 3, 0, 19 },
+  })
+
+  Name(PR05, Package()
+  {
+// PCIE Port #2 Slot
+    Package() {0x0000FFFF, 0, LNKB, 0 },
+    Package() {0x0000FFFF, 1, LNKC, 0 },
+    Package() {0x0000FFFF, 2, LNKD, 0 },
+    Package() {0x0000FFFF, 3, LNKA, 0 },
+  })
+
+  Name(AR05, Package()
+  {
+// PCIE Port #2 Slot
+    Package() {0x0000FFFF, 0, 0, 17 },
+    Package() {0x0000FFFF, 1, 0, 18 },
+    Package() {0x0000FFFF, 2, 0, 19 },
+    Package() {0x0000FFFF, 3, 0, 16 },
+  })
+
+  Name(PR06, Package()
+  {
+// PCIE Port #3 Slot
+    Package() {0x0000FFFF, 0, LNKC, 0 },
+    Package() {0x0000FFFF, 1, LNKD, 0 },
+    Package() {0x0000FFFF, 2, LNKA, 0 },
+    Package() {0x0000FFFF, 3, LNKB, 0 },
+  })
+
+  Name(AR06, Package()
+  {
+// PCIE Port #3 Slot
+    Package() {0x0000FFFF, 0, 0, 18 },
+    Package() {0x0000FFFF, 1, 0, 19 },
+    Package() {0x0000FFFF, 2, 0, 16 },
+    Package() {0x0000FFFF, 3, 0, 17 },
+  })
+
+  Name(PR07, Package()
+  {
+// PCIE Port #4 Slot
+    Package() {0x0000FFFF, 0, LNKD, 0 },
+    Package() {0x0000FFFF, 1, LNKA, 0 },
+    Package() {0x0000FFFF, 2, LNKB, 0 },
+    Package() {0x0000FFFF, 3, LNKC, 0 },
+  })
+
+  Name(AR07, Package()
+  {
+// PCIE Port #4 Slot
+    Package() {0x0000FFFF, 0, 0, 19 },
+    Package() {0x0000FFFF, 1, 0, 16 },
+    Package() {0x0000FFFF, 2, 0, 17 },
+    Package() {0x0000FFFF, 3, 0, 18 },
+  })
+
+  Name(PR01, Package()
+  {
+// PCI slot 1
+    Package() {0x0000FFFF, 0, LNKF, 0 },
+    Package() {0x0000FFFF, 1, LNKG, 0 },
+    Package() {0x0000FFFF, 2, LNKH, 0 },
+    Package() {0x0000FFFF, 3, LNKE, 0 },
+// PCI slot 2
+    Package() {0x0001FFFF, 0, LNKG, 0 },
+    Package() {0x0001FFFF, 1, LNKF, 0 },
+    Package() {0x0001FFFF, 2, LNKE, 0 },
+    Package() {0x0001FFFF, 3, LNKH, 0 },
+// PCI slot 3
+    Package() {0x0002FFFF, 0, LNKC, 0 },
+    Package() {0x0002FFFF, 1, LNKD, 0 },
+    Package() {0x0002FFFF, 2, LNKB, 0 },
+    Package() {0x0002FFFF, 3, LNKA, 0 },
+// PCI slot 4
+    Package() {0x0003FFFF, 0, LNKD, 0 },
+    Package() {0x0003FFFF, 1, LNKC, 0 },
+    Package() {0x0003FFFF, 2, LNKF, 0 },
+    Package() {0x0003FFFF, 3, LNKG, 0 },
+  })
+
+  Name(AR01, Package()
+  {
+// PCI slot 1
+    Package() {0x0000FFFF, 0, 0, 21 },
+    Package() {0x0000FFFF, 1, 0, 22 },
+    Package() {0x0000FFFF, 2, 0, 23 },
+    Package() {0x0000FFFF, 3, 0, 20 },
+// PCI slot 2
+    Package() {0x0001FFFF, 0, 0, 22 },
+    Package() {0x0001FFFF, 1, 0, 21 },
+    Package() {0x0001FFFF, 2, 0, 20 },
+    Package() {0x0001FFFF, 3, 0, 23 },
+// PCI slot 3
+    Package() {0x0002FFFF, 0, 0, 18 },
+    Package() {0x0002FFFF, 1, 0, 19 },
+    Package() {0x0002FFFF, 2, 0, 17 },
+    Package() {0x0002FFFF, 3, 0, 16 },
+// PCI slot 4
+    Package() {0x0003FFFF, 0, 0, 19 },
+    Package() {0x0003FFFF, 1, 0, 18 },
+    Package() {0x0003FFFF, 2, 0, 21 },
+    Package() {0x0003FFFF, 3, 0, 22 },
+  })
+//---------------------------------------------------------------------------
+// List of IRQ resource buffers compatible with _PRS return format.
+//---------------------------------------------------------------------------
+// Naming legend:
+// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
+// Note. PRSy name is generated if IRQ Link name starts from "LNK".
+// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
+//---------------------------------------------------------------------------
+  Name(PRSA, ResourceTemplate()         // Link name: LNKA
+  {
+    IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
+  })
+  Alias(PRSA,PRSB)      // Link name: LNKB
+  Alias(PRSA,PRSC)      // Link name: LNKC
+  Alias(PRSA,PRSD)      // Link name: LNKD
+  Alias(PRSA,PRSE)      // Link name: LNKE
+  Alias(PRSA,PRSF)      // Link name: LNKF
+  Alias(PRSA,PRSG)      // Link name: LNKG
+  Alias(PRSA,PRSH)      // Link name: LNKH
+//---------------------------------------------------------------------------
+// Begin PCI tree object scope
+//---------------------------------------------------------------------------
+
+  Device(PCI0)   // PCI Bridge "Host Bridge"
+  {
+    Name(_HID, EISAID("PNP0A08"))       // Indicates PCI Express/PCI-X Mode2 host hierarchy
+    Name(_CID, EISAID("PNP0A03"))       // To support legacy OS that doesn't understand the new HID
+    Name(_ADR, 0x00000000)
+    Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
+    Method(_BBN, 0) { return(BN00()) }  // Bus number, optional for the Root PCI Bus
+    Name(_UID, 0x0000)  // Unique Bus ID, optional
+    Name(_DEP, Package(0x1)
+    {
+      PEPD
+    })
+
+                            Method(_PRT,0)
+    {
+      If(PICM) {Return(AR00)} // APIC mode
+      Return (PR00) // PIC Mode
+    } // end _PRT
+
+    include("HOST_BUS.ASL")
+    Device(LPCB)   // LPC Bridge
+    {
+      Name(_ADR, 0x001F0000)
+      include("LpcB.asl")
+    } // end "LPC Bridge"
+
+  } // end PCI0 Bridge "Host Bridge"
+} // end _SB scope

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl

@@ -0,0 +1,830 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+// Define the following External variables to prevent a WARNING when
+// using ASL.EXE and an ERROR when using IASL.EXE.
+
+External(PDC0)
+External(PDC1)
+External(PDC2)
+External(PDC3)
+External(CFGD)
+External(\_PR.CPU0._PPC, IntObj)
+External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj)
+External(\_SB.STR3, DeviceObj)
+External(\_SB.I2C1.BATC, DeviceObj)
+External(\_SB.DPTF, DeviceObj)
+External(\_SB.TCHG, DeviceObj)
+External(\_SB.IAOE.PTSL)
+External(\_SB.IAOE.WKRS)
+
+//
+// Create a Global MUTEX.
+//
+Mutex(MUTX,0)
+
+
+
+// Port 80h Update:
+//              Update 8 bits of the 32-bit Port 80h.
+//
+//      Arguments:
+//              Arg0:   0 = Write Port 80h, Bits 7:0 Only.
+//                      1 = Write Port 80h, Bits 15:8 Only.
+//                      2 = Write Port 80h, Bits 23:16 Only.
+//                      3 = Write Port 80h, Bits 31:24 Only.
+//              Arg1:   8-bit Value to write
+//
+//      Return Value:
+//              None
+
+Method(P8XH,2,Serialized)
+{
+  If(LEqual(Arg0,0))            // Write Port 80h, Bits 7:0.
+  {
+    Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)
+  }
+
+  If(LEqual(Arg0,1))            // Write Port 80h, Bits 15:8.
+  {
+    Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)
+  }
+
+  If(LEqual(Arg0,2))            // Write Port 80h, Bits 23:16.
+  {
+    Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)
+  }
+
+  If(LEqual(Arg0,3))            // Write Port 80h, Bits 31:24.
+  {
+    Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)
+  }
+
+}
+
+//
+// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.
+//
+OperationRegion (SPRT, SystemIO, 0xB2, 2)
+Field (SPRT, ByteAcc, Lock, Preserve)
+{
+  SSMP, 8
+}
+
+// The _PIC Control Method is optional for ACPI design.  It allows the
+// OS to inform the ASL code which interrupt controller is being used,
+// the 8259 or APIC.  The reference code in this document will address
+// PCI IRQ Routing and resource allocation for both cases.
+//
+// The values passed into _PIC are:
+//       0 = 8259
+//       1 = IOAPIC
+
+Method(\_PIC,1)
+{
+  Store(Arg0,GPIC)
+  Store(Arg0,PICM)
+}
+
+OperationRegion(SWC0, SystemIO, 0x610, 0x0F)
+Field(SWC0, ByteAcc, NoLock, Preserve)
+{
+  G1S, 8,      //SWC GPE1_STS
+  Offset(0x4),
+  G1E, 8,
+  Offset(0xA),
+  G1S2, 8,     //SWC GPE1_STS_2
+  G1S3, 8      //SWC GPE1_STS_3
+}
+
+OperationRegion (SWC1, SystemIO, \PMBS, 0x2C)
+Field(SWC1, DWordAcc, NoLock, Preserve)
+{
+  Offset(0x20),
+  G0S, 32,      //GPE0_STS
+  Offset(0x28),
+  G0EN, 32      //GPE0_EN
+}
+
+// Prepare to Sleep.  The hook is called when the OS is about to
+// enter a sleep state.  The argument passed is the numeric value of
+// the Sx state.
+
+Method(_PTS,1)
+{
+  Store(0,P80D)         // Zero out the entire Port 80h DWord.
+  P8XH(0,Arg0)          // Output Sleep State to Port 80h, Byte 0.
+
+  //clear the 3 SWC status bits
+  Store(Ones, G1S3)
+  Store(Ones, G1S2)
+  Store(1, G1S)
+
+  //set SWC GPE1_EN
+  Store(1,G1E)
+
+  //clear GPE0_STS
+  Store(Ones, G0S)
+
+
+  If(LEqual(Arg0,3))   // If S3 Suspend
+  {
+    //
+    // Disable Digital Thermal Sensor function when doing S3 suspend
+    //
+    If(CondRefOf(DTSE))
+    {
+      If(LGreaterEqual(DTSE, 0x01))
+      {
+        Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI
+        Store(0xD0, SSMP) // DTS SW SMI
+      }
+    }
+  }
+}
+
+// Wake.  This hook is called when the OS is about to wake from a
+// sleep state.  The argument passed is the numeric value of the
+// sleep state the system is waking from.
+Method(_WAK,1,Serialized)
+{
+  P8XH(1,0xAB) // Beginning of _WAK.
+
+  Notify(\_SB.PWRB,0x02)
+
+  If(NEXP)
+  {
+    // Reinitialize the Native PCI Express after resume
+    If(And(OSCC,0x02))
+    {
+      \_SB.PCI0.NHPG()
+    }
+
+    If(And(OSCC,0x04))   // PME control granted?
+    {
+      \_SB.PCI0.NPME()
+    }
+  }
+
+  If(LOr(LEqual(Arg0,3), LEqual(Arg0,4)))   // If S3 or S4 Resume
+  {
+
+
+    // If CMP is enabled, we may need to restore the C-State and/or
+    // P-State configuration, as it may have been saved before the
+    // configuration was finalized based on OS/driver support.
+    //
+    //   CFGD[24]  = Two or more cores enabled
+    //
+    If(And(CFGD,0x01000000))
+    {
+      //
+      // If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if
+      // C-States are enabled.
+      //
+      //   CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled
+      //
+      //
+    }
+
+    // Windows XP SP2 does not properly restore the P-State
+    // upon resume from S4 or S3 with degrade modes enabled.
+    // Use the existing _PPC methods to cycle the available
+    // P-States such that the processor ends up running at
+    // the proper P-State.
+    //
+    // Note:  For S4, another possible W/A is to always boot
+    // the system in LFM.
+    //
+    If(LEqual(OSYS,2002))
+    {
+      If(And(CFGD,0x01))
+      {
+        If(LGreater(\_PR.CPU0._PPC,0))
+        {
+          Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
+          PNOT()
+          Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
+          PNOT()
+        }
+        Else
+        {
+          Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
+          PNOT()
+          Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
+          PNOT()
+        }
+      }
+    }
+  }
+  Return(Package() {0,0})
+}
+
+// Power Notification:
+//              Perform all needed OS notifications during a
+//              Power Switch.
+//
+//      Arguments:
+//              None
+//
+//      Return Value:
+//              None
+
+Method(PNOT,0,Serialized)
+{
+  // If MP enabled and driver support is present, notify all
+  // processors.
+
+  If(MPEN)
+  {
+    If(And(PDC0,0x0008))
+    {
+      Notify(\_PR.CPU0,0x80)    // Eval CPU0 _PPC.
+
+      If(And(PDC0,0x0010))
+      {
+        Sleep(100)
+        Notify(\_PR.CPU0,0x81)  // Eval _CST.
+      }
+    }
+
+    If(And(PDC1,0x0008))
+    {
+      Notify(\_PR.CPU1,0x80)    // Eval CPU1 _PPC.
+
+      If(And(PDC1,0x0010))
+      {
+        Sleep(100)
+        Notify(\_PR.CPU1,0x81)  // Eval _CST.
+      }
+    }
+
+    If(And(PDC2,0x0008))
+    {
+      Notify(\_PR.CPU2,0x80)    // Eval CPU2 _PPC.
+
+      If(And(PDC2,0x0010))
+      {
+        Sleep(100)
+        Notify(\_PR.CPU2,0x81)  // Eval _CST.
+      }
+    }
+
+    If(And(PDC3,0x0008))
+    {
+      Notify(\_PR.CPU3,0x80)    // Eval CPU3 _PPC.
+
+      If(And(PDC3,0x0010))
+      {
+        Sleep(100)
+        Notify(\_PR.CPU3,0x81)  // Eval _CST.
+      }
+    }
+  }
+  Else
+  {
+    Notify(\_PR.CPU0,0x80)      // Eval _PPC.
+    Sleep(100)
+    Notify(\_PR.CPU0,0x81)      // Eval _CST
+  }
+}
+
+//
+// System Bus
+//
+Scope(\_SB)
+{
+  Name(CRTT, 110) // Processor critical temperature
+  Name(ACTT, 77)  // Active temperature limit for processor participant
+  Name(GCR0, 70)  // Critical temperature for Generic participant 0 in degree celsius
+  Name(GCR1, 70)  // Critical temperature for Generic participant 1 in degree celsius
+  Name(GCR2, 70)  // Critical temperature for Generic participant 2 in degree celsius
+  Name(GCR3, 70)  // Critical temperature for Generic participant 3 in degree celsius
+  Name(GCR4, 70)  // Critical temperature for Generic participant 4 in degree celsius
+  Name(GCR5, 70)  // Critical temperature for Generic participant 5 in degree celsius
+  Name(GCR6, 70)  // Critical temperature for Generic participant 6 in degree celsius
+  Name(PST0, 60)  // Passive temperature limit for Generic Participant 0 in degree celsius
+  Name(PST1, 60)  // Passive temperature limit for Generic Participant 1 in degree celsius
+  Name(PST2, 60)  // Passive temperature limit for Generic Participant 2 in degree celsius
+  Name(PST3, 60)  // Passive temperature limit for Generic Participant 3 in degree celsius
+  Name(PST4, 60)  // Passive temperature limit for Generic Participant 4 in degree celsius
+  Name(PST5, 60)  // Passive temperature limit for Generic Participant 5 in degree celsius
+  Name(PST6, 60)  // Passive temperature limit for Generic Participant 6 in degree celsius
+  Name(LPMV, 3)
+  Name(PDBG, 0)   // DPTF Super debug option
+  Name(PDPM, 1)   // DPTF DPPM enable
+  Name(PDBP, 1)   // DPTF DBPT enable (dynamic battery protection technology)
+  Name(DLPO, Package()
+  {
+    0x1, // Revision
+    0x1, // LPO Enable
+    0x1, // LPO StartPState
+    25,  // LPO StepSize
+    0x1, //
+    0x1, //
+  })
+  Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change
+  // or it is from Graphics driver. Value of 1 is for DPTF else it is 0
+
+  Method(_INI,0)
+  {
+    // NVS has stale DTS data.  Get and update the values
+    // with current temperatures.   Note that this will also
+    // re-arm any AP Thermal Interrupts.
+    // Read temperature settings from global NVS
+    Store(DPCT, CRTT)
+    Store(Subtract(DPPT, 8), ACTT)                      // Active Trip point = Passive trip point - 8
+    Store(DGC0, GCR0)
+    Store(DGC0, GCR1)
+    Store(DGC1, GCR2)
+    Store(DGC1, GCR3)
+    Store(DGC1, GCR4)
+    Store(DGC2, GCR5)
+    Store(DGC2, GCR6)
+    Store(DGP0, PST0)
+    Store(DGP0, PST1)
+    Store(DGP1, PST2)
+    Store(DGP1, PST3)
+    Store(DGP1, PST4)
+    Store(DGP2, PST5)
+    Store(DGP2, PST6)
+    // Read Current low power mode setting from global NVS
+    Store(DLPM, LPMV)
+
+
+    // Update DPTF Super Debug option
+    Store(DDBG, PDBG)
+
+
+    // Update DPTF LPO Options
+    Store(LPOE, Index(DLPO,1))
+    Store(LPPS, Index(DLPO,2))
+    Store(LPST, Index(DLPO,3))
+    Store(LPPC, Index(DLPO,4))
+    Store(LPPF, Index(DLPO,5))
+    Store(DPME, PDPM)
+  }
+
+  // Define a (Control Method) Power Button.
+  Device(PWRB)
+  {
+    Name(_HID,EISAID("PNP0C0C"))
+
+    // GPI_SUS0 = GPE16 = Waketime SCI.  The PRW isn't working when
+    // placed in any of the logical locations ( PS2K, PS2M),
+    // so a Power Button Device was created specifically
+    // for the WAKETIME_SCI PRW.
+
+    Name(_PRW, Package() {16,4})
+  }
+
+  Device(SLPB)
+  {
+    Name(_HID, EISAID("PNP0C0E"))
+  } // END SLPB
+
+  Scope(PCI0)
+  {
+    Method(_INI,0)
+    {
+      // Determine the OS and store the value, where:
+      //
+      //   OSYS = 2009 = Windows 7 and Windows Server 2008 R2.
+      //   OSYS = 2012 = Windows 8 and Windows Server 2012.
+      //
+      // Assume Windows 7 at a minimum.
+
+      Store(2009,OSYS)
+
+      // Check for a specific OS which supports _OSI.
+
+      If(CondRefOf(\_OSI,Local0))
+      {
+        // Linux returns _OSI = TRUE for numerous Windows
+        // strings so that it is fully compatible with
+        // BIOSes available in the market today.  There are
+        // currently 2 known exceptions to this model:
+        //      1) Video Repost - Linux supports S3 without
+        //              requireing a Driver, meaning a Video
+        //              Repost will be required.
+        //      2) On-Screen Branding - a full CMT Logo
+        //              is limited to the WIN2K and WINXP
+        //              Operating Systems only.
+
+        // Use OSYS for Windows Compatibility.
+        If(\_OSI("Windows 2009"))   // Windows 7 or Windows Server 2008 R2
+        {
+          Store(2009,OSYS)
+        }
+        If(\_OSI("Windows 2012"))   // Windows 8 or Windows Server 2012
+        {
+          Store(2012,OSYS)
+        }
+        If(\_OSI("Windows 2013"))   //Windows Blue
+        {
+          Store(2013,OSYS)
+        }
+
+        //
+        // If CMP is enabled, enable SMM C-State
+        // coordination.  SMM C-State coordination
+        // will be disabled in _PDC if driver support
+        // for independent C-States deeper than C1
+        // is indicated.
+      }
+    }
+
+    Method(NHPG,0,Serialized)
+    {
+
+    }
+
+    Method(NPME,0,Serialized)
+    {
+
+    }
+  } // end Scope(PCI0)
+
+  Device (GPED)   //virtual GPIO device for ASL based AC/Battery/Expection notification
+  {
+    Name (_ADR, 0)
+    Name (_HID, "INT0002")
+    Name (_CID, "INT0002")
+    Name (_DDN, "Virtual GPIO controller" )
+    Name (_UID, 1)
+
+    Method (_CRS, 0x0, Serialized)
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9
+      })
+      Return (RBUF)
+    }
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return(0x0)
+    }
+
+    Method (_AEI, 0x0, Serialized)
+    {
+      Name(RBUF, ResourceTemplate()
+      {
+        GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2
+      })
+      Return(RBUF)
+    }
+
+    Method(_E02)   // _Exx method will be called when interrupt is raised
+    {
+      If (LEqual (PWBS, 1))
+      {
+        Store (1, PWBS)      //Clear PowerButton Status
+      }
+      If (LEqual (PMEB, 1))
+      {
+        Store (1, PMEB)      //Clear PME_B0_STS
+      }
+      If (LEqual (\_SB.PCI0.SATA.PMES, 1))
+      {
+        Store (1, \_SB.PCI0.SATA.PMES)
+        Notify (\_SB.PCI0.SATA, 0x02)
+      }
+      //
+      // eMMC 4.41
+      //
+      If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1)))
+      {
+        Store (1, \_SB.PCI0.EM41.PMES)
+        Notify (\_SB.PCI0.EM41, 0x02)
+      }
+
+      //
+      // eMMC 4.5
+      //
+      If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1)))
+      {
+        Store (1, \_SB.PCI0.EM45.PMES)
+        Notify (\_SB.PCI0.EM45, 0x02)
+      }
+
+      If (LEqual(HDAD, 0))
+      {
+        If (LEqual (\_SB.PCI0.HDEF.PMES, 1))
+        {
+          Store (1, \_SB.PCI0.HDEF.PMES)
+          Notify (\_SB.PCI0.HDEF, 0x02)
+        }
+      }
+
+      If (LEqual (\_SB.PCI0.EHC1.PMES, 1))
+      {
+        Store (1, \_SB.PCI0.EHC1.PMES)
+        Notify (\_SB.PCI0.EHC1, 0x02)
+      }
+      If (LEqual (\_SB.PCI0.XHC1.PMES, 1))
+      {
+        Store (1, \_SB.PCI0.XHC1.PMES)
+        Notify (\_SB.PCI0.XHC1, 0x02)
+      }
+      If (LEqual (\_SB.PCI0.SEC0.PMES, 1))
+      {
+        Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES)
+        Notify (\_SB.PCI0.SEC0, 0x02)
+      }
+    }
+  } //  Device (GPED)
+
+  //--------------------
+  //  GPIO
+  //--------------------
+  Device (GPO0)
+  {
+    Name (_ADR, 0)
+    Name (_HID, "INT33FC")
+    Name (_CID, "INT33B2")
+    Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" )
+    Name (_UID, 1)
+    Method (_CRS, 0x0, Serialized)
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000)
+        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49}
+
+      })
+      Return (RBUF)
+    }
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      //
+      // GPO driver will report present if any of below New IO bus exist
+      //
+      If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist
+      { Return(0xF) }
+      If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist
+      { Return(0xF) }
+      If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist
+      { Return(0xF) }
+      If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist
+      { Return(0xF) }
+      If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist
+      { Return(0xF) }
+      If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist
+      { Return(0xF) }
+      If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist
+      { Return(0xF) }
+      If (LEqual(L27D, 0))                       // LPIO2 I2C #7 exist
+      { Return(0xF) }
+
+      Return(0x0)
+    }
+
+    // Track status of GPIO OpRegion availability for this controller
+    Name(AVBL, 0)
+    Method(_REG,2)
+    {
+      If (Lequal(Arg0, 8))
+      {
+        Store(Arg1, ^AVBL)
+      }
+    }
+
+    OperationRegion(GPOP, SystemIo, \GPBS, 0x50)
+      Field(GPOP, ByteAcc, NoLock, Preserve) {
+      Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h
+          ,  21,
+      BTD3,  1,     //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP
+      Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h
+          ,  30,
+      SHD3,  1      //GPIO_S0_SC_95 - SENS_HUB_RST_N
+    }
+
+
+
+  }   //  Device (GPO0)
+
+  Device (GPO1)
+  {
+    Name (_ADR, 0)
+    Name (_HID, "INT33FC")
+    Name (_CID, "INT33B2")
+    Name (_DDN, "ValleyView2 GPNCORE controller" )
+    Name (_UID, 2)
+    Method (_CRS, 0x0, Serialized)
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000)
+        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48}
+      })
+      Return (RBUF)
+    }
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return(\_SB.GPO0._STA)
+    }
+  }   //  Device (GPO1)
+
+  Device (GPO2)
+  {
+    Name (_ADR, 0)
+    Name (_HID, "INT33FC")
+    Name (_CID, "INT33B2")
+    Name (_DDN, "ValleyView2 GPSUS controller" )
+    Name (_UID, 3)
+    Method (_CRS, 0x0, Serialized)
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000)
+        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50}
+      })
+      Return (RBUF)
+    }
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return(^^GPO0._STA)
+    }
+
+    // Track status of GPIO OpRegion availability for this controller
+    Name(AVBL, 0)
+    Method(_REG,2)
+    {
+      If (Lequal(Arg0, 8))
+      {
+        Store(Arg1, ^AVBL)
+      }
+    }
+    //Manipulate GPIO line using GPIO operation regions.
+    Name (GMOD, ResourceTemplate ()     //One method of creating a Connection for OpRegion accesses in Field definitions
+    {
+      //is creating a named object that refers to the connection attributes
+      GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21}  //sus 21+128 BT+WLAN_ENABLE
+    })
+
+  OperationRegion(GPOP, SystemIo, \GPBS, 0x100)
+  Field(GPOP, ByteAcc, NoLock, Preserve) {
+      Offset(0x88),  // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h
+          ,  20,
+      WFD3,  1
+    }
+
+
+  }   //  Device (GPO2)
+  include ("PchScc.asl")
+  include ("PchLpss.asl")
+
+         Scope(I2C7)
+  {
+
+  } //End Scope(I2C7)
+
+  //
+  // Device for Message Bus Interface
+  //
+  Device(MBID)
+  {
+    Name(_HID, "INT33BD")
+    Name(_CID, "INT33BD")
+    Name(_HRV, 2)//different from CLT's
+    Name(_UID, 1)
+
+    Method (_CRS, 0, Serialized)
+    {
+      Name (RBUF, ResourceTemplate ()
+      {
+        Memory32Fixed (
+          ReadWrite,
+          0xE00000D0, // Address Base
+          0xC,        // Address Length (MCR/MDR/MCRX)
+        )
+      })
+      Return (RBUF)
+    }
+
+
+    //
+    // custom opregion for MBI access
+    //
+    OperationRegion (REGS, 0x87, 0x0, 0x30)
+    Field (REGS, DWordAcc, NoLock, Preserve)
+    {
+      PORT, 32,    // Message Port
+      REG,  32,    // Message Target Register Address
+      DATA, 32,    // Message Data
+      MASK, 32,    // Mask bits for modify operation
+      BE,   32,    // Message Write Byte enables: 0 - BYTE; 1 - WORD; 2 - DWORD
+      OP,   32     // Operations: 0 - read; 1 - write; 2 - modify
+    }
+
+    //
+    // availability of the custom opregion
+    //
+    Name (AVBL, 0)
+    Method(_REG,2)
+    {
+      If (Lequal(Arg0, 0x87))
+      {
+        Store(Arg1, ^AVBL)
+      }
+    }
+
+    //
+    //  Method Name: READ
+    //  Arguments:
+    //    Arg0:   PORT
+    //    Arg1:   REG
+    //    Arg2:   BE
+    //  Return Value:
+    //  DATA
+    //
+    Method(READ, 3, Serialized)
+    {
+      Store(0xFFFFFFFF , Local0)
+      If (Lequal (AVBL, 1))
+      {
+        Store(0, OP)  // must be set at first, do not change!
+        Store(Arg0, PORT)
+        Store(Arg1, REG)
+        Store(Arg2, BE)
+        Store(DATA, Local0)
+      }
+      return(Local0)
+    }
+
+    //
+    //  Method Name: WRIT
+    //  Arguments:
+    //    Arg0:   PORT
+    //    Arg1:   REG
+    //    Arg2:   BE
+    //    Arg3:   DATA
+    //  Return Value:
+    //  NONE
+    //
+    Method(WRIT, 4, Serialized)
+    {
+      If (Lequal (AVBL, 1))
+      {
+        Store(1, OP)  // must be set at first, do not change!
+        Store(Arg0, PORT)
+        Store(Arg1, REG)
+        Store(Arg2, BE)
+        Store(Arg3, DATA)
+      }
+    }
+
+    //
+    //  Method Name: MODI
+    //  Arguments:
+    //    Arg0:   PORT
+    //    Arg1:   REG
+    //    Arg2:   BE
+    //    Arg3:   DATA
+    //    Arg4:   MASK
+    //  Return Value:
+    //  NONE
+    //
+    Method(MODI, 5, Serialized)
+    {
+      If (Lequal (AVBL, 1))
+      {
+        Store(2, OP)  // must be set at first, do not change!
+        Store(Arg0, PORT)
+        Store(Arg1, REG)
+        Store(Arg2, BE)
+        Store(Arg3, DATA)
+        Store(Arg4, MASK)
+      }
+    }
+  }
+
+
+} // end Scope(\_SB)
+
+Name(PICM, 0)   // Global Name, returns current Interrupt controller mode; updated from _PIC control method
+

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl

@@ -0,0 +1,203 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+DefinitionBlock (
+  "Rtd3.aml",
+  "SSDT",
+  1,
+  "AcpiRef",
+  "Msg_Rtd3",
+  0x1000
+)
+{
+  External(RTD3)             //flag if RTD3 is enabled
+
+  If(LEqual(RTD3,1))
+  {
+    Scope (\_SB)
+    {
+      Name(OSCI, 0)  // \_SB._OSC DWORD2 input
+      Name(OSCO, 0)  // \_SB._OSC DWORD2 output
+
+      //Arg0 -- A buffer containing UUID
+      //Arg1 -- An Interger containing a Revision ID of the buffer format
+      //Arg2 -- An interger containing a count of entries in Arg3
+      //Arg3 -- A buffer containing a list of DWORD capacities
+      Method(_OSC, 4, NotSerialized)
+      {
+        // Check for proper UUID
+        If(LEqual(Arg0, ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
+        {
+          CreateDWordField(Arg3,0,CDW1)     //bit1,2 is always clear
+          CreateDWordField(Arg3,4,CDW2)     //Table 6-147 from ACPI spec
+
+          Store(CDW2, OSCI)                 // Save DWord2
+          Or(OSCI, 0x4, OSCO)               // Only allow _PR3 support
+
+          If(LNotEqual(Arg1,One))
+          {
+            Or(CDW1,0x08,CDW1)            // Unknown revision
+          }
+
+          If(LNotEqual(OSCI, OSCO))
+          {
+            Or(CDW1,0x10,CDW1)            // Capabilities bits were masked
+          }
+
+          Store(OSCO, CDW2)                 // Replace DWord2
+          Return(Arg3)
+        } Else
+        {
+          Or(CDW1,4,CDW1)                   // Unrecognized UUID
+          Return(Arg3)
+        }
+      }// End _OSC
+    }
+  }//end of RTD3 condition
+
+
+  //USB RTD3 code
+  If(LEqual(RTD3,1))
+  {
+    Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR13)
+    {
+      Name(_PR0, Package() {\PR34})
+      Name(_PR3, Package() {\PR34})
+
+      Method(_S0W, 0)
+      {
+        If(And(\_SB.OSCO, 0x04))              // PMEs can be genrated from D3cold
+        {
+          Return(4)                         // OS comprehends D3cold, as described via \_SB._OSC
+        } Else
+        {
+          Return(3)
+        }
+      } // End _S0W
+    }
+
+    Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR14)
+    {
+      Name(_PR0, Package() {\PR34})
+      Name(_PR3, Package() {\PR34})
+
+      Method(_S0W, 0)
+      {
+        If(And(\_SB.OSCO, 0x04))
+        {
+          Return(4)
+        } Else
+        {
+          Return(3)
+        }
+      } // End _S0W
+    }
+
+
+    Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR15)
+    {
+      Name(_PR0, Package() {\PR56})
+      Name(_PR3, Package() {\PR56})
+
+      Method(_S0W, 0)
+      {
+        If(And(\_SB.OSCO, 0x04))
+        {
+          Return(4)
+        } Else
+        {
+          Return(3)
+        }
+      } // End _S0W
+    }
+
+    Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR16)
+    {
+      Name(_PR0, Package() {\PR56})
+      Name(_PR3, Package() {\PR56})
+
+      Method(_S0W, 0)
+      {
+        If(And(\_SB.OSCO, 0x04))
+        {
+          Return(4)
+        } Else
+        {
+          Return(3)
+        }
+      } // End _S0W
+    }
+
+    Scope(\_SB.PCI0.XHC1)                              // XHCI host only controller
+    {
+
+      Method(_PS0,0,Serialized)                      // set device into D0 state
+      {
+      }
+
+      Method(_PS3,0,Serialized)                      // place device into D3H state
+      {
+        //write to PMCSR
+      }
+
+      Method(_DSW, 3,Serialized)                     // enable or disable the device’s ability to wake a sleeping system.
+      {
+      }
+    }
+
+    Scope(\_SB.PCI0.XHC1.RHUB.HS01)
+    {
+
+    }
+
+    Scope(\_SB.PCI0.XHC1.RHUB.SSP1)
+    {
+
+    }
+
+    Scope(\_SB.PCI0.XHC2)                              // OTG
+    {
+
+      Method(_PS0,0,Serialized)                      // set device into D0 state
+      {
+      }
+
+      Method(_PS3,0,Serialized)                      // place device into D3H state
+      {
+        //write to PMCSR
+      }
+
+      Method(_DSW, 3,Serialized)                      // enable or disable the device’s ability to wake a sleeping system.
+      {
+      }
+    }
+
+    Scope(\_SB.PCI0.XHC2.RHUB.HS01)
+    {
+
+    }
+
+    Scope(\_SB.PCI0.XHC2.RHUB.SSP1)
+    {
+
+    }
+  } //If(LEqual(RTD3,1)) USB
+
+}//end of SSDT

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL

@@ -0,0 +1,138 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+// THERMAL.ASL represents a Thermal Zone to be used for testing on the
+// Customer Reference Boards.
+
+External(\_SB.DPTF.CTOK, MethodObj)
+
+Scope(\_TZ)
+{
+
+  // Thermal Zone 1 = DTS Thermal Zone.
+
+  ThermalZone(TZ01)
+  {
+    // Return the temperature at which the OS must perform a Critcal
+    // Shutdown.
+
+    Method(_CRT,0,Serialized)
+    {
+      Return(Add(2732,Multiply(CRTT,10)))
+    }
+
+    // Notifies ASL Code the current cooling mode.
+    //      0 - Active cooling
+    //      1 - Passive cooling
+
+    Method(_SCP,1,Serialized)
+    {
+      Store(Arg0,CTYP)
+    }
+
+    // _TMP (Temperature)
+    //
+    // Return the highest of the CPU temperatures to the OS.
+    //
+    // Arguments: (0)
+    //   None
+    // Return Value:
+    //   An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin)
+    //
+    Method(_TMP,0,Serialized)
+    {
+      If(DTSE)
+      {
+        If(LGreater(DTS2, DTS1))
+        {
+          Store(DTS2,Local0)
+        } else
+        {
+          Store(DTS1,Local0)
+        }
+        Return(Add(2732,Multiply(Local0,10)))
+        //
+        // Else return a static value if both EC and DTS are unavailable.
+        //
+      } Else
+      {
+        Return(3000) // (3000-2732)/10 = 26.8 degree C
+      }
+    }
+
+    // Return the Processor(s) used for Passive Cooling.
+
+    Method(_PSL,0,Serialized)
+    {
+      If(LEqual(MPEN, 4))
+      {
+        //  CMP - Throttling controls all four logical CPUs.
+        Return(Package() {\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3})
+      }
+
+      If(MPEN)
+      {
+        //  CMP - Throttling controls both CPUs.
+
+        Return(Package() {\_PR.CPU0,\_PR.CPU1})
+      }
+
+      Return(Package() {\_PR.CPU0})
+    }
+
+    // Returns the temperature at which the OS initiates CPU throttling.
+
+    Method(_PSV,0,Serialized)
+    {
+      Return(Add(2732,Multiply(PSVT,10)))
+    }
+
+    // Returns TC1 value used in the passive cooling formula.
+
+    Method(_TC1,0,Serialized)
+    {
+      Return(TC1V)
+    }
+
+    // Returns TC2 value used in the passive cooling formula.
+
+    Method(_TC2,0,Serialized)
+    {
+      Return(TC2V)
+    }
+
+    // Returns the sampling period used in the passive cooling formula.
+
+    Method(_TSP,0,Serialized)
+    {
+      Return(TSPV)
+    }
+
+    // Returns Hot Temperature
+
+    Method(_HOT,0,Serialized)
+    {
+      Subtract(CRTT, 5, Local0)
+      Return(Add(2732,Multiply(Local0,10)))
+    }
+  }
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl

@@ -0,0 +1,99 @@
+/************************************************************************************;
+;*                                                                                  *;
+;*                                                                                  *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail                      *;
+;*    Family of Customer Reference Boards.                                          *;
+;*                                                                                  *;
+;*    MPG-MSAE                                                                      *;
+;*                                                                                  *;
+;*    Copyright (c) 1999 - 2014, Intel Corporation.                                 *;
+;*                                                                                  *;
+;* This program and the accompanying materials are licensed and made available under*;
+;* the terms and conditions of the BSD License that accompanies this distribution.  *;
+;* The full text of the license may be found at                                     *;
+;* http://opensource.org/licenses/bsd-license.php.                                  *;
+;*                                                                                  *;
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            *;
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    *;
+;*                                                                                  *;
+;*                                                                                  *;
+;*    This program has been developed by Intel Corporation.                         *;
+;*    Licensee has Intel's permission to incorporate this source code               *;
+;*    into their product, royalty free.  This source code may NOT be                *;
+;*    redistributed to anyone without Intel's written permission.                   *;
+;*                                                                                  *;
+;*    Intel specifically disclaims all warranties, express or                       *;
+;*    implied, and all liability, including consequential and other                 *;
+;*    indirect damages, for the use of this code, including liability               *;
+;*    for infringement of any proprietary rights, and including the                 *;
+;*    warranties of merchantability and fitness for a particular                    *;
+;*    purpose.  Intel does not assume any responsibility for any                    *;
+;*    errors which may appear in this code nor any responsibility to                *;
+;*    update it.                                                                    *;
+;*                                                                                  *;
+;*    Version:  See README.TXT                                                      *;
+;*                                                                                  *;
+;************************************************************************************/
+
+//
+// _DSM : Device Specific Method supporting USB Sideband Deferring function
+//
+// Arg0: UUID Unique function identifier
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index
+// Arg3: Package Parameters
+//
+Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})
+{
+
+  If (LEqual(Arg0, ToUUID ("A5FC708F-8775-4BA6-BD0C-BA90A1EC72F8")))
+  {
+    //
+    // Switch by function index
+    //
+    Switch (ToInteger(Arg2))
+    {
+      //
+      // Standard query - A bitmask of functions supported
+      // Supports function 0-2
+      //
+      Case (0)
+      {
+        if (LEqual(Arg1, 1))   // test Arg1 for the revision
+        {
+          Return (Buffer () {0x07})
+        }
+        else
+        {
+          Return (Buffer () {0})
+        }
+      }
+      //
+      // USB Sideband Deferring Support
+      //   0: USB Sideband Deferring not supported on this device
+      //   1: USB Sideband Deferring supported
+      //
+      Case (1)
+      {
+        if (LEqual(SDGV,0xFF))   // check for valid GPE vector
+        {
+          Return (0)
+        }
+        else
+        {
+          Return (1)
+        }
+      }
+      //
+      // GPE Vector
+      //  Return the bit offset within the GPE block of the GPIO (HOST_ALERT) driven by this device
+      //
+      Case (2)
+      {
+        Return (SDGV)
+      }
+    }
+  }
+
+  Return (0)
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl

@@ -0,0 +1,40 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+
+
+
+// Brightness Notification:
+//              Generate a brightness related notification
+//      to the LFP if its populated.
+//
+//      Arguments:
+//              Arg0:   Notification value.
+//
+//      Return Value:
+//              None
+Method(BRTN,1,Serialized)
+{
+  If(LEqual(And(DIDX,0x0F00),0x400))
+  {
+    Notify(\_SB.PCI0.GFX0.DD1F,Arg0)
+  }
+}

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl

@@ -0,0 +1,45 @@
+/*++
+
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+  VLV.ASL
+
+Abstract:
+
+  Baytrail PCI configuration space definition.
+
+--*/
+Scope (\_SB.PCI0)
+{
+
+  Device(GFX0)   // Mobile I.G.D
+  {
+    Name(_ADR, 0x00020000)
+
+    Method(GDEP, 0)
+    {
+      If(LEqual(OSYS,2013))
+      {
+        Name(_DEP, Package(0x1)
+        {
+          PEPD
+        })
+      }
+    }
+
+    include("INTELGFX.ASL")
+    include("INTELISPDev2.ASL")
+  } // end "Mobile I.G.D"
+}//end scope

Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl

@@ -0,0 +1,45 @@
+/**************************************************************************;
+;*                                                                        *;
+;*                                                                        *;
+;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;
+;*    Family of Customer Reference Boards.                                *;
+;*                                                                        *;
+;*                                                                        *;
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
+;
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;*                                                                        *;
+;*                                                                        *;
+;**************************************************************************/
+
+Name(PMBS, 0x400)       // ASL alias for ACPI I/O base address.
+Name(SMIP, 0xb2)        // I/O port to trigger SMI
+Name(GPBS, 0x500)       // GPIO Register Block address
+Name(APCB, 0xfec00000)  // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled
+Name(APCL, 0x1000)      // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded
+Name(PFDR, 0xfed03034)  // PMC Function Disable Register
+Name(PMCB, 0xfed03000)  // PMC Base Address
+Name(PCLK, 0xfed03060)  // PMC Clock Control Register
+Name(PUNB, 0xfed05000)  // PUNIT Base Address
+Name(IBAS, 0xfed08000)  // ILB Base Address
+Name(SRCB, 0xfed1c000)  // RCBA (Root Complex Base Address)
+Name(SRCL, 0x1000)      // RCBA length
+Name(HPTB, 0xfed00000)  // Same as HPET_BASE_ADDRESS for ASL use
+Name(PEBS, 0xe0000000)  // PCIe Base
+Name(PELN, 0x10000000)  //
+Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code.
+Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code.
+Name(SDGV, 0x1c)        // UHCI Controller HOST_ALERT's bit offset within the GPE block. GPIO[0:15] corresponding to GPE[16:31]
+Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control
+Name(SHPC, 0x0) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control
+Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control
+Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control
+Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control
+