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Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

Browse Source 
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, 

which are for MinnowBoard MAX open source project.


Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
2015-01-12 09:37:20 +00:00
committed by zwei4
parent 6f785cfcc3
commit 3cbfba02fe
518 changed files with 118538 additions and 0 deletions
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33
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h Normal file
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/*++
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PowerManagementAcpiTableStorage.h
Abstract:
GUID definition for the Power Management ACPI table storage file name
--*/
#ifndef _POWER_MANAGEMENT_ACPI_TABLE_STORAGE_H_
#define _POWER_MANAGEMENT_ACPI_TABLE_STORAGE_H_
#define POWER_MANAGEMENT_ACPI_TABLE_STORAGE_GUID \
{ 0x161be597, 0xe9c5, 0x49db, 0xae, 0x50, 0xc4, 0x62, 0xab, 0x54, 0xee, 0xda }
extern EFI_GUID gPowerManagementAcpiTableStorageGuid;
#endif

110
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h Normal file
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/*++
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
VlvPolicy.h
Abstract:
Interface definition details between ValleyView MRC and platform drivers during PEI phase.
--*/
#ifndef _VLV_POLICY_PPI_H_
#define _VLV_POLICY_PPI_H_
//
// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}
//
#define VLV_POLICY_PPI_GUID \
{ \
0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \
}
//
// Extern the GUID for protocol users.
//
extern EFI_GUID gVlvPolicyPpiGuid;
//
// PPI revision number
// Any backwards compatible changes to this PPI will result in an update in the revision number
// Major changes will require publication of a new PPI
//
#define MRC_PLATFORM_POLICY_PPI_REVISION 1
#ifndef MAX_SOCKETS
#define MAX_SOCKETS 4
#endif
#define S3_TIMING_DATA_LEN 9
#define S3_READ_TRAINING_DATA_LEN 16
#define S3_WRITE_TRAINING_DATA_LEN 12
#ifndef S3_RESTORE_DATA_LEN
#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
#endif // S3_RESTORE_DATA_LEN
#pragma pack(1)
//
// MRC Platform Data Structure
//
typedef struct {
UINT8 SpdAddressTable[MAX_SOCKETS];
UINT8 TSonDimmSmbusAddress[MAX_SOCKETS];
UINT16 SmbusBar;
UINT32 IchRcba;
UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode)
UINT32 WdbRegionSize;
UINT32 SmBusAddress;
UINT8 UserBd;
UINT8 PlatformType;
UINT8 FastBoot;
UINT8 DynSR;
} VLV_PLATFORM_DATA;
typedef struct {
UINT16 MmioSize;
UINT16 GttSize;
UINT8 IgdDvmt50PreAlloc;
UINT8 PrimaryDisplay;
UINT8 PAVPMode;
UINT8 ApertureSize;
} GT_CONFIGURATION;
typedef struct {
UINT8 EccSupport;
UINT16 DdrFreqLimit;
UINT8 MaxTolud;
} MEMORY_CONFIGURATION;
//
// MRC Platform Policiy PPI
//
typedef struct _VLV_POLICY_PPI {
UINT8 Revision;
VLV_PLATFORM_DATA PlatformData;
GT_CONFIGURATION GtConfig;
MEMORY_CONFIGURATION MemConfig;
VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE
UINT8 ISPEn; //ISP (IUNIT) Device Enabled
UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS
} VLV_POLICY_PPI;
#pragma pack()
#endif // _VLV_POLICY_PPI_H_

138
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h Normal file
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/**
Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
/*++
Module Name:
PpmPlatformPolicy.h
Abstract:
Interface definition details between PPM and platform drivers during DXE phase.
--*/
#ifndef _PPM_PLATFORM_POLICY_H_
#define _PPM_PLATFORM_POLICY_H_
//
// PPM policy provided by platform for DXE phase {DDABFEAC-EF63-452c-8F39-ED7FAED8265E}
//
#define PPM_PLATFORM_POLICY_PROTOCOL_GUID \
{0xddabfeac, 0xef63, 0x452c, 0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}
//
// Extern the GUID for protocol users.
//
extern EFI_GUID gPpmPlatformPolicyProtocolGuid;
//
// Forward reference for ANSI C compatibility
//
typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL;
//
// Protocol revision number
// Any backwards compatible changes to this protocol will result in an update in the revision number
// Major changes will require publication of a new protocol
//
// Revision 1: Original version
// Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable
// Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn)
// Revision 4: Added support for extended C6 residency enabling
//
#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION 1
#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2 2
#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3 3
#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4 4
//
// Define maximum number of custom VID states supported
//
#ifndef MAX_CUSTOM_VID_TABLE_STATES
#define MAX_CUSTOM_VID_TABLE_STATES 6
#endif
//
// Custom VID table
//
typedef struct {
UINT8 VidNumber;
UINT32 VidCpuid;
UINT16 VidMaxRatio;
UINT16 VidMaxVid;
UINT16 StateRatio[MAX_CUSTOM_VID_TABLE_STATES];
UINT16 StateVid[MAX_CUSTOM_VID_TABLE_STATES];
} PPM_CUSTOM_VID_TABLE;
//
// PPM functional enables
//
typedef struct {
UINT8 EnableGv :1; // 0: Disabled; 1: Enabled
UINT8 EnableCx :1;
UINT8 EnableCxe :1;
UINT8 EnableC4 :1;
UINT8 EnableC6 :1;
UINT8 EnableC7 :1;
UINT8 EnableTm :1;
UINT8 Reserve00 :1;
UINT8 Reserve01 :1;
UINT8 EnableTurboMode :1;
UINT8 PowerLimit2 :1;
UINT8 EnableProcHot :1;
UINT8 Reserve02 :1;
UINT8 EnableCMP :1;
UINT8 TStatesEnable :1;
UINT8 Reserve03 :1;
UINT8 Reserve04 ;
} PPM_FUNCTION_ENABLES;
//
// PPM Turbo settings
//
typedef struct _PPM_TURBO_SETTINGS {
UINT16 PowerLimit1;
UINT32 PowerLimit1Time;
UINT16 PowerLimit2;
UINT8 TurboPowerLimitLock;
} PPM_TURBO_SETTINGS;
//
// Platform Policy
//
typedef struct _PPM_PLATFORM_POLICY_PROTOCOL {
UINT8 Revision;
PPM_FUNCTION_ENABLES FunctionEnables;
PPM_CUSTOM_VID_TABLE CustomVidTable;
PPM_TURBO_SETTINGS TurboSettings;
UINT8 Reserve00;
UINT8 Reserve01;
UINT8 Reserve02;
UINT8 Reserve03;
UINT8 Reserve04;
UINT8 Reserve05;
UINT8 Reserve06;
UINT8 S3RestoreMsrSwSmiNumber;
UINT8 Reserve07;
UINT32 Reserve08;
UINT8 Reserve09;
//
// Primary and Secondary Plane Current Limits
//
UINT16 Reserve10;
UINT8 Reserve11;
} PPM_PLATFORM_POLICY_PROTOCOL;
#endif

61
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h Normal file
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/*++
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
Types.h
Abstract:
This file include all the external data types.
--*/
#ifndef _TYPES_H_
#define _TYPES_H_
//
// Modifiers to abstract standard types to aid in debug of problems
//
#define CONST const
#define STATIC static
#define VOID void
#define VOLATILE volatile
//
// Constants. They may exist in other build structures, so #ifndef them.
//
#ifndef TRUE
#define TRUE ((BOOLEAN) 1 == 1)
#endif
#ifndef FALSE
#define FALSE ((BOOLEAN) 0 == 1)
#endif
#ifndef NULL
#define NULL ((VOID *) 0)
#endif
typedef UINT32 STATUS;
#define SUCCESS 0
#define FAILURE 0xFFFFFFFF
#ifndef MRC_DEADLOOP
#define MRC_DEADLOOP() while (TRUE)
#endif
#endif

45
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf Normal file
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#
#/*++
#
#Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#Module Name:
#
# PowerManagementAcpiTables.inf
#
#Abstract:
#
# Component description file for the ACPI tables
#
#--*/
[defines]
INF_VERSION = 0x00010005
BASE_NAME = PowerManagementAcpiTables2
FILE_GUID = 161BE597-E9C5-49DB-AE50-C462AB54EEDA
MODULE_TYPE = USER_DEFINED
VERSION_STRING = 1.0
EDK_RELEASE_VERSION = 0x00020000
EFI_SPECIFICATION_VERSION = 0x00020000
[sources.common]
Ssdt/Cpu0Cst.asl
Ssdt/Cpu0Ist.asl
Ssdt/Cpu0Tst.asl
Ssdt/ApCst.asl
Ssdt/ApIst.asl
Ssdt/ApTst.asl
Ssdt/CpuPm.asl
[Packages]
MdePkg/MdePkg.dec

116
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl Normal file
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/*-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
Intel Silvermont Processor Power Management BIOS Reference Code
Copyright (c) 2006 - 2014, Intel Corporation
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Filename: CPU1CST.ASL
Revision: Refer to Readme
Date: Refer to Readme
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
This Processor Power Management BIOS Source Code is furnished under license
and may only be used or copied in accordance with the terms of the license.
The information in this document is furnished for informational use only, is
subject to change without notice, and should not be construed as a commitment
by Intel Corporation. Intel Corporation assumes no responsibility or liability
for any errors or inaccuracies that may appear in this document or any
software that may be provided in association with this document.
Except as permitted by such license, no part of this document may be
reproduced, stored in a retrieval system, or transmitted in any form or by
any means without the express written consent of Intel Corporation.
WARNING: You are authorized and licensed to install and use this BIOS code
ONLY on an IST PC. This utility may damage any system that does not
meet these requirements.
An IST PC is a computer which
(1) Is capable of seamlessly and automatically transitioning among
multiple performance states (potentially operating at different
efficiency ratings) based upon power source changes, END user
preference, processor performance demand, and thermal conditions; and
(2) Includes an Intel Pentium II processors, Intel Pentium III
processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
Processor-M, Intel Pentium M Processor, or any other future Intel
processors that incorporates the capability to transition between
different performance states by altering some, or any combination of,
the following processor attributes: core voltage, core frequency, bus
frequency, number of processor cores available, or any other attribute
that changes the efficiency (instructions/unit time-power) at which the
processor operates.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
NOTES:
(1) <TODO> - IF the trap range and port definitions do not match those
specified by this reference code, this file must be modified IAW the
individual implmentation.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
DefinitionBlock (
"APCST.aml",
"SSDT",
1,
"PmRef",
"ApCst",
0x3000
)
{
External(\_PR.CPU1, DeviceObj)
External(\_PR.CPU2, DeviceObj)
External(\_PR.CPU3, DeviceObj)
External(\_PR.CPU0._CST)
Scope(\_PR.CPU1)
{
Method(_CST,0)
{
//
// Return P0's _CST object.
//
Return(\_PR.CPU0._CST)
}
}
Scope(\_PR.CPU2)
{
Method(_CST,0)
{
//
// Return P0's _CST object.
//
Return(\_PR.CPU0._CST)
}
}
Scope(\_PR.CPU3)
{
Method(_CST,0)
{
//
// Return P0's _CST object.
//
Return(\_PR.CPU0._CST)
}
}
} // End of Definition Block

172
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl Normal file
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/*-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
Intel Silvermont Processor Power Management BIOS Reference Code
Copyright (c) 2006 - 2014, Intel Corporation
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Filename: APIST.ASL
Revision: Refer to Readme
Date: Refer to Readme
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
This Processor Power Management BIOS Source Code is furnished under license
and may only be used or copied in accordance with the terms of the license.
The information in this document is furnished for informational use only, is
subject to change without notice, and should not be construed as a commitment
by Intel Corporation. Intel Corporation assumes no responsibility or liability
for any errors or inaccuracies that may appear in this document or any
software that may be provided in association with this document.
Except as permitted by such license, no part of this document may be
reproduced, stored in a retrieval system, or transmitted in any form or by
any means without the express written consent of Intel Corporation.
WARNING: You are authorized and licensed to install and use this BIOS code
ONLY on an IST PC. This utility may damage any system that does not
meet these requirements.
An IST PC is a computer which
(1) Is capable of seamlessly and automatically transitioning among
multiple performance states (potentially operating at different
efficiency ratings) based upon power source changes, END user
preference, processor performance demand, and thermal conditions; and
(2) Includes an Intel Pentium II processors, Intel Pentium III
processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
Processor-M, Intel Pentium M Processor, or any other future Intel
processors that incorporates the capability to transition between
different performance states by altering some, or any combination of,
the following processor attributes: core voltage, core frequency, bus
frequency, number of processor cores available, or any other attribute
that changes the efficiency (instructions/unit time-power) at which the
processor operates.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
NOTES:
(1) <TODO> - IF the trap range and port definitions do not match those
specified by this reference code, this file must be modified IAW the
individual implmentation.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
DefinitionBlock (
"APIST.aml",
"SSDT",
1,
"PmRef",
"ApIst",
0x3000
)
{
External(\_PR.CPU0._PSS, MethodObj)
External(\_PR.CPU0._PCT, MethodObj)
External(\_PR.CPU0._PPC, IntObj)
External(\_PR.CPU0._PSD, MethodObj)
External(\_PR.CPU1, DeviceObj)
External(\_PR.CPU2, DeviceObj)
External(\_PR.CPU3, DeviceObj)
External (CFGD)
External (PDC0)
Scope(\_PR.CPU1)
{
Method(_PPC,0)
{
Return(\_PR.CPU0._PPC) // Return P0 _PPC value.
}
Method(_PCT,0)
{
Return(\_PR.CPU0._PCT) // Return P0 _PCT.
}
Method(_PSS,0)
{
//Return the same table as CPU0 for CMP cases.
Return(\_PR.CPU0._PSS)
}
// The _PSD object provides information to the OSPM related
// to P-State coordination between processors in a multi-processor
// configurations.
//
Method(_PSD,0)
{
Return(\_PR.CPU0._PSD) // Return P0 _PSD.
}
}
Scope(\_PR.CPU2)
{
Method(_PPC,0)
{
Return(\_PR.CPU0._PPC) // Return P0 _PPC value.
}
Method(_PCT,0)
{
Return(\_PR.CPU0._PCT) // Return P0 _PCT.
}
Method(_PSS,0)
{
//Return the same table as CPU0 for CMP cases.
Return(\_PR.CPU0._PSS)
}
// The _PSD object provides information to the OSPM related
// to P-State coordination between processors in a multi-processor
// configurations.
//
Method(_PSD,0)
{
Return(\_PR.CPU0._PSD) // Return P0 _PSD.
}
}
Scope(\_PR.CPU3)
{
Method(_PPC,0)
{
Return(\_PR.CPU0._PPC) // Return P0 _PPC value.
}
Method(_PCT,0)
{
Return(\_PR.CPU0._PCT) // Return P0 _PCT.
}
Method(_PSS,0)
{
//Return the same table as CPU0 for CMP cases.
Return(\_PR.CPU0._PSS)
}
// The _PSD object provides information to the OSPM related
// to P-State coordination between processors in a multi-processor
// configurations.
//
Method(_PSD,0)
{
Return(\_PR.CPU0._PSD) // Return P0 _PSD.
}
}
} // End of Definition Block

268
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl Normal file
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/*-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
Intel Platform Processor Power Management BIOS Reference Code
Copyright (c) 2007 - 2014, Intel Corporation
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Filename: APTST.ASL
Revision: Refer to Readme
Date: Refer to Readme
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
This Processor Power Management BIOS Source Code is furnished under license
and may only be used or copied in accordance with the terms of the license.
The information in this document is furnished for informational use only, is
subject to change without notice, and should not be construed as a commitment
by Intel Corporation. Intel Corporation assumes no responsibility or liability
for any errors or inaccuracies that may appear in this document or any
software that may be provided in association with this document.
Except as permitted by such license, no part of this document may be
reproduced, stored in a retrieval system, or transmitted in any form or by
any means without the express written consent of Intel Corporation.
WARNING: You are authorized and licensed to install and use this BIOS code
ONLY on an IST PC. This utility may damage any system that does not
meet these requirements.
An IST PC is a computer which
(1) Is capable of seamlessly and automatically transitioning among
multiple performance states (potentially operating at different
efficiency ratings) based upon power source changes, END user
preference, processor performance demand, and thermal conditions; and
(2) Includes an Intel Pentium II processors, Intel Pentium III
processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
Processor-M, Intel Pentium M Processor, or any other future Intel
processors that incorporates the capability to transition between
different performance states by altering some, or any combination of,
the following processor attributes: core voltage, core frequency, bus
frequency, number of processor cores available, or any other attribute
that changes the efficiency (instructions/unit time-power) at which the
processor operates.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
NOTES:
(1) <TODO> - IF the trap range and port definitions do not match those
specified by this reference code, this file must be modified IAW the
individual implmentation.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
DefinitionBlock(
"APTST.aml",
"SSDT",
0x01,
"PmRef",
"ApTst",
0x3000
)
{
External(\_PR.CPU1, DeviceObj)
External(\_PR.CPU2, DeviceObj)
External(\_PR.CPU3, DeviceObj)
External(\_PR.CPU0._PTC)
External(\_PR.CPU0._TSS)
External(PDC0)
External(CFGD)
External(MPEN)
Scope(\_PR.CPU1)
{
Name(_TPC, 0) // All T-States are available
//
// T-State Control/Status interface
//
Method(_PTC, 0)
{
Return(\_PR.CPU0._PTC)
}
Method(_TSS, 0)
{
Return(\_PR.CPU0._TSS)
}
//
// T-State Dependency
//
Method(_TSD, 0)
{
//
// IF four cores are supported/enabled && !(direct access to MSR)
// Report 4 processors and SW_ANY as the coordination
// IF two cores are supported/enabled && !(direct access to MSR)
// Report 2 processors and SW_ANY as the coordination type
// ELSE
// Report 1 processor and SW_ALL as the coordination type (domain 1)
//
// CFGD[23] = Four cores enabled
// CFGD[24] = Two or more cores enabled
// PDCx[2] = OSPM is capable of direct access to On
// Demand throttling MSR
//
If(LNot(And(PDC0,4)))
{
Return(Package(){ // SW_ANY
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFD, // Coord Type- SW_ANY
MPEN // # processors.
}
})
}
Return(Package(){ // SW_ALL
Package(){
5, // # entries.
0, // Revision.
1, // Domain #.
0xFC, // Coord Type- SW_ALL
1 // # processors.
}
})
}
} // End of CPU1
Scope(\_PR.CPU2)
{
Name(_TPC, 0) // All T-States are available
//
// T-State Control/Status interface
//
Method(_PTC, 0)
{
Return(\_PR.CPU0._PTC)
}
Method(_TSS, 0)
{
Return(\_PR.CPU0._TSS)
}
//
// T-State Dependency
//
Method(_TSD, 0)
{
//
// IF four cores are supported/enabled && !(direct access to MSR)
// Report 4 processors and SW_ANY as the coordination
// IF two cores are supported/enabled && !(direct access to MSR)
// Report 2 processors and SW_ANY as the coordination type
// ELSE
// Report 1 processor and SW_ALL as the coordination type (domain 1)
//
// CFGD[23] = Four cores enabled
// CFGD[24] = Two or more cores enabled
// PDCx[2] = OSPM is capable of direct access to On
// Demand throttling MSR
//
If(LNot(And(PDC0,4)))
{
Return(Package(){ // SW_ANY
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFD, // Coord Type- SW_ANY
MPEN // # processors.
}
})
}
Return(Package(){ // SW_ALL
Package(){
5, // # entries.
0, // Revision.
1, // Domain #.
0xFC, // Coord Type- SW_ALL
1 // # processors.
}
})
}
} // End of CPU2
Scope(\_PR.CPU3)
{
Name(_TPC, 0) // All T-States are available
//
// T-State Control/Status interface
//
Method(_PTC, 0)
{
Return(\_PR.CPU0._PTC)
}
Method(_TSS, 0)
{
Return(\_PR.CPU0._TSS)
}
//
// T-State Dependency
//
Method(_TSD, 0)
{
//
// IF four cores are supported/enabled && !(direct access to MSR)
// Report 4 processors and SW_ANY as the coordination
// IF two cores are supported/enabled && !(direct access to MSR)
// Report 2 processors and SW_ANY as the coordination type
// ELSE
// Report 1 processor and SW_ALL as the coordination type (domain 1)
//
// CFGD[23] = Four cores enabled
// CFGD[24] = Two or more cores enabled
// PDCx[2] = OSPM is capable of direct access to On
// Demand throttling MSR
//
If(LNot(And(PDC0,4)))
{
Return(Package(){ // SW_ANY
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFD, // Coord Type- SW_ANY
MPEN // # processors.
}
})
}
Return(Package(){ // SW_ALL
Package(){
5, // # entries.
0, // Revision.
1, // Domain #.
0xFC, // Coord Type- SW_ALL
1 // # processors.
}
})
}
} // End of CPU3
} // End of Definition Block

280
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/*-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
Intel Silvermont Processor Power Management BIOS Reference Code
Copyright (c) 2006 - 2014, Intel Corporation
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Filename: CPU0CST.ASL
Revision: Refer to Readme
Date: Refer to Readme
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
This Processor Power Management BIOS Source Code is furnished under license
and may only be used or copied in accordance with the terms of the license.
The information in this document is furnished for informational use only, is
subject to change without notice, and should not be construed as a commitment
by Intel Corporation. Intel Corporation assumes no responsibility or liability
for any errors or inaccuracies that may appear in this document or any
software that may be provided in association with this document.
Except as permitted by such license, no part of this document may be
reproduced, stored in a retrieval system, or transmitted in any form or by
any means without the express written consent of Intel Corporation.
WARNING: You are authorized and licensed to install and use this BIOS code
ONLY on an IST PC. This utility may damage any system that does not
meet these requirements.
An IST PC is a computer which
(1) Is capable of seamlessly and automatically transitioning among
multiple performance states (potentially operating at different
efficiency ratings) based upon power source changes, END user
preference, processor performance demand, and thermal conditions; and
(2) Includes an Intel Pentium II processors, Intel Pentium III
processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
Processor-M, Intel Pentium M Processor, or any other future Intel
processors that incorporates the capability to transition between
different performance states by altering some, or any combination of,
the following processor attributes: core voltage, core frequency, bus
frequency, number of processor cores available, or any other attribute
that changes the efficiency (instructions/unit time-power) at which the
processor operates.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
NOTES:
(1) <TODO> - IF the trap range and port definitions do not match those
specified by this reference code, this file must be modified IAW the
individual implmentation.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
DefinitionBlock (
"CPU0CST.aml",
"SSDT",
1,
"PmRef",
"Cpu0Cst",
0x3001
)
{
External(\_PR.CPU0, DeviceObj)
External(PWRS)
External(CFGD)
External(PDC0)
Scope(\_PR.CPU0)
{
OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG
Field (DEB0, ByteAcc,NoLock,Preserve) //DBG
{ DBG8, 8,} //DBG
Method (_CST, 0)
{
Store(0x60,DBG8) //DBG
// IF CMP is supported, but independent C-States beyond C1 are
// not supported; return C1 Halt and rely on BIOS based software
// coordination
//
// CFGD[24] = CMP support
// PDCx[4] = 0 - OS does not support ind. C2/C3 in MP systems
//
// Note: SMI will be generated when both processor enter the
// Halt state.
//
If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))
{
Store(0x61,DBG8) //DBG
Return(Package() {
1,
Package()
{ // C1 halt, but with BIOS coordination
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
1,
157,
1000
}
})
}
// IF MWAIT extensions are supported, use them.
//
// IF C6 capable/enabled AND Battery
// Report MWAIT C1, C2, C6 w/ BM_STS avoidance
// ELSE IF C4 capable/enabled AND Battery
// Report MWAIT C1, C2, C4 w/ BM_STS avoidance
// ELSE IF C3 capable/enabled
// Report MWAIT C1, C2, C3 w/ BM_STS avoidance
// ELSE IF C2 capable/enabled
// Report MWAIT C1, C2
// ELSE
// Report MWAIT C1
//
// CFGD[21] = 1 - MWAIT extensions supported
// CFGD[13] = 1 - C7 Capable/Enabled
// CFGD[12] = 1 - C6S Capable/Enabled
// CFGD[11] = 1 - C6 Capable/Enabled
// CFGD[7] = 1 - C4 Capable/Enabled
// CFGD[5] = 1 - C3 Capable/Enabled
// PDCx[9] = 1 - OS supports MWAIT extensions
// PDCx[8] = 1 - OS supports MWAIT for C1
// (Inferred from PDCx[9] = 1.)
// PDCx[4] = 1 - OS supports independent C2/C3 in MP systems
// or
// NOT CMP (Inferred from previous check.)
//
If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))
{
//
// <TODO> The implementor may wish to only report C1-C2
// when on AC power. In this case, the IF clause below can
// be modified to something like:
//
// "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"
//
// Which uses the power state of the system (PWRS) to
// determine whether to allow deepers states.
//
// IF C7 supported AND on battery
// report MWAIT C1, C6, C7
//
// CFGD[13] = C7 Capable/Enabled
// CFGD[11] = C6 Capable/Enabled
//
If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))
{
Store(0x77,DBG8) //DBG
Return( Package()
{
3,
Package()
{ // C1, MWAIT
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{
// C6, MWAIT Extension with Incremental L2 Shrink
// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
// C6, MWAIT Extension with No L2 Shrink
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
2,
500,
10
},
Package()
{
// C7, MWAIT Extension with Full L2 Shrink
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},
3,
1500, //PnP setting, 1.5 ms for worst-case exit latency
10
}
})
}
If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))
{
Store(0x67,DBG8) //DBG
Return( Package()
{
3,
Package()
{ // C1, MWAIT
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{
// C6, MWAIT Extension with Incremental L2 Shrink
// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
// C6 = C6NS, MWAIT Extension with No L2 Shrink
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
2,
500,
10
},
Package()
{
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},
3,
1500, //PnP setting, 1.5 ms for worst-case exit latency
10
}
})
}
If(And(CFGD,0x800)) // Setup Max C-State = C6
{
Store(0x76,DBG8) //DBG
Return( Package()
{
2,
Package()
{ // C1, MWAIT
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
},
Package()
{
// C6, MWAIT Extension with Incremental L2 Shrink
// ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},
// C6, MWAIT Extension with No L2 Shrink
ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},
2,
500,
10
}
})
}
//
// IF no deeper C-States are supported; report MWAIT C1.
//
Store(0x71,DBG8) //DBG
Return(Package()
{
1,
Package()
{ // C1, MWAIT
ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},
1,
1,
1000
}
})
}
}
}
}

266
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View File

@@ -0,0 +1,266 @@
/*-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
Intel Silvermont Processor Power Management BIOS Reference Code
Copyright (c) 2006 - 2014, Intel Corporation
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Filename: CPU0IST.ASL
Revision: Refer to Readme
Date: Refer to Readme
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
This Processor Power Management BIOS Source Code is furnished under license
and may only be used or copied in accordance with the terms of the license.
The information in this document is furnished for informational use only, is
subject to change without notice, and should not be construed as a commitment
by Intel Corporation. Intel Corporation assumes no responsibility or liability
for any errors or inaccuracies that may appear in this document or any
software that may be provided in association with this document.
Except as permitted by such license, no part of this document may be
reproduced, stored in a retrieval system, or transmitted in any form or by
any means without the express written consent of Intel Corporation.
WARNING: You are authorized and licensed to install and use this BIOS code
ONLY on an IST PC. This utility may damage any system that does not
meet these requirements.
An IST PC is a computer which
(1) Is capable of seamlessly and automatically transitioning among
multiple performance states (potentially operating at different
efficiency ratings) based upon power source changes, END user
preference, processor performance demand, and thermal conditions; and
(2) Includes an Intel Pentium II processors, Intel Pentium III
processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
Processor-M, Intel Pentium M Processor, or any other future Intel
processors that incorporates the capability to transition between
different performance states by altering some, or any combination of,
the following processor attributes: core voltage, core frequency, bus
frequency, number of processor cores available, or any other attribute
that changes the efficiency (instructions/unit time-power) at which the
processor operates.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
NOTES:
(1) <TODO> - IF the trap range and port definitions do not match those
specified by this reference code, this file must be modified IAW the
individual implmentation.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
DefinitionBlock (
"CPU0IST.aml",
"SSDT",
0x01,
"PmRef",
"Cpu0Ist",
0x3000
)
{
External (\_PR.CPU0, DeviceObj)
External (PDC0)
External (CFGD)
Scope(\_PR.CPU0)
{
//OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG
//Field (DEB0, ByteAcc,NoLock,Preserve) //DBG
//{ DBG8, 8,} //DBG
Name(_PPC, 0) // Initialize as All States Available.
// NOTE: For CMP systems; this table is not loaded unless
// the required driver support is present.
// So, we do not check for those cases here.
//
// CFGD[0] = GV3 Capable/Enabled
// PDCx[0] = OS Capable of Hardware P-State control
//
Method(_PCT,0)
{
If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))
{
//Store(0xA0,DBG8) //DBG
Return(Package() // Native Mode
{
ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
})
}
// @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT
// For all other cases, report control through the
// SMI interface. (The port used for SMM control is fixed up
// by the initialization code.)
//
Return(Package() // SMM Mode
{
ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
})
}
// NOTE: For CMP systems; this table is not loaded if MP
// driver support is not present or P-State are disabled.
//
Method(_PSS,0)
{
//
// Report NSPP if:
// (1) GV3 capable (Not checked, see above.)
// (2) Driver support direct hardware control
// (3) MP driver support present (Not checked, see above.)
// else;
// Report SPSS
//
// PDCx[0] = OS Capable of Hardware P-State control
//
If(And(PDC0,0x0001)){
//Store(0xB0,DBG8) //DBG
Return(NPSS)
}
//Store(0xBF,DBG8) //DBG
// Otherwise, report SMM mode
//
Return(SPSS)
}
Name(SPSS,Package()
{
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
})
Name(NPSS,Package()
{
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
})
// The _PSD object provides information to the OSPM related
// to P-State coordination between processors in a multi-processor
// configurations.
//
Method(_PSD,0)
{
//
// IF CMP is supported/enabled
// IF quad core processor
// IF PDC[11]
// Report 4 processors and HW_ALL as the coordination type
// ELSE
// Report 4 processors and SW_ALL as the coordination type
// ELSE
// IF PDC[11]
// Report 2 processors and HW_ALL as the coordination type
// ELSE
// Report 2 processors and SW_ALL as the coordination type
// ELSE
// Report 1 processor and SW_ALL as the coordination type
// (Domain 0)
//
// CFGD[24] = Two or more cores enabled
// CFGD[23] = Four cores enabled
// PDCx[11] = Hardware coordination with hardware feedback
//
If(And(CFGD,0x1000000)) // CMP Enabled.
{
If(And(CFGD,0x800000)) // 2 or 4 process.
{
If(And(PDC0,0x0800))
{
Return(Package(){ // HW_ALL
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFE, // Coord Type- HW_ALL.
4 // # processors.
}
})
} // If(And(PDC0,0x0800))
Return(Package(){ // SW_ALL
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFC, // Coord Type- SW_ALL.
4 // # processors.
}
})
} else {
Return(Package(){ // HW_ALL
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFE, // Coord Type- HW_ALL.
2 // # processors.
}
})
}
} // If(And(CFGD,0x1000000)) // CMP Enabled.
Return(Package(){ // SW_ALL
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFC, // Coord Type- SW_ALL.
1 // # processors.
}
})
} // Method(_PSD,0)
} // Scope(\_PR.CPU0)
} // End of Definition Block

241
Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl Normal file
View File

@@ -0,0 +1,241 @@
/*-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
Intel Silvermont Processor Power Management BIOS Reference Code
Copyright (c) 2006 - 2014, Intel Corporation
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Filename: CPU0TST.ASL
Revision: Refer to Readme
Date: Refer to Readme
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
This Processor Power Management BIOS Source Code is furnished under license
and may only be used or copied in accordance with the terms of the license.
The information in this document is furnished for informational use only, is
subject to change without notice, and should not be construed as a commitment
by Intel Corporation. Intel Corporation assumes no responsibility or liability
for any errors or inaccuracies that may appear in this document or any
software that may be provided in association with this document.
Except as permitted by such license, no part of this document may be
reproduced, stored in a retrieval system, or transmitted in any form or by
any means without the express written consent of Intel Corporation.
WARNING: You are authorized and licensed to install and use this BIOS code
ONLY on an IST PC. This utility may damage any system that does not
meet these requirements.
An IST PC is a computer which
(1) Is capable of seamlessly and automatically transitioning among
multiple performance states (potentially operating at different
efficiency ratings) based upon power source changes, end user
preference, processor performance demand, and thermal conditions; and
(2) Includes an Intel Pentium II processors, Intel Pentium III
processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
Processor-M, Intel Pentium M Processor, or any other future Intel
processors that incorporates the capability to transition between
different performance states by altering some, or any combination of,
the following processor attributes: core voltage, core frequency, bus
frequency, number of processor cores available, or any other attribute
that changes the efficiency (instructions/unit time-power) at which the
processor operates.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
NOTES:
(1) <TODO> - IF the trap range and port definitions do not match those
specified by this reference code, this file must be modified IAW the
individual implmentation.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
DefinitionBlock(
"CPU0TST.aml",
"SSDT",
0x01,
"PmRef",
"Cpu0Tst",
0x3000
)
{
External(\_PR.CPU0, DeviceObj)
External(PDC0)
External(CFGD)
External(_PSS)
Scope(\_PR.CPU0)
{
Name(_TPC, 0) // All T-States are available
//
// T-State Control/Status interface
//
Method(_PTC, 0)
{
//
// IF OSPM is capable of direct access to MSR
// Report MSR interface
// ELSE
// Report I/O interface
//
// PDCx[2] = OSPM is capable of direct access to On
// Demand throttling MSR
//
If(And(PDC0, 0x0004)) {
Return(Package() {
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
})
}
}
// _TSS package for I/O port based T-State control
// "Power" fields are replaced with real values by the first
// call of _TSS method.
//
Name(TSSI, Package() {
Package(){100, 1000, 0, 0x00, 0},
Package(){ 88, 875, 0, 0x0F, 0},
Package(){ 75, 750, 0, 0x0E, 0},
Package(){ 63, 625, 0, 0x0D, 0},
Package(){ 50, 500, 0, 0x0C, 0},
Package(){ 38, 375, 0, 0x0B, 0},
Package(){ 25, 250, 0, 0x0A, 0},
Package(){ 13, 125, 0, 0x09, 0}
})
// _TSS package for MSR based T-State control
// "Power" fields are replaced with real values by the first
// call of _TSS method.
//
Name(TSSM, Package() {
Package(){100, 1000, 0, 0x00, 0},
Package(){ 88, 875, 0, 0x1E, 0},
Package(){ 75, 750, 0, 0x1C, 0},
Package(){ 63, 625, 0, 0x1A, 0},
Package(){ 50, 500, 0, 0x18, 0},
Package(){ 38, 375, 0, 0x16, 0},
Package(){ 25, 250, 0, 0x14, 0},
Package(){ 13, 125, 0, 0x12, 0}
})
Name(TSSF, 0) // Flag for TSSI/TSSM initialization
Method(_TSS, 0)
{
// Update "Power" fields of TSSI/TSSM with the LFM
// power data IF _PSS is available
//
IF (LAnd(LNot(TSSF),CondRefOf(_PSS)))
{
Store(_PSS, Local0)
Store(SizeOf(Local0), Local1) // _PSS size
Decrement(Local1) // Index of LFM
Store(DerefOf(Index(DerefOf(Index(Local0,Local1)),1)), Local2) // LFM Power
Store(0, Local3)
While(LLess(Local3, SizeOf(TSSI)))
{
Store(Divide(Multiply(Local2, Subtract(8, Local3)), 8),
Local4) // Power for this TSSI/TSSM entry
Store(Local4,Index(DerefOf(Index(TSSI,Local3)),1))
Store(Local4,Index(DerefOf(Index(TSSM,Local3)),1))
Increment(Local3)
}
Store(Ones, TSSF) // TSSI/TSSM are updated
}
//
// IF OSPM is capable of direct access to MSR
// Report TSSM
// ELSE
// Report TSSI
//
If(And(PDC0, 0x0004))
{
Return(TSSM)
}
Return(TSSI)
}
Method(_TDL, 0)
{
Store ("Cpu0: _TDL Called", Debug)
Name ( LFMI, 0)
Store (SizeOf(TSSM), LFMI)
Decrement(LFMI) // Index of LFM entry in TSSM
Return(LFMI)
}
//
// T-State Dependency
//
Method(_TSD, 0)
{
//
// IF four cores are supported/enabled && !(direct access to MSR)
// Report 4 processors and SW_ANY as the coordination type
// ELSE IF two cores are supported/enabled && !(direct access to MSR)
// Report 2 processors and SW_ANY as the coordination type
// ELSE
// Report 1 processor and SW_ALL as the coordination type
//
// CFGD[23] = Four cores enabled
// CFGD[24] = Two or more cores enabled
// PDCx[2] = OSPM is capable of direct access to On
// Demand throttling MSR
//
If(LAnd(And(CFGD,0x0800000),LNot(And(PDC0,4))))
{
Return(Package(){ // SW_ANY
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFD, // Coord Type- SW_ANY
4 // # processors.
}
})
}
If(LAnd(And(CFGD,0x1000000),LNot(And(PDC0,4))))
{
Return(Package(){ // SW_ANY
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFD, // Coord Type- SW_ANY
2 // # processors.
}
})
}
Return(Package(){ // SW_ALL
Package(){
5, // # entries.
0, // Revision.
0, // Domain #.
0xFC, // Coord Type- SW_ALL
1 // # processors.
}
})
}
}
} // End of Definition Block

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/*-----------------------------------------------------------------------------
Intel Silvermont Processor Power Management BIOS Reference Code
Copyright (c) 2006 - 2014, Intel Corporation
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Filename: CPUPM.ASL
Revision: Refer to Readme
Date: Refer to Readme
-------------------------------------------------------------------------------
This Processor Power Management BIOS Source Code is furnished under license
and may only be used or copied in accordance with the terms of the license.
The information in this document is furnished for informational use only, is
subject to change without notice, and should not be construed as a commitment
by Intel Corporation. Intel Corporation assumes no responsibility or liability
for any errors or inaccuracies that may appear in this document or any
software that may be provided in association with this document.
Except as permitted by such license, no part of this document may be
reproduced, stored in a retrieval system, or transmitted in any form or by
any means without the express written consent of Intel Corporation.
WARNING: You are authorized and licensed to install and use this BIOS code
ONLY on an IST PC. This utility may damage any system that does not
meet these requirements.
An IST PC is a computer which
(1) Is capable of seamlessly and automatically transitioning among
multiple performance states (potentially operating at different
efficiency ratings) based upon power source changes, END user
preference, processor performance demand, and thermal conditions; and
(2) Includes an Intel Pentium II processors, Intel Pentium III
processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
Processor-M, Intel Pentium M Processor, or any other future Intel
processors that incorporates the capability to transition between
different performance states by altering some, or any combination of,
the following processor attributes: core voltage, core frequency, bus
frequency, number of processor cores available, or any other attribute
that changes the efficiency (instructions/unit time-power) at which the
processor operates.
-------------------------------------------------------------------------------
NOTES:
(1) <TODO> - Except for the SSDT package, the objects in this ASL code
may be moved to the DSDT. It is kept separate in this reference package
for ease of distribution only.
------------------------------------------------------------------------------*/
DefinitionBlock (
"CPUPM.aml",
"SSDT",
0x01,
"PmRef",
"CpuPm",
0x3000
)
{
External(\_PR.CPU0, DeviceObj)
External(\_PR.CPU1, DeviceObj)
External(\_PR.CPU2, DeviceObj)
External(\_PR.CPU3, DeviceObj)
External(SMIF)
Scope(\)
{
// Package of pointers to SSDT's
//
// First column is SSDT name, used for debug only.
// (First column must be EXACTLY eight characters.)
// Second column is physical address.
// Third column is table length.
//
// IF modifying this file, see warnings listed in ppminit.asm.
//
Name(SSDT,Package()
{
"CPU0IST ", 0x80000000, 0x80000000,
"APIST ", 0x80000000, 0x80000000,
"CPU0CST ", 0x80000000, 0x80000000,
"APCST ", 0x80000000, 0x80000000
})
//
// Note: See PpmBiosInit in PPMINIT.ASM for a definition of
// the PpmFlags mirrored in CFGD.
//
Name(CFGD, 0x80000000)
Name(\PDC0,0x80000000) // CPU0 _PDC Flags.
Name(\PDC1,0x80000000) // CPU1 _PDC Flags.
Name(\PDC2,0x80000000) // CPU2 _PDC Flags.
Name(\PDC3,0x80000000) // CPU3 _PDC Flags.
Name(\SDTL,0x00) // Loaded SSDT Flags.
}
Scope(\_PR.CPU0)
{
//
// Define handles for opregions (used by load.)
//
Name(HI0,0) // Handle to CPU0IST
Name(HC0,0) // Handle to CPU0CST
Method(_PDC,1)
{
//
// Check and extract the _PDC information.
//
Store(CPDC(Arg0), Local0)
//
// Save the capability information and load tables as needed.
//
GCAP(Local0)
//
// Return status.
//
//Return (Local0)
}
Method(_OSC, 4)
{
//
// Check and extract the _OSC information.
//
Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)
//
// Save the capability information and load tables as needed.
//
GCAP(Local0)
//
// Return status.
//
Return (Local0)
}
//
// Implement a generic Method to check _PDC information which may be called
// by any of the processor scopes. (The use of _PDC is deprecated in ACPI 3.
// in favor of _OSC. However, for backwards compatibility, _PDC may be
// implemented using _OSC as follows:)
//
Method(CPDC,1)
{
CreateDwordField (Arg0, 0, REVS)
CreateDwordField (Arg0, 4, SIZE)
//
// Local0 = Number of bytes for Arg0
//
Store (SizeOf (Arg0), Local0)
//
// Local1 = Number of Capabilities bytes in Arg0
//
Store (Subtract (Local0, 8), Local1)
//
// TEMP = Temporary field holding Capability DWORDs
//
CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)
//
// Create the Status (STAT) buffer with the first DWORD = 0
// This is required as per ACPI 3.0 Spec which says the
// first DWORD is used to return errors defined by _OSC.
//
Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})
//
// Concatenate the _PDC capabilities bytes to the STS0 Buffer
// and store them in a local variable for calling OSC
//
Concatenate (STS0, TEMP, Local2)
Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))
}
//
// Implement a generic Method to check _OSC information which may be called
// by any of the processor scopes.
//
Method(COSC, 4)
{
//
// Point to Status DWORD in the Arg3 buffer (STATUS)
//
CreateDWordField(Arg3, 0, STS0)
//
// Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
//
CreateDwordField(Arg3, 4, CAP0)
//
// _OSC needs to validate the UUID and Revision.
//
// IF Unrecognized UUID
// Return Unrecognized UUID _OSC Failure
// IF Unsupported Revision
// Return Unsupported Revision _OSC Failure
//
// STS0[0] = Reserved
// STS0[1] = _OSC Failure
// STS0[2] = Unrecognized UUID
// STS0[3] = Unsupported Revision
// STS0[4] = Capabilities masked
//
// Note: The comparison method used is necessary due to
// limitations of certain OSes which cannot perform direct
// buffer comparisons.
//
// Create a set of "Input" UUID fields.
//
CreateDwordField(Arg0, 0x0, IID0)
CreateDwordField(Arg0, 0x4, IID1)
CreateDwordField(Arg0, 0x8, IID2)
CreateDwordField(Arg0, 0xC, IID3)
//
// Create a set of "Expected" UUID fields.
//
Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))
CreateDwordField(UID0, 0x0, EID0)
CreateDwordField(UID0, 0x4, EID1)
CreateDwordField(UID0, 0x8, EID2)
CreateDwordField(UID0, 0xC, EID3)
//
// Verify the input UUID matches the expected UUID.
//
If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3)))))
{
//
// Return Unrecognized UUID _OSC Failure
//
Store (0x6, STS0)
Return (Arg3)
}
If(LNot(LEqual(Arg1,1)))
{
//
// Return Unsupported Revision _OSC Failure
//
Store (0xA, STS0)
Return (Arg3)
}
Return (Arg3)
}
//
// Get the capability information and load appropriate tables as needed.
//
Method(GCAP, 1)
{
// Point to Status DWORD in the Arg0 buffer (STATUS)
CreateDWordField(Arg0, 0, STS0)
// Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
CreateDwordField(Arg0, 4, CAP0)
//
// If the UUID was unrecognized or the _OSC revision was unsupported,
// return without updating capabilities.
//
If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA)))
{
Return()
}
//
// Check if this is a query (BIT0 of Status = 1).
// If so, mask off the bits we support and return.
//
if (And(STS0, 1))
{
And(CAP0, 0xBFF, CAP0)
Return()
}
//
// Store result of PDC. (We clear out the MSB, which was just
// used as a placeholder for the compiler; and then "OR" the
// value in case we get multiple calls, each of which only
// reports partial support.)
//
Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)
//
// Check IF the IST SSDTs should be loaded.
//
// CFGD[0] = GV3 Capable/Enabled
//
If(And(CFGD,0x01))
{
//
// Load the IST SSDTs if:
// (1) CMP capable and enabled.
// (2) Driver supports P-States in MP configurations
// (3) Driver supports direct HW P-State control
// (4) SSDT is not already loaded
//
// CFGD[24] = Two or more cores enabled
// PDCx[3] = OS supports C1 and P-states in MP systems
// PDCx[0] = OS supports direct access of the perf MSR
// SDTL[0] = CPU0 IST SSDT Loaded
//
If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01))))
{
//
// Flag the IST SSDT as loaded for CPU0
//
Or(SDTL, 0x01, SDTL)
OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))
Load(IST0, HI0) // Dynamically load the CPU0IST SSDT
}
}
//
// Check IF the CST SSDTs should be loaded.
//
// CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
//
If(And(CFGD,0x82))
{
//
// Load the CST SSDTs if:
// (1) CMP capable/enabled
// (2) Driver supports multi-processor configurations
// (3) CPU0 CST ISDT is not already loaded
//
// CFGD[24] = Two or more cores enabled
// PDCx[3] = OS supports C1 and P-states in MP systems
// PDCx[4] = OS supports ind. C2/C3 in MP systems
// SDTL[1] = CPU0 CST SSDT Loaded
//
If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02))))
{
//
// Flag the CST SSDT as loaded for CPU0
//
Or(SDTL, 0x02, SDTL)
OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))
Load(CST0, HC0) // Dynamically load the CPU0CST SSDT
}
}
Return ()
}
}
Scope(\_PR.CPU1)
{
//
// Define handles for opregions (used by load.)
//
Name(HI1,0) // Handle to APIST
Name(HC1,0) // Handle to APCST
Method(_PDC,1)
{
//
// Refer to \_PR.CPU0._PDC for description.
//
Store(\_PR.CPU0.CPDC(Arg0), Local0)
GCAP(Local0)
//Return (Local0)
}
Method(_OSC, 4)
{
//
// Refer to \_PR.CPU0._OSC for description.
//
Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
GCAP(Local0)
Return (Local0)
}
//
// Get the capability information and load appropriate tables as needed.
//
Method(GCAP, 1)
{
//
// Point to Status DWORD in the Arg0 buffer (STATUS)
//
CreateDWordField(Arg0, 0, STS1)
//
// Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
//
CreateDwordField(Arg0, 4, CAP1)
//
// If the UUID was unrecognized or the _OSC revision was unsupported,
// return without updating capabilities.
//
If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
{
Return()
}
//
// Check if this is a query (BIT0 of Status = 1).
// If so, mask off the bits we support and return.
//
if (And(STS1, 1))
{
And(CAP1, 0xBFF, CAP1)
Return()
}
//
// Store result of PDC. (We clear out the MSB, which was just
// used as a placeholder for the compiler; and then "OR" the
// value in case we get multiple calls, each of which only
// reports partial support.)
//
Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
//
// Attempt to dynamically load the IST SSDTs if:
// (1) Driver supports P-States in MP configurations
// (2) Driver supports direct HW P-State control
//
// PDCx[3] = OS supports C1 and P-states in MP systems
// PDCx[0] = OS supports direct access of the perf MSR
//
If(LEqual(And(PDC0, 0x0009), 0x0009))
{
APPT()
}
//
// Load the CST SSDTs if:
// (1) Driver supports multi-processor configurations
//
// PDCx[3] = OS supports C1 and P-states in MP systems
// PDCx[4] = OS supports ind. C2/C3 in MP systems
//
If(And(PDC0,0x0018))
{
APCT()
}
Return()
}
//
// Dynamically load the CST SSDTs if:
// (1) C-States are enabled
// (2) SSDT is not already loaded
//
// CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
// SDTL[5] = AP CST SSDT Loaded
//
Method(APCT,0)
{
If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
{
//
// Flag the CST SSDT as loaded for the AP's
//
Or(SDTL, 0x20, SDTL)
//
// Dynamically load the APCST SSDT
//
OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
Load(CST1, HC1)
}
}
//
// Dynamically load the IST SSDTs if:
// (1) If GV3 capable and enabled
// (2) SSDT is not already loaded
//
// CFGD[0] = GV3 Capable/Enabled
// SDTL[4] = AP IST SSDT Loaded
//
Method(APPT,0)
{
If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
{
//
// Flag the IST SSDT as loaded for CPU0
//
Or(SDTL, 0x10, SDTL)
OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
}
}
} // End CPU1
Scope(\_PR.CPU2)
{
//
// Define handles for opregions (used by load.)
//
Name(HI1,0) // Handle to APIST
Name(HC1,0) // Handle to APCST
Method(_PDC,1)
{
//
// Refer to \_PR.CPU0._PDC for description.
//
Store(\_PR.CPU0.CPDC(Arg0), Local0)
GCAP(Local0)
//Return (Local0)
}
Method(_OSC, 4)
{
//
// Refer to \_PR.CPU0._OSC for description.
//
Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
GCAP(Local0)
Return (Local0)
}
//
// Get the capability information and load appropriate tables as needed.
//
Method(GCAP, 1)
{
//
// Point to Status DWORD in the Arg0 buffer (STATUS)
//
CreateDWordField(Arg0, 0, STS1)
//
// Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
//
CreateDwordField(Arg0, 4, CAP1)
//
// If the UUID was unrecognized or the _OSC revision was unsupported,
// return without updating capabilities.
//
If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
{
Return()
}
//
// Check if this is a query (BIT0 of Status = 1).
// If so, mask off the bits we support and return.
//
if (And(STS1, 1))
{
And(CAP1, 0xBFF, CAP1)
Return()
}
//
// Store result of PDC. (We clear out the MSB, which was just
// used as a placeholder for the compiler; and then "OR" the
// value in case we get multiple calls, each of which only
// reports partial support.)
//
Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
//
// Attempt to dynamically load the IST SSDTs if:
// (1) Driver supports P-States in MP configurations
// (2) Driver supports direct HW P-State control
//
// PDCx[3] = OS supports C1 and P-states in MP systems
// PDCx[0] = OS supports direct access of the perf MSR
//
If(LEqual(And(PDC0, 0x0009), 0x0009))
{
APPT()
}
//
// Load the CST SSDTs if:
// (1) Driver supports multi-processor configurations
//
// PDCx[3] = OS supports C1 and P-states in MP systems
// PDCx[4] = OS supports ind. C2/C3 in MP systems
//
If(And(PDC0,0x0018))
{
APCT()
}
Return()
}
//
// Dynamically load the CST SSDTs if:
// (1) C-States are enabled
// (2) SSDT is not already loaded
//
// CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
// SDTL[5] = AP CST SSDT Loaded
//
Method(APCT,0)
{
If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
{
//
// Flag the CST SSDT as loaded for the AP's
//
Or(SDTL, 0x20, SDTL)
//
// Dynamically load the APCST SSDT
//
OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
Load(CST1, HC1)
}
}
//
// Dynamically load the IST SSDTs if:
// (1) If GV3 capable and enabled
// (2) SSDT is not already loaded
//
// CFGD[0] = GV3 Capable/Enabled
// SDTL[4] = AP IST SSDT Loaded
//
Method(APPT,0)
{
If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
{
//
// Flag the IST SSDT as loaded for CPU0
//
Or(SDTL, 0x10, SDTL)
OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
}
}
} // End CPU1
Scope(\_PR.CPU3)
{
//
// Define handles for opregions (used by load.)
//
Name(HI1,0) // Handle to APIST
Name(HC1,0) // Handle to APCST
Method(_PDC,1)
{
//
// Refer to \_PR.CPU0._PDC for description.
//
Store(\_PR.CPU0.CPDC(Arg0), Local0)
GCAP(Local0)
//Return (Local0)
}
Method(_OSC, 4)
{
//
// Refer to \_PR.CPU0._OSC for description.
//
Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
GCAP(Local0)
Return (Local0)
}
//
// Get the capability information and load appropriate tables as needed.
//
Method(GCAP, 1)
{
//
// Point to Status DWORD in the Arg0 buffer (STATUS)
//
CreateDWordField(Arg0, 0, STS1)
//
// Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
//
CreateDwordField(Arg0, 4, CAP1)
//
// If the UUID was unrecognized or the _OSC revision was unsupported,
// return without updating capabilities.
//
If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
{
Return()
}
//
// Check if this is a query (BIT0 of Status = 1).
// If so, mask off the bits we support and return.
//
if (And(STS1, 1))
{
And(CAP1, 0xBFF, CAP1)
Return()
}
//
// Store result of PDC. (We clear out the MSB, which was just
// used as a placeholder for the compiler; and then "OR" the
// value in case we get multiple calls, each of which only
// reports partial support.)
//
Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
//
// Attempt to dynamically load the IST SSDTs if:
// (1) Driver supports P-States in MP configurations
// (2) Driver supports direct HW P-State control
//
// PDCx[3] = OS supports C1 and P-states in MP systems
// PDCx[0] = OS supports direct access of the perf MSR
//
If(LEqual(And(PDC0, 0x0009), 0x0009))
{
APPT()
}
//
// Load the CST SSDTs if:
// (1) Driver supports multi-processor configurations
//
// PDCx[3] = OS supports C1 and P-states in MP systems
// PDCx[4] = OS supports ind. C2/C3 in MP systems
//
If(And(PDC0,0x0018))
{
APCT()
}
Return()
}
//
// Dynamically load the CST SSDTs if:
// (1) C-States are enabled
// (2) SSDT is not already loaded
//
// CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
// SDTL[5] = AP CST SSDT Loaded
//
Method(APCT,0)
{
If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
{
//
// Flag the CST SSDT as loaded for the AP's
//
Or(SDTL, 0x20, SDTL)
//
// Dynamically load the APCST SSDT
//
OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
Load(CST1, HC1)
}
}
//
// Dynamically load the IST SSDTs if:
// (1) If GV3 capable and enabled
// (2) SSDT is not already loaded
//
// CFGD[0] = GV3 Capable/Enabled
// SDTL[4] = AP IST SSDT Loaded
//
Method(APPT,0)
{
If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
{
//
// Flag the IST SSDT as loaded for CPU0
//
Or(SDTL, 0x10, SDTL)
OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
}
}
} // End CPU3
} // End of Definition Block