Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
@@ -0,0 +1,98 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PlatformBaseAddresses.h
|
||||
|
||||
Abstract:
|
||||
|
||||
|
||||
|
||||
Revision History
|
||||
|
||||
++*/
|
||||
|
||||
|
||||
#ifndef _PLATFORM_BASE_ADDRESSES_H
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||||
#define _PLATFORM_BASE_ADDRESSES_H
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||||
|
||||
//
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||||
// Define some fixed platform device location information
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||||
//
|
||||
|
||||
//
|
||||
// Define platform base
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||||
//
|
||||
|
||||
//
|
||||
// SIO
|
||||
//
|
||||
#define SIO_BASE_ADDRESS 0x0680
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||||
#define SIO_MONITORING_BASE_ADDRESS 0x0290
|
||||
#define SIO_BASE_MASK 0xFFF0
|
||||
#define WINDBOND_ECIR_BASE_ADDRESS 0x0810
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||||
#define SIO_MAILBOX_BASE_ADDRESS 0x0360 // Used by EC controller
|
||||
#define SIO_EC_CHANNEL2 0x62 // Used by EC controller for offset 0x62 and 0x66
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||||
|
||||
|
||||
//
|
||||
// South Cluster
|
||||
//
|
||||
#define ACPI_BASE_ADDRESS 0x0400
|
||||
#define GPIO_BASE_ADDRESS 0x0500
|
||||
#define SMBUS_BUS_DEV_FUNC 0x1F0300
|
||||
#define SMBUS_BASE_ADDRESS 0xEFA0 // SMBus IO Base Address
|
||||
#define SPI_BASE_ADDRESS 0xFED01000 // SPI Memory Base Address
|
||||
#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address
|
||||
#define SMBM_BASE_ADDRESS 0xFED04000 // SMBus Memory Base Address
|
||||
#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address
|
||||
#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address
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||||
#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base Address
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||||
#define RCBA_BASE_ADDRESS 0xFED1C000 // Root Complex Base Address
|
||||
#define MPHY_BASE_ADDRESS 0xFEF00000 // MPHY Memory Base Address
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||||
#define PUNIT_BASE_ADDRESS 0xFED05000 // PUnit Memory Base Address
|
||||
|
||||
//
|
||||
// GPIO GROUP OFFSET
|
||||
//
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||||
#define GPIO_SCORE_OFFSET 0x0000
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||||
#define GPIO_NCORE_OFFSET 0x1000
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||||
#define GPIO_SSUS_OFFSET 0x2000
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||||
|
||||
//
|
||||
// MCH/CPU
|
||||
//
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||||
#define DMI_BASE_ADDRESS 0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10
|
||||
#define EP_BASE_ADDRESS 0xFED19000
|
||||
#define MC_MMIO_BASE 0xFED14000 // Base Address for MMIO registers
|
||||
|
||||
//
|
||||
// TPM
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||||
//
|
||||
#define TPM_BASE_ADDRESS 0xFED40000 // Base address for TPM
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||||
|
||||
//
|
||||
// Local and I/O APIC addresses.
|
||||
//
|
||||
#define IO_APIC_ADDRESS 0xFEC00000
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||||
#define IIO_IOAPIC_ADDRESS 0xFEC90000
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||||
#define LOCAL_APIC_ADDRESS 0xFEE00000
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||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,66 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
Capsule.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Capsule PPI definitions.
|
||||
|
||||
--*/
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||||
//
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||||
//
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||||
#ifndef _PEI_CAPSULE_PPI_H_
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||||
#define _PEI_CAPSULE_PPI_H_
|
||||
|
||||
#define PEI_CAPSULE_PPI_GUID \
|
||||
{ \
|
||||
0x3acf33ee, 0xd892, 0x40f4, 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d \
|
||||
}
|
||||
|
||||
EFI_FORWARD_DECLARATION (PEI_CAPSULE_PPI);
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_CAPSULE_COALESCE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN OUT VOID **MemoryBase,
|
||||
IN OUT UINTN *MemSize
|
||||
);
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_CAPSULE_CREATE_STATE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
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||||
IN VOID *CapsuleBase, // returned from coalesce
|
||||
IN UINTN CapsuleSize // returned from coalesce
|
||||
);
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||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_CAPSULE_CHECK_CAPSULE_UPDATE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices
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||||
);
|
||||
|
||||
typedef struct _PEI_CAPSULE_PPI {
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||||
PEI_CAPSULE_COALESCE Coalesce;
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||||
PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate;
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||||
PEI_CAPSULE_CREATE_STATE CreateState;
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||||
} PEI_CAPSULE_PPI;
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||||
|
||||
extern EFI_GUID gPeiCapsulePpiGuid;
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#endif // #ifndef _PEI_CAPSULE_PPI_H_
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||||
@@ -0,0 +1,150 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PlatformMemoryRange.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Platform Memory Range PPI as defined in EFI 2.0
|
||||
|
||||
PPI for reserving special purpose memory ranges.
|
||||
|
||||
--*/
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||||
//
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||||
//
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||||
#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
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||||
#define _PEI_PLATFORM_MEMORY_RANGE_H_
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||||
|
||||
#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \
|
||||
{ \
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||||
0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \
|
||||
}
|
||||
|
||||
typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI ;
|
||||
|
||||
#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
|
||||
|
||||
#define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF
|
||||
#define PEI_MR_OPTION_ROM_NONE 0x00000000
|
||||
#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
|
||||
#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
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||||
#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
|
||||
#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
|
||||
#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
|
||||
#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
|
||||
#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
|
||||
#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
|
||||
#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
|
||||
#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
|
||||
#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
|
||||
#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
|
||||
#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
|
||||
#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
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||||
#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
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||||
#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
|
||||
|
||||
//
|
||||
// SMRAM Memory Range
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||||
//
|
||||
#define PEI_MEMORY_RANGE_SMRAM UINT32
|
||||
#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
|
||||
#define PEI_MR_SMRAM_NONE 0x00000000
|
||||
#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
|
||||
#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
|
||||
#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
|
||||
#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
|
||||
#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
|
||||
//
|
||||
// If adding additional entries, SMRAM Size
|
||||
// is a multiple of 128KB.
|
||||
//
|
||||
#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
|
||||
#define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001
|
||||
#define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002
|
||||
#define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004
|
||||
#define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008
|
||||
#define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010
|
||||
#define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020
|
||||
#define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040
|
||||
|
||||
#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
|
||||
#define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001
|
||||
#define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001
|
||||
#define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001
|
||||
#define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001
|
||||
#define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002
|
||||
#define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002
|
||||
#define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004
|
||||
#define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004
|
||||
#define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008
|
||||
#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
|
||||
|
||||
//
|
||||
// Graphics Memory Range
|
||||
//
|
||||
#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32
|
||||
#define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF
|
||||
#define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000
|
||||
#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000
|
||||
//
|
||||
// If adding additional entries, Graphics Memory Size
|
||||
// is a multiple of 512KB.
|
||||
//
|
||||
#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF
|
||||
#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
|
||||
#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001
|
||||
#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002
|
||||
#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002
|
||||
#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008
|
||||
#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008
|
||||
#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010
|
||||
#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010
|
||||
#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020
|
||||
#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020
|
||||
#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040
|
||||
#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040
|
||||
#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060
|
||||
#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060
|
||||
#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080
|
||||
#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080
|
||||
#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
|
||||
#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100
|
||||
#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
|
||||
#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200
|
||||
//
|
||||
// Pci Memory Hole
|
||||
//
|
||||
#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
|
||||
#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_CHOOSE_RANGES) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,
|
||||
IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,
|
||||
IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,
|
||||
IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,
|
||||
IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask
|
||||
);
|
||||
|
||||
struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
|
||||
PEI_CHOOSE_RANGES ChooseRanges;
|
||||
};
|
||||
|
||||
extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PlatformMemorySize.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Platform Memory Size PPI as defined in Tiano
|
||||
|
||||
PPI for describing the minimum platform memory size in order to successfully
|
||||
pass control into DXE
|
||||
|
||||
--*/
|
||||
//
|
||||
//
|
||||
#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_
|
||||
#define _PEI_PLATFORM_MEMORY_SIZE_H_
|
||||
|
||||
#define PEI_PLATFORM_MEMORY_SIZE_PPI_GUID \
|
||||
{ \
|
||||
0x9a7ef41e, 0xc140, 0x4bd1, 0xb8, 0x84, 0x1e, 0x11, 0x24, 0xb, 0x4c, 0xe6 \
|
||||
}
|
||||
|
||||
EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_SIZE_PPI);
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_MEMORY_SIZE_PPI * This,
|
||||
IN OUT UINT64 *MemorySize
|
||||
);
|
||||
|
||||
typedef struct _PEI_PLATFORM_MEMORY_SIZE_PPI {
|
||||
PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE GetPlatformMemorySize;
|
||||
} PEI_PLATFORM_MEMORY_SIZE_PPI;
|
||||
|
||||
extern EFI_GUID gPeiPlatformMemorySizePpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,171 @@
|
||||
//
|
||||
//
|
||||
/*++
|
||||
|
||||
Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
SmmAccess.h
|
||||
|
||||
Abstract:
|
||||
|
||||
SmmAccess PPI
|
||||
|
||||
This code abstracts the PEI core to provide SmmAccess services.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PEI_SMM_ACCESS_PPI_H_
|
||||
#define _PEI_SMM_ACCESS_PPI_H_
|
||||
|
||||
#ifdef ECP_FLAG
|
||||
#include "Guid/SmramMemoryReserve/SmramMemoryReserve.h"
|
||||
#else
|
||||
#include "Guid/SmramMemoryReserve.h"
|
||||
#endif
|
||||
|
||||
#define PEI_SMM_ACCESS_PPI_GUID \
|
||||
{ \
|
||||
0x268f33a9, 0xcccd, 0x48be, 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 \
|
||||
}
|
||||
|
||||
typedef struct _PEI_SMM_ACCESS_PPI PEI_SMM_ACCESS_PPI;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_SMM_OPEN) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_SMM_ACCESS_PPI *This,
|
||||
IN UINTN DescriptorIndex
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This routine accepts a request to "open" a region of SMRAM. The
|
||||
region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
|
||||
The use of "open" means that the memory is visible from all PEIM
|
||||
and SMM agents.
|
||||
|
||||
Arguments:
|
||||
PeiServices - General purpose services available to every PEIM.
|
||||
This - Pointer to the SMM Access Interface.
|
||||
DescriptorIndex - Region of SMRAM to Open.
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - The region was successfully opened.
|
||||
EFI_DEVICE_ERROR - The region could not be opened because locked by
|
||||
chipset.
|
||||
EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
|
||||
--*/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_SMM_CLOSE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_SMM_ACCESS_PPI *This,
|
||||
IN UINTN DescriptorIndex
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This routine accepts a request to "close" a region of SMRAM. The
|
||||
region could be legacy AB or TSEG near top of physical memory.
|
||||
The use of "close" means that the memory is only visible from SMM agents,
|
||||
not from PEIM.
|
||||
|
||||
Arguments:
|
||||
PeiServices - General purpose services available to every PEIM.
|
||||
This - Pointer to the SMM Access Interface.
|
||||
DescriptorIndex - Region of SMRAM to Close.
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - The region was successfully closed.
|
||||
EFI_DEVICE_ERROR - The region could not be closed because locked by
|
||||
chipset.
|
||||
EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
|
||||
|
||||
--*/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_SMM_LOCK) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_SMM_ACCESS_PPI *This,
|
||||
IN UINTN DescriptorIndex
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This routine accepts a request to "lock" SMRAM. The
|
||||
region could be legacy AB or TSEG near top of physical memory.
|
||||
The use of "lock" means that the memory can no longer be opened
|
||||
to PEIM.
|
||||
|
||||
Arguments:
|
||||
PeiServices - General purpose services available to every PEIM.
|
||||
This - Pointer to the SMM Access Interface.
|
||||
DescriptorIndex - Region of SMRAM to Lock.
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - The region was successfully locked.
|
||||
EFI_DEVICE_ERROR - The region could not be locked because at least
|
||||
one range is still open.
|
||||
EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
|
||||
|
||||
--*/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_SMM_CAPABILITIES) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_SMM_ACCESS_PPI *This,
|
||||
IN OUT UINTN *SmramMapSize,
|
||||
IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This routine services a user request to discover the SMRAM
|
||||
capabilities of this platform. This will report the possible
|
||||
ranges that are possible for SMRAM access, based upon the
|
||||
memory controller capabilities.
|
||||
|
||||
Arguments:
|
||||
PeiServices - General purpose services available to every PEIM.
|
||||
This - Pointer to the SMRAM Access Interface.
|
||||
SmramMapSize - Pointer to the variable containing size of the
|
||||
buffer to contain the description information.
|
||||
SmramMap - Buffer containing the data describing the Smram
|
||||
region descriptors.
|
||||
Returns:
|
||||
EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.
|
||||
EFI_SUCCESS - The user provided a sufficiently-sized buffer.
|
||||
--*/
|
||||
;
|
||||
|
||||
struct _PEI_SMM_ACCESS_PPI {
|
||||
PEI_SMM_OPEN Open;
|
||||
PEI_SMM_CLOSE Close;
|
||||
PEI_SMM_LOCK Lock;
|
||||
PEI_SMM_CAPABILITIES GetCapabilities;
|
||||
BOOLEAN LockState;
|
||||
BOOLEAN OpenState;
|
||||
};
|
||||
|
||||
extern EFI_GUID gPeiSmmAccessPpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,45 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
VlvMmioPolicy.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition details between ValleyView platform drivers during PEI phase.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLV_MMIO_POLICY_PPI_H_
|
||||
#define _VLV_MMIO_POLICY_PPI_H_
|
||||
|
||||
#define VLV_MMIO_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0xE767BF7F, 0x4DB6, 0x5B34, 0x10, 0x11, 0x4F, 0xBE, 0x4C, 0xA7, 0xAF, 0xD2 \
|
||||
}
|
||||
|
||||
extern EFI_GUID gVlvMmioPolicyPpiGuid;
|
||||
|
||||
|
||||
//
|
||||
// MRC Platform Policiy PPI
|
||||
//
|
||||
typedef struct _VLV_MMIO_POLICY_PPI {
|
||||
UINT16 MmioSize;
|
||||
} VLV_MMIO_POLICY_PPI;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif // _VLV_MMIO_POLICY_PPI_H_
|
||||
@@ -0,0 +1,41 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
VlvPeiInit.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition between ValleyView MRC and VlvInitPeim driver..
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLV_PEI_INIT_H_
|
||||
#define _VLV_PEI_INIT_H_
|
||||
|
||||
//
|
||||
// Define the VLV PEI Init PPI GUID
|
||||
//
|
||||
#define VLV_PEI_INIT_PPI_GUID \
|
||||
{ \
|
||||
0x9ea8911, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11 \
|
||||
}
|
||||
|
||||
//
|
||||
// Extern the GUID for PPI users.
|
||||
//
|
||||
extern EFI_GUID gVlvPeiInitPpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,112 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
VlvPolicy.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition details between ValleyView MRC and platform drivers during PEI phase.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLV_POLICY_PPI_H_
|
||||
#define _VLV_POLICY_PPI_H_
|
||||
|
||||
//
|
||||
// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}
|
||||
//
|
||||
#define VLV_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \
|
||||
}
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gVlvPolicyPpiGuid;
|
||||
|
||||
//
|
||||
// PPI revision number
|
||||
// Any backwards compatible changes to this PPI will result in an update in the revision number
|
||||
// Major changes will require publication of a new PPI
|
||||
//
|
||||
#define MRC_PLATFORM_POLICY_PPI_REVISION 1
|
||||
|
||||
#ifndef MAX_SOCKETS
|
||||
#define MAX_SOCKETS 4
|
||||
#endif
|
||||
|
||||
#define S3_TIMING_DATA_LEN 9
|
||||
#define S3_READ_TRAINING_DATA_LEN 16
|
||||
#define S3_WRITE_TRAINING_DATA_LEN 12
|
||||
|
||||
#ifndef S3_RESTORE_DATA_LEN
|
||||
#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
|
||||
#endif // S3_RESTORE_DATA_LEN
|
||||
#pragma pack(1)
|
||||
//
|
||||
// MRC Platform Data Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 SpdAddressTable[MAX_SOCKETS];
|
||||
UINT8 TSonDimmSmbusAddress[MAX_SOCKETS];
|
||||
|
||||
UINT16 SmbusBar;
|
||||
UINT32 IchRcba;
|
||||
UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode)
|
||||
UINT32 WdbRegionSize;
|
||||
UINT32 SmBusAddress;
|
||||
UINT8 UserBd;
|
||||
UINT8 PlatformType;
|
||||
UINT8 FastBoot;
|
||||
UINT8 DynSR;
|
||||
} VLV_PLATFORM_DATA;
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT16 MmioSize;
|
||||
UINT16 GttSize;
|
||||
UINT8 IgdDvmt50PreAlloc;
|
||||
UINT8 PrimaryDisplay;
|
||||
UINT8 PAVPMode;
|
||||
UINT8 ApertureSize;
|
||||
UINT8 InternalGraphics;
|
||||
UINT8 IgdTurboEn;
|
||||
} GT_CONFIGURATION;
|
||||
|
||||
typedef struct {
|
||||
UINT8 EccSupport;
|
||||
UINT16 DdrFreqLimit;
|
||||
UINT8 MaxTolud;
|
||||
} MEMORY_CONFIGURATION;
|
||||
|
||||
|
||||
//
|
||||
// MRC Platform Policiy PPI
|
||||
//
|
||||
typedef struct _VLV_POLICY_PPI {
|
||||
UINT8 Revision;
|
||||
VLV_PLATFORM_DATA PlatformData;
|
||||
GT_CONFIGURATION GtConfig;
|
||||
MEMORY_CONFIGURATION MemConfig;
|
||||
VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE
|
||||
UINT8 ISPEn; //ISP (IUNIT) Device Enabled
|
||||
UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS
|
||||
} VLV_POLICY_PPI;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif // _VLV_POLICY_PPI_H_
|
||||
@@ -0,0 +1,219 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
IgdOpRegion.h
|
||||
|
||||
Abstract:
|
||||
|
||||
This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
|
||||
an interface between system BIOS, ASL code, and Graphics drivers.
|
||||
|
||||
Supporting Specifiction: IGD OpRegion/Software SCI SPEC
|
||||
|
||||
Note: Data structures defined in this protocol are packed not naturally
|
||||
aligned.
|
||||
|
||||
GUID forms:
|
||||
{CDC5DDDF-E79D-41ec-A9B0-6565490DB9D3}
|
||||
(0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3);
|
||||
|
||||
Acronyms:
|
||||
NVS: ACPI Non Volatile Storage
|
||||
OpRegion: ACPI Operational Region
|
||||
VBT: Video BIOS Table (OEM customizable data)
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _IGD_OPREGION_PROTOCOL_H_
|
||||
#define _IGD_OPREGION_PROTOCOL_H_
|
||||
|
||||
//
|
||||
// OpRegion / Software SCI protocol GUID
|
||||
//
|
||||
#define IGD_OPREGION_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3 \
|
||||
}
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gIgdOpRegionProtocolGuid;
|
||||
|
||||
//
|
||||
// Forward reference for pure ANSI compatability
|
||||
//
|
||||
typedef struct _IGD_OPREGION_PROTOCOL IGD_OPREGION_PROTOCOL;
|
||||
|
||||
//
|
||||
// Protocol data definitions
|
||||
//
|
||||
|
||||
//
|
||||
// OpRegion structures:
|
||||
// Sub-structures define the different parts of the OpRegion followed by the
|
||||
// main structure representing the entire OpRegion.
|
||||
//
|
||||
// Note: These structures are packed to 1 byte offsets because the exact
|
||||
// data location is requred by the supporting design specification due to
|
||||
// the fact that the data is used by ASL and Graphics driver code compiled
|
||||
// separatly.
|
||||
//
|
||||
|
||||
//
|
||||
// OpRegion header (mailbox 0) structure and #defines.
|
||||
//
|
||||
#pragma pack (1)
|
||||
typedef struct {
|
||||
CHAR8 SIGN[0x10]; // 0 OpRegion signature
|
||||
UINT32 SIZE; // 0x10 OpRegion size
|
||||
UINT32 OVER; // 0x14 OpRegion structure version
|
||||
UINT8 SVER[0x20]; // 0x18 System BIOS build version
|
||||
UINT8 VVER[0x10]; // 0x38 Video BIOS build version
|
||||
UINT8 GVER[0x10]; // 0x48 Graphic driver build version
|
||||
UINT32 MBOX; // 0x58 Mailboxes supported
|
||||
UINT32 DMOD; // 0x5C Driver Model
|
||||
UINT32 PCON; // 0x60 Platform Configuration Info
|
||||
CHAR8 GOPV[0x20]; // 0X64 GOP build version
|
||||
UINT8 RSV[0x7C]; // Reserved
|
||||
} OPREGION_HEADER;
|
||||
#pragma pack ()
|
||||
|
||||
//
|
||||
// OpRegion mailbox 1 (public ACPI Methods).
|
||||
//
|
||||
#pragma pack (1)
|
||||
typedef struct {
|
||||
UINT32 DRDY; // 0 Driver readiness
|
||||
UINT32 CSTS; // 4 Status
|
||||
UINT32 CEVT; // 8 Current event
|
||||
UINT8 RM11[0x14]; // 12 Reserved
|
||||
UINT32 DIDL; // 32 Supported display devices list
|
||||
UINT32 DDL2; // 8 Devices.
|
||||
UINT32 DDL3;
|
||||
UINT32 DDL4;
|
||||
UINT32 DDL5;
|
||||
UINT32 DDL6;
|
||||
UINT32 DDL7;
|
||||
UINT32 DDL8;
|
||||
UINT32 CPDL; // 64 Currently present display devices list
|
||||
UINT32 CPL2; // 8 Devices.
|
||||
UINT32 CPL3;
|
||||
UINT32 CPL4;
|
||||
UINT32 CPL5;
|
||||
UINT32 CPL6;
|
||||
UINT32 CPL7;
|
||||
UINT32 CPL8;
|
||||
UINT32 CADL; // 96 Currently active display devices list
|
||||
UINT32 CAL2; // 8 Devices.
|
||||
UINT32 CAL3;
|
||||
UINT32 CAL4;
|
||||
UINT32 CAL5;
|
||||
UINT32 CAL6;
|
||||
UINT32 CAL7;
|
||||
UINT32 CAL8;
|
||||
UINT32 NADL; // 128 Next active device list
|
||||
UINT32 NDL2; // 8 Devices.
|
||||
UINT32 NDL3;
|
||||
UINT32 NDL4;
|
||||
UINT32 NDL5;
|
||||
UINT32 NDL6;
|
||||
UINT32 NDL7;
|
||||
UINT32 NDL8;
|
||||
UINT32 ASLP; // 160 ASL sleep timeout
|
||||
UINT32 TIDX; // 164 Toggle table index
|
||||
UINT32 CHPD; // 168 Current hot plug enable indicator
|
||||
UINT32 CLID; // 172 Current lid state indicator
|
||||
UINT32 CDCK; // 176 Current docking state indicator
|
||||
UINT32 SXSW; // 180 Display Switch notification on Sx State resume
|
||||
UINT32 EVTS; // 184 Events supported by ASL
|
||||
UINT32 CNOT; // 188 Current OS Notification
|
||||
UINT32 NRDY; // 192 Reasons for DRDY = 0
|
||||
UINT8 RM12[0x3C]; // 196 Reserved
|
||||
} OPREGION_MBOX1;
|
||||
#pragma pack ()
|
||||
|
||||
//
|
||||
// OpRegion mailbox 2 (Software SCI Interface).
|
||||
//
|
||||
#pragma pack (1)
|
||||
typedef struct {
|
||||
UINT32 SCIC; // 0 Software SCI function number parameters
|
||||
UINT32 PARM; // 4 Software SCI additional parameters
|
||||
UINT32 DSLP; // 8 Driver sleep timeout
|
||||
UINT8 RM21[0xF4]; // 12 Reserved
|
||||
} OPREGION_MBOX2;
|
||||
#pragma pack ()
|
||||
|
||||
//
|
||||
// OpRegion mailbox 3 (Power Conservation).
|
||||
//
|
||||
#pragma pack (1)
|
||||
typedef struct {
|
||||
UINT32 ARDY; // 0 Driver readiness
|
||||
UINT32 ASLC; // 4 ASLE interrupt command / status
|
||||
UINT32 TCHE; // 8 Technology enabled indicator
|
||||
UINT32 ALSI; // 12 Current ALS illuminance reading
|
||||
UINT32 BCLP; // 16 Backlight britness to set
|
||||
UINT32 PFIT; // 20 Panel fitting Current State or Request
|
||||
UINT32 CBLV; // 24 Brightness Current State
|
||||
UINT16 BCLM[0x14]; // 28 Backlight Brightness Level Duty Cycle Mapping Table
|
||||
UINT32 CPFM; // 68 Panel Fitting Current Mode
|
||||
UINT32 EPFM; // 72 Enabled Panel Fitting Mode
|
||||
UINT8 PLUT[0x4A]; // 76 Panel Look Up Table
|
||||
UINT32 PFMB; // 150 PWM Frequency and Minimum Brightness
|
||||
UINT32 CCDV; // 154 Color Correction Default Values
|
||||
UINT32 PCFT; // 158 Power Conservation Features
|
||||
UINT8 RM31[0x5E]; // 162 Reserved
|
||||
} OPREGION_MBOX3;
|
||||
#pragma pack ()
|
||||
|
||||
//
|
||||
// OpRegion mailbox 4 (VBT).
|
||||
//
|
||||
#pragma pack (1)
|
||||
typedef struct {
|
||||
UINT8 GVD1[0x1800]; // 6K Reserved
|
||||
} OPREGION_VBT;
|
||||
#pragma pack ()
|
||||
|
||||
#pragma pack (1)
|
||||
typedef struct {
|
||||
UINT8 EDIDOVRD[0x400]; // 6K Edid overriding data
|
||||
} OPREGION_MBOX5;
|
||||
#pragma pack ()
|
||||
//
|
||||
// Entire OpRegion
|
||||
//
|
||||
#pragma pack (1)
|
||||
typedef struct {
|
||||
OPREGION_HEADER Header; // OpRegion header
|
||||
OPREGION_MBOX1 MBox1; // Mailbox 1: Public ACPI Methods
|
||||
OPREGION_MBOX2 MBox2; // Mailbox 2: Software SCI Inteface
|
||||
OPREGION_MBOX3 MBox3; // Mailbox 3: Power Conservation
|
||||
OPREGION_VBT VBT; // VBT: Video BIOS Table (OEM customizable data)
|
||||
OPREGION_MBOX5 MBox5;
|
||||
} IGD_OPREGION_STRUC;
|
||||
#pragma pack ()
|
||||
|
||||
//
|
||||
// Protocol data structure definition
|
||||
//
|
||||
struct _IGD_OPREGION_PROTOCOL {
|
||||
IGD_OPREGION_STRUC *OpRegion;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,89 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
MemInfo.h
|
||||
|
||||
Abstract:
|
||||
|
||||
This protocol provides the memory information data, such as
|
||||
total physical memory size, memory frequency, memory size
|
||||
of each dimm and rank.
|
||||
|
||||
This protocol is EFI compatible.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _MEM_INFO_PROTOCOL_H_
|
||||
#define _MEM_INFO_PROTOCOL_H_
|
||||
|
||||
//
|
||||
// Define the protocol GUID
|
||||
//
|
||||
#define MEM_INFO_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x6f20f7c8, 0xe5ef, 0x4f21, 0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae \
|
||||
}
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gMemInfoProtocolGuid;
|
||||
|
||||
//
|
||||
// Forward reference for ANSI C compatibility
|
||||
//
|
||||
typedef struct _MEM_INFO_PROTOCOL MEM_INFO_PROTOCOL;
|
||||
|
||||
//
|
||||
// Protocol definitions
|
||||
//
|
||||
|
||||
#define CH_NUM 2
|
||||
#define DIMM_NUM 1
|
||||
#define RANK_NUM 2
|
||||
|
||||
#pragma pack(1)
|
||||
typedef struct {
|
||||
UINT32 memSize;
|
||||
UINT8 ddrFreq;
|
||||
UINT8 ddrType;
|
||||
BOOLEAN EccSupport;
|
||||
UINT16 dimmSize[CH_NUM * DIMM_NUM];
|
||||
UINT8 reserved;
|
||||
UINT16 reserved2;
|
||||
} MEMORY_INFO_DATA;
|
||||
#pragma pack()
|
||||
|
||||
/*++
|
||||
Data definition:
|
||||
|
||||
memSize Total physical memory size
|
||||
ddrFreq DDR Frequency
|
||||
EccSupport ECC Support
|
||||
dimmSize Dimm Size
|
||||
DimmExist Dimm Present or not
|
||||
RankInDimm No. of ranks in a dimm
|
||||
|
||||
--*/
|
||||
|
||||
//
|
||||
// Protocol definition
|
||||
//
|
||||
struct _MEM_INFO_PROTOCOL {
|
||||
MEMORY_INFO_DATA MemInfoData;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,73 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
/** @file
|
||||
**/
|
||||
|
||||
#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_
|
||||
#define _PLATFORM_GOP_POLICY_PROTOCOL_H_
|
||||
|
||||
#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \
|
||||
{ 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d }
|
||||
|
||||
#define EFI_BMP_IMAGE_GUID \
|
||||
{ 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA }
|
||||
|
||||
#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01
|
||||
#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02 x0222
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
typedef enum {
|
||||
LidClosed,
|
||||
LidOpen,
|
||||
LidStatusMax
|
||||
} LID_STATUS;
|
||||
|
||||
typedef enum {
|
||||
Docked,
|
||||
UnDocked,
|
||||
DockStatusMax
|
||||
} DOCK_STATUS;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *GET_PLATFORM_LID_STATUS) (
|
||||
OUT LID_STATUS *CurrentLidStatus
|
||||
);
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *GET_VBT_DATA) (
|
||||
OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
|
||||
OUT UINT32 *VbtSize
|
||||
);
|
||||
|
||||
#pragma pack()
|
||||
|
||||
typedef struct _PLATFORM_GOP_POLICY_PROTOCOL {
|
||||
UINT32 Revision;
|
||||
GET_PLATFORM_LID_STATUS GetPlatformLidStatus;
|
||||
GET_VBT_DATA GetVbtData;
|
||||
} PLATFORM_GOP_POLICY_PROTOCOL;
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gPlatformGOPPolicyGuid;
|
||||
|
||||
extern EFI_GUID gBmpImageGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,111 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
VlvPlatformPolicy.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition details between MCH and platform drivers during DXE phase.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLV_PLATFORM_POLICY_H_
|
||||
#define _VLV_PLATFORM_POLICY_H_
|
||||
|
||||
//
|
||||
// VLV Policy provided by platform for DXE phase {5BAB88BA-E0E2-4674-B6AD-B812F6881CD6}
|
||||
//
|
||||
#define DXE_VLV_PLATFORM_POLICY_GUID \
|
||||
{0x5bab88ba, 0xe0e2, 0x4674, 0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6}
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gDxeVlvPlatformPolicyGuid;
|
||||
|
||||
//
|
||||
// Protocol revision number
|
||||
// Any backwards compatible changes to this protocol will result in an update in the revision number
|
||||
// Major changes will require publication of a new protocol
|
||||
//
|
||||
#define DXE_VLV_PLATFORM_POLICY_PROTOCOL_REVISION 0
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT8 PFITStatus;
|
||||
UINT8 IgdTheramlSupport;
|
||||
UINT8 ALSEnabled;
|
||||
UINT8 LidStatus;
|
||||
} IGD_PANEL_FEATURES;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Reserved00;
|
||||
UINT8 Reserved01;
|
||||
UINT16 Reserved02;
|
||||
UINT16 Reserved03;
|
||||
UINT16 Reserved04;
|
||||
UINT16 Reserved05;
|
||||
UINT16 Reserved06;
|
||||
UINT16 Reserved07;
|
||||
UINT16 Reserved08;
|
||||
UINT16 Reserved09;
|
||||
UINT16 Reserved0A;
|
||||
UINT16 Reserved0B;
|
||||
UINT16 Reserved0C;
|
||||
UINT16 Reserved0D;
|
||||
UINT8 Reserved0E;
|
||||
UINT8 Reserved0F;
|
||||
UINT32 Reserved10;
|
||||
UINT32 Reserved11;
|
||||
UINT32 Reserved12;
|
||||
UINT32 Reserved13;
|
||||
UINT32 Reserved14;
|
||||
UINT8 Reserved15;
|
||||
UINT8 Reserved16;
|
||||
} DPTF_SETTINGS;
|
||||
|
||||
//
|
||||
// MCH DXE Platform Policiy ==================================================
|
||||
//
|
||||
|
||||
#define NO_AUDIO 0
|
||||
#define HD_AUDIO 1
|
||||
#define LPE_AUDIO 2
|
||||
|
||||
typedef struct _DXE_VLV_PLATFORM_POLICY_PROTOCOL {
|
||||
UINT8 Revision;
|
||||
IGD_PANEL_FEATURES IgdPanelFeatures;
|
||||
DPTF_SETTINGS Reserved;
|
||||
UINT8 GraphicReserve00;
|
||||
UINT8 GraphicsPerfAnalyzers;
|
||||
UINT8 PwmReserved00;
|
||||
UINT8 PwmReserved01;
|
||||
UINT8 PmSupport;
|
||||
UINT8 GraphicReserve01;
|
||||
UINT8 GfxPause;
|
||||
UINT8 GraphicsFreqReq;
|
||||
UINT8 GraphicReserve03;
|
||||
UINT8 GraphicReserve02;
|
||||
UINT8 GraphicReserve04;
|
||||
UINT8 PavpMode;
|
||||
UINT8 GraphicReserve05;
|
||||
UINT8 UlClockGating;
|
||||
UINT8 IdleReserve;
|
||||
UINT8 AudioTypeSupport;
|
||||
UINT8 GraphicReserve06;
|
||||
} DXE_VLV_PLATFORM_POLICY_PROTOCOL;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,61 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
Valleyview.h
|
||||
|
||||
Abstract:
|
||||
|
||||
This header file provides common definitions just for Valleyview-SOC using to avoid including extra module's file.
|
||||
--*/
|
||||
|
||||
#ifndef _MC_H_INCLUDED_
|
||||
#define _MC_H_INCLUDED_
|
||||
/*
|
||||
< Extended Configuration Base Address.*/
|
||||
#define EC_BASE 0xE0000000
|
||||
|
||||
//
|
||||
// DEVICE 0 (Memroy Controller Hub)
|
||||
//
|
||||
#define MC_BUS 0x00
|
||||
#define MC_DEV 0x00
|
||||
#define MC_DEV2 0x02
|
||||
#define MC_FUN 0x00
|
||||
// NC DEV 0 Vendor and Device IDs
|
||||
#define MC_VID 0x8086
|
||||
#define MC_DID_OFFSET 0x2 //Device Identification
|
||||
#define MC_GGC_OFFSET 0x50 //GMCH Graphics Control Register
|
||||
|
||||
//
|
||||
// Device 2 Register Equates
|
||||
//
|
||||
#define IGD_BUS 0x00
|
||||
#define IGD_DEV 0x02
|
||||
#define IGD_FUN_0 0x00
|
||||
#define IGD_FUN_1 0x01
|
||||
#define IGD_DEV_FUN (IGD_DEV << 3)
|
||||
#define IGD_BUS_DEV_FUN (MC_BUS << 8) + IGD_DEV_FUN
|
||||
#define IGD_VID 0x8086
|
||||
#define IGD_DID 0xA001
|
||||
#define IGD_MGGC_OFFSET 0x0050 //GMCH Graphics Control Register 0x50
|
||||
#define IGD_BSM_OFFSET 0x005C //Base of Stolen Memory
|
||||
#define IGD_SWSCI_OFFSET 0x00E0 //Software SCI 0xE0 2
|
||||
#define IGD_ASLE_OFFSET 0x00E4 //System Display Event Register 0xE4 4
|
||||
#define IGD_ASLS_OFFSET 0x00FC // ASL Storage
|
||||
#define IGD_DID_QS 0x0BE2 //RCOverride -a: Fix the DID error
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,260 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
vlvAccess.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Macros to simplify and abstract the interface to PCI configuration.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLVACCESS_H_INCLUDED_
|
||||
#define _VLVACCESS_H_INCLUDED_
|
||||
|
||||
#include "Valleyview.h"
|
||||
#include "VlvCommonDefinitions.h"
|
||||
#include <Library/IoLib.h>
|
||||
|
||||
//
|
||||
// Memory Mapped IO access macros used by MSG BUS LIBRARY
|
||||
//
|
||||
#define MmioAddress( BaseAddr, Register ) \
|
||||
( (UINTN)BaseAddr + \
|
||||
(UINTN)(Register) \
|
||||
)
|
||||
|
||||
|
||||
//
|
||||
// UINT32
|
||||
//
|
||||
|
||||
#define Mmio32Ptr( BaseAddr, Register ) \
|
||||
( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
|
||||
|
||||
#define Mmio32( BaseAddr, Register ) \
|
||||
*Mmio32Ptr( BaseAddr, Register )
|
||||
|
||||
#define Mmio32Or( BaseAddr, Register, OrData ) \
|
||||
Mmio32( BaseAddr, Register ) = \
|
||||
(UINT32) ( \
|
||||
Mmio32( BaseAddr, Register ) | \
|
||||
(UINT32)(OrData) \
|
||||
)
|
||||
|
||||
#define Mmio32And( BaseAddr, Register, AndData ) \
|
||||
Mmio32( BaseAddr, Register ) = \
|
||||
(UINT32) ( \
|
||||
Mmio32( BaseAddr, Register ) & \
|
||||
(UINT32)(AndData) \
|
||||
)
|
||||
|
||||
#define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
|
||||
Mmio32( BaseAddr, Register ) = \
|
||||
(UINT32) ( \
|
||||
( Mmio32( BaseAddr, Register ) & \
|
||||
(UINT32)(AndData) \
|
||||
) | \
|
||||
(UINT32)(OrData) \
|
||||
)
|
||||
|
||||
//
|
||||
// UINT16
|
||||
//
|
||||
|
||||
#define Mmio16Ptr( BaseAddr, Register ) \
|
||||
( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) )
|
||||
|
||||
#define Mmio16( BaseAddr, Register ) \
|
||||
*Mmio16Ptr( BaseAddr, Register )
|
||||
|
||||
#define Mmio16Or( BaseAddr, Register, OrData ) \
|
||||
Mmio16( BaseAddr, Register ) = \
|
||||
(UINT16) ( \
|
||||
Mmio16( BaseAddr, Register ) | \
|
||||
(UINT16)(OrData) \
|
||||
)
|
||||
|
||||
#define Mmio16And( BaseAddr, Register, AndData ) \
|
||||
Mmio16( BaseAddr, Register ) = \
|
||||
(UINT16) ( \
|
||||
Mmio16( BaseAddr, Register ) & \
|
||||
(UINT16)(AndData) \
|
||||
)
|
||||
|
||||
#define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
|
||||
Mmio16( BaseAddr, Register ) = \
|
||||
(UINT16) ( \
|
||||
( Mmio16( BaseAddr, Register ) & \
|
||||
(UINT16)(AndData) \
|
||||
) | \
|
||||
(UINT16)(OrData) \
|
||||
)
|
||||
|
||||
//
|
||||
// UINT8
|
||||
//
|
||||
|
||||
#define Mmio8Ptr( BaseAddr, Register ) \
|
||||
( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) )
|
||||
|
||||
#define Mmio8( BaseAddr, Register ) \
|
||||
*Mmio8Ptr( BaseAddr, Register )
|
||||
|
||||
#define Mmio8Or( BaseAddr, Register, OrData ) \
|
||||
Mmio8( BaseAddr, Register ) = \
|
||||
(UINT8) ( \
|
||||
Mmio8( BaseAddr, Register ) | \
|
||||
(UINT8)(OrData) \
|
||||
)
|
||||
|
||||
#define Mmio8And( BaseAddr, Register, AndData ) \
|
||||
Mmio8( BaseAddr, Register ) = \
|
||||
(UINT8) ( \
|
||||
Mmio8( BaseAddr, Register ) & \
|
||||
(UINT8)(AndData) \
|
||||
)
|
||||
|
||||
#define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
|
||||
Mmio8( BaseAddr, Register ) = \
|
||||
(UINT8) ( \
|
||||
( Mmio8( BaseAddr, Register ) & \
|
||||
(UINT8)(AndData) \
|
||||
) | \
|
||||
(UINT8)(OrData) \
|
||||
)
|
||||
|
||||
//
|
||||
// MSG BUS API
|
||||
//
|
||||
|
||||
#define MSG_BUS_ENABLED 0x000000F0
|
||||
#define MSGBUS_MASKHI 0xFFFFFF00
|
||||
#define MSGBUS_MASKLO 0x000000FF
|
||||
|
||||
#define MESSAGE_BYTE_EN BIT4
|
||||
#define MESSAGE_WORD_EN BIT4 | BIT5
|
||||
#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7
|
||||
|
||||
#define SIDEBAND_OPCODE 0x78
|
||||
#define MEMREAD_OPCODE 0x00000000
|
||||
#define MEMWRITE_OPCODE 0x01000000
|
||||
|
||||
|
||||
|
||||
/***************************/
|
||||
//
|
||||
// Memory mapped PCI IO
|
||||
//
|
||||
|
||||
#define PciCfgPtr(Bus, Device, Function, Register )\
|
||||
(UINTN)(Bus << 20) + \
|
||||
(UINTN)(Device << 15) + \
|
||||
(UINTN)(Function << 12) + \
|
||||
(UINTN)(Register)
|
||||
|
||||
#define PciCfg32Read_CF8CFC(B,D,F,R) \
|
||||
(UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC))
|
||||
|
||||
#define PciCfg32Write_CF8CFC(B,D,F,R,Data) \
|
||||
(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data))
|
||||
|
||||
#define PciCfg32Or_CF8CFC(B,D,F,R,O) \
|
||||
PciCfg32Write_CF8CFC(B,D,F,R, \
|
||||
(PciCfg32Read_CF8CFC(B,D,F,R) | (O)))
|
||||
|
||||
#define PciCfg32And_CF8CFC(B,D,F,R,A) \
|
||||
PciCfg32Write_CF8CFC(B,D,F,R, \
|
||||
(PciCfg32Read_CF8CFC(B,D,F,R) & (A)))
|
||||
|
||||
#define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \
|
||||
PciCfg32Write_CF8CFC(B,D,F,R, \
|
||||
(PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O))
|
||||
|
||||
//
|
||||
// Device 0, Function 0
|
||||
//
|
||||
#define McD0PciCfg64(Register) MmPci64 (0, MC_BUS, 0, 0, Register)
|
||||
#define McD0PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 0, 0, Register, OrData)
|
||||
#define McD0PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 0, 0, Register, AndData)
|
||||
#define McD0PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD0PciCfg32(Register) MmPci32 (0, MC_BUS, 0, 0, Register)
|
||||
#define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 0, 0, Register, OrData)
|
||||
#define McD0PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 0, 0, Register, AndData)
|
||||
#define McD0PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD0PciCfg16(Register) MmPci16 (0, MC_BUS, 0, 0, Register)
|
||||
#define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 0, 0, Register, OrData)
|
||||
#define McD0PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 0, 0, Register, AndData)
|
||||
#define McD0PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD0PciCfg8(Register) MmPci8 (0, MC_BUS, 0, 0, Register)
|
||||
#define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 0, 0, Register, OrData)
|
||||
#define McD0PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 0, 0, Register, AndData)
|
||||
#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) MmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
|
||||
|
||||
|
||||
//
|
||||
// Device 2, Function 0
|
||||
//
|
||||
#define McD2PciCfg64(Register) MmPci64 (0, MC_BUS, 2, 0, Register)
|
||||
#define McD2PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 2, 0, Register, OrData)
|
||||
#define McD2PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 2, 0, Register, AndData)
|
||||
#define McD2PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD2PciCfg32(Register) MmPci32 (0, MC_BUS, 2, 0, Register)
|
||||
#define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 2, 0, Register, OrData)
|
||||
#define McD2PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 2, 0, Register, AndData)
|
||||
#define McD2PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD2PciCfg16(Register) MmPci16 (0, MC_BUS, 2, 0, Register)
|
||||
#define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 2, 0, Register, OrData)
|
||||
#define McD2PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 2, 0, Register, AndData)
|
||||
#define McD2PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)
|
||||
|
||||
#define McD2PciCfg8(Register) MmPci8 (0, MC_BUS, 2, 0, Register)
|
||||
#define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 2, 0, Register, OrData)
|
||||
#define McD2PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 2, 0, Register, AndData)
|
||||
|
||||
//
|
||||
// IO
|
||||
//
|
||||
|
||||
#ifndef IoIn8
|
||||
|
||||
#define IoIn8(Port) \
|
||||
IoRead8(Port)
|
||||
|
||||
#define IoIn16(Port) \
|
||||
IoRead16(Port)
|
||||
|
||||
#define IoIn32(Port) \
|
||||
IoRead32(Port)
|
||||
|
||||
#define IoOut8(Port, Data) \
|
||||
IoWrite8(Port, Data)
|
||||
|
||||
#define IoOut16(Port, Data) \
|
||||
IoWrite16(Port, Data)
|
||||
|
||||
#define IoOut32(Port, Data) \
|
||||
IoWrite32(Port, Data)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,258 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
VlvCommonDefinitions.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Macros to simplify and abstract the interface to PCI configuration.
|
||||
|
||||
--*/
|
||||
|
||||
///
|
||||
/// PCI CONFIGURATION MAP REGISTER OFFSETS
|
||||
///
|
||||
#ifndef PCI_VID
|
||||
#define PCI_VID 0x0000 ///< Vendor ID Register
|
||||
#define PCI_DID 0x0002 ///< Device ID Register
|
||||
#define PCI_CMD 0x0004 ///< PCI Command Register
|
||||
#define PCI_STS 0x0006 ///< PCI Status Register
|
||||
#define PCI_RID 0x0008 ///< Revision ID Register
|
||||
#define PCI_IFT 0x0009 ///< Interface Type
|
||||
#define PCI_SCC 0x000A ///< Sub Class Code Register
|
||||
#define PCI_BCC 0x000B ///< Base Class Code Register
|
||||
#define PCI_CLS 0x000C ///< Cache Line Size
|
||||
#define PCI_PMLT 0x000D ///< Primary Master Latency Timer
|
||||
#define PCI_HDR 0x000E ///< Header Type Register
|
||||
#define PCI_BIST 0x000F ///< Built in Self Test Register
|
||||
#define PCI_BAR0 0x0010 ///< Base Address Register 0
|
||||
#define PCI_BAR1 0x0014 ///< Base Address Register 1
|
||||
#define PCI_BAR2 0x0018 ///< Base Address Register 2
|
||||
#define PCI_PBUS 0x0018 ///< Primary Bus Number Register
|
||||
#define PCI_SBUS 0x0019 ///< Secondary Bus Number Register
|
||||
#define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register
|
||||
#define PCI_SMLT 0x001B ///< Secondary Master Latency Timer
|
||||
#define PCI_BAR3 0x001C ///< Base Address Register 3
|
||||
#define PCI_IOBASE 0x001C ///< I/O base Register
|
||||
#define PCI_IOLIMIT 0x001D ///< I/O Limit Register
|
||||
#define PCI_SECSTATUS 0x001E ///< Secondary Status Register
|
||||
#define PCI_BAR4 0x0020 ///< Base Address Register 4
|
||||
#define PCI_MEMBASE 0x0020 ///< Memory Base Register
|
||||
#define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register
|
||||
#define PCI_BAR5 0x0024 ///< Base Address Register 5
|
||||
#define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register
|
||||
#define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register
|
||||
#define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits
|
||||
#define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits
|
||||
#define PCI_SVID 0x002C ///< Subsystem Vendor ID
|
||||
#define PCI_SID 0x002E ///< Subsystem ID
|
||||
#define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register
|
||||
#define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register
|
||||
#define PCI_CAPP 0x0034 ///< Capabilities Pointer
|
||||
#define PCI_EROM 0x0038 ///< Expansion ROM Base Address
|
||||
#define PCI_INTLINE 0x003C ///< Interrupt Line Register
|
||||
#define PCI_INTPIN 0x003D ///< Interrupt Pin Register
|
||||
#define PCI_MAXGNT 0x003E ///< Max Grant Register
|
||||
#define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register
|
||||
#define PCI_MAXLAT 0x003F ///< Max Latency Register
|
||||
#endif
|
||||
//
|
||||
// Bit Difinitions
|
||||
//
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x0001
|
||||
#define BIT1 0x0002
|
||||
#define BIT2 0x0004
|
||||
#define BIT3 0x0008
|
||||
#define BIT4 0x0010
|
||||
#define BIT5 0x0020
|
||||
#define BIT6 0x0040
|
||||
#define BIT7 0x0080
|
||||
#define BIT8 0x0100
|
||||
#define BIT9 0x0200
|
||||
#define BIT10 0x0400
|
||||
#define BIT11 0x0800
|
||||
#define BIT12 0x1000
|
||||
#define BIT13 0x2000
|
||||
#define BIT14 0x4000
|
||||
#define BIT15 0x8000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
#endif
|
||||
|
||||
#ifndef _PCIACCESS_H_INCLUDED_
|
||||
#define _PCIACCESS_H_INCLUDED_
|
||||
#ifndef PCI_EXPRESS_BASE_ADDRESS
|
||||
#define PCI_EXPRESS_BASE_ADDRESS 0xE0000000
|
||||
#endif
|
||||
|
||||
#ifndef MmPciAddress
|
||||
#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
|
||||
( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
|
||||
(UINTN)(Bus << 20) + \
|
||||
(UINTN)(Device << 15) + \
|
||||
(UINTN)(Function << 12) + \
|
||||
(UINTN)(Register) \
|
||||
)
|
||||
#endif
|
||||
|
||||
//
|
||||
// UINT64
|
||||
//
|
||||
#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \
|
||||
( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
|
||||
|
||||
#define MmPci64( Segment, Bus, Device, Function, Register ) \
|
||||
*MmPci64Ptr( Segment, Bus, Device, Function, Register )
|
||||
|
||||
#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \
|
||||
MmPci64( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT64) ( \
|
||||
MmPci64( Segment, Bus, Device, Function, Register ) | \
|
||||
(UINT64)(OrData) \
|
||||
)
|
||||
|
||||
#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \
|
||||
MmPci64( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT64) ( \
|
||||
MmPci64( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT64)(AndData) \
|
||||
)
|
||||
|
||||
#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
|
||||
MmPci64( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT64) ( \
|
||||
( MmPci64( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT64)(AndData) \
|
||||
) | \
|
||||
(UINT64)(OrData) \
|
||||
)
|
||||
|
||||
//
|
||||
// UINT32
|
||||
//
|
||||
|
||||
#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \
|
||||
( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )
|
||||
|
||||
#define MmPci32( Segment, Bus, Device, Function, Register ) \
|
||||
*MmPci32Ptr( Segment, Bus, Device, Function, Register )
|
||||
|
||||
#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
|
||||
MmPci32( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT32) ( \
|
||||
MmPci32( Segment, Bus, Device, Function, Register ) | \
|
||||
(UINT32)(OrData) \
|
||||
)
|
||||
|
||||
#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
|
||||
MmPci32( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT32) ( \
|
||||
MmPci32( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT32)(AndData) \
|
||||
)
|
||||
|
||||
#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
|
||||
MmPci32( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT32) ( \
|
||||
( MmPci32( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT32)(AndData) \
|
||||
) | \
|
||||
(UINT32)(OrData) \
|
||||
)
|
||||
|
||||
//
|
||||
// UINT16
|
||||
//
|
||||
|
||||
#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \
|
||||
( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
|
||||
|
||||
#define MmPci16( Segment, Bus, Device, Function, Register ) \
|
||||
*MmPci16Ptr( Segment, Bus, Device, Function, Register )
|
||||
|
||||
#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
|
||||
MmPci16( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT16) ( \
|
||||
MmPci16( Segment, Bus, Device, Function, Register ) | \
|
||||
(UINT16)(OrData) \
|
||||
)
|
||||
|
||||
#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
|
||||
MmPci16( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT16) ( \
|
||||
MmPci16( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT16)(AndData) \
|
||||
)
|
||||
|
||||
#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
|
||||
MmPci16( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT16) ( \
|
||||
( MmPci16( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT16)(AndData) \
|
||||
) | \
|
||||
(UINT16)(OrData) \
|
||||
)
|
||||
|
||||
//
|
||||
// UINT8
|
||||
//
|
||||
|
||||
#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \
|
||||
( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
|
||||
|
||||
#define MmPci8( Segment, Bus, Device, Function, Register ) \
|
||||
*MmPci8Ptr( Segment, Bus, Device, Function, Register )
|
||||
|
||||
#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
|
||||
MmPci8( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT8) ( \
|
||||
MmPci8( Segment, Bus, Device, Function, Register ) | \
|
||||
(UINT8)(OrData) \
|
||||
)
|
||||
|
||||
#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
|
||||
MmPci8( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT8) ( \
|
||||
MmPci8( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT8)(AndData) \
|
||||
)
|
||||
|
||||
#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
|
||||
MmPci8( Segment, Bus, Device, Function, Register ) = \
|
||||
(UINT8) ( \
|
||||
( MmPci8( Segment, Bus, Device, Function, Register ) & \
|
||||
(UINT8)(AndData) \
|
||||
) | \
|
||||
(UINT8)(OrData) \
|
||||
)
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user