Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
@@ -0,0 +1,66 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
Capsule.h
|
||||
|
||||
Abstract:
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||||
|
||||
Capsule PPI definitions.
|
||||
|
||||
--*/
|
||||
//
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||||
//
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||||
#ifndef _PEI_CAPSULE_PPI_H_
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||||
#define _PEI_CAPSULE_PPI_H_
|
||||
|
||||
#define PEI_CAPSULE_PPI_GUID \
|
||||
{ \
|
||||
0x3acf33ee, 0xd892, 0x40f4, 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d \
|
||||
}
|
||||
|
||||
EFI_FORWARD_DECLARATION (PEI_CAPSULE_PPI);
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||||
|
||||
typedef
|
||||
EFI_STATUS
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||||
(EFIAPI *PEI_CAPSULE_COALESCE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN OUT VOID **MemoryBase,
|
||||
IN OUT UINTN *MemSize
|
||||
);
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_CAPSULE_CREATE_STATE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN VOID *CapsuleBase, // returned from coalesce
|
||||
IN UINTN CapsuleSize // returned from coalesce
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||||
);
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||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_CAPSULE_CHECK_CAPSULE_UPDATE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices
|
||||
);
|
||||
|
||||
typedef struct _PEI_CAPSULE_PPI {
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||||
PEI_CAPSULE_COALESCE Coalesce;
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PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate;
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PEI_CAPSULE_CREATE_STATE CreateState;
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} PEI_CAPSULE_PPI;
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||||
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extern EFI_GUID gPeiCapsulePpiGuid;
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#endif // #ifndef _PEI_CAPSULE_PPI_H_
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||||
@@ -0,0 +1,150 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PlatformMemoryRange.h
|
||||
|
||||
Abstract:
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||||
|
||||
Platform Memory Range PPI as defined in EFI 2.0
|
||||
|
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PPI for reserving special purpose memory ranges.
|
||||
|
||||
--*/
|
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//
|
||||
//
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#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
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#define _PEI_PLATFORM_MEMORY_RANGE_H_
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||||
|
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#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \
|
||||
{ \
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0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \
|
||||
}
|
||||
|
||||
typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI ;
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||||
|
||||
#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
|
||||
|
||||
#define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF
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#define PEI_MR_OPTION_ROM_NONE 0x00000000
|
||||
#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
|
||||
#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
|
||||
#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
|
||||
#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
|
||||
#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
|
||||
#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
|
||||
#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
|
||||
#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
|
||||
#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
|
||||
#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
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||||
#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
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||||
#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
|
||||
#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
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||||
#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
|
||||
#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
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||||
#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
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||||
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||||
//
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||||
// SMRAM Memory Range
|
||||
//
|
||||
#define PEI_MEMORY_RANGE_SMRAM UINT32
|
||||
#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
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||||
#define PEI_MR_SMRAM_NONE 0x00000000
|
||||
#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
|
||||
#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
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||||
#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
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||||
#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
|
||||
#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
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||||
//
|
||||
// If adding additional entries, SMRAM Size
|
||||
// is a multiple of 128KB.
|
||||
//
|
||||
#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
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||||
#define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001
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||||
#define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002
|
||||
#define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004
|
||||
#define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008
|
||||
#define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010
|
||||
#define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020
|
||||
#define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040
|
||||
|
||||
#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
|
||||
#define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001
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||||
#define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001
|
||||
#define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001
|
||||
#define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001
|
||||
#define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002
|
||||
#define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002
|
||||
#define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004
|
||||
#define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004
|
||||
#define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008
|
||||
#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
|
||||
|
||||
//
|
||||
// Graphics Memory Range
|
||||
//
|
||||
#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32
|
||||
#define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF
|
||||
#define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000
|
||||
#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000
|
||||
//
|
||||
// If adding additional entries, Graphics Memory Size
|
||||
// is a multiple of 512KB.
|
||||
//
|
||||
#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF
|
||||
#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
|
||||
#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001
|
||||
#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002
|
||||
#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002
|
||||
#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008
|
||||
#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008
|
||||
#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010
|
||||
#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010
|
||||
#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020
|
||||
#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020
|
||||
#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040
|
||||
#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040
|
||||
#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060
|
||||
#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060
|
||||
#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080
|
||||
#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080
|
||||
#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
|
||||
#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100
|
||||
#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
|
||||
#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200
|
||||
//
|
||||
// Pci Memory Hole
|
||||
//
|
||||
#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
|
||||
#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_CHOOSE_RANGES) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,
|
||||
IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,
|
||||
IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,
|
||||
IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,
|
||||
IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask
|
||||
);
|
||||
|
||||
struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
|
||||
PEI_CHOOSE_RANGES ChooseRanges;
|
||||
};
|
||||
|
||||
extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PlatformMemorySize.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Platform Memory Size PPI as defined in Tiano
|
||||
|
||||
PPI for describing the minimum platform memory size in order to successfully
|
||||
pass control into DXE
|
||||
|
||||
--*/
|
||||
//
|
||||
//
|
||||
#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_
|
||||
#define _PEI_PLATFORM_MEMORY_SIZE_H_
|
||||
|
||||
#define PEI_PLATFORM_MEMORY_SIZE_PPI_GUID \
|
||||
{ \
|
||||
0x9a7ef41e, 0xc140, 0x4bd1, 0xb8, 0x84, 0x1e, 0x11, 0x24, 0xb, 0x4c, 0xe6 \
|
||||
}
|
||||
|
||||
EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_SIZE_PPI);
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_PLATFORM_MEMORY_SIZE_PPI * This,
|
||||
IN OUT UINT64 *MemorySize
|
||||
);
|
||||
|
||||
typedef struct _PEI_PLATFORM_MEMORY_SIZE_PPI {
|
||||
PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE GetPlatformMemorySize;
|
||||
} PEI_PLATFORM_MEMORY_SIZE_PPI;
|
||||
|
||||
extern EFI_GUID gPeiPlatformMemorySizePpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,171 @@
|
||||
//
|
||||
//
|
||||
/*++
|
||||
|
||||
Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
SmmAccess.h
|
||||
|
||||
Abstract:
|
||||
|
||||
SmmAccess PPI
|
||||
|
||||
This code abstracts the PEI core to provide SmmAccess services.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PEI_SMM_ACCESS_PPI_H_
|
||||
#define _PEI_SMM_ACCESS_PPI_H_
|
||||
|
||||
#ifdef ECP_FLAG
|
||||
#include "Guid/SmramMemoryReserve/SmramMemoryReserve.h"
|
||||
#else
|
||||
#include "Guid/SmramMemoryReserve.h"
|
||||
#endif
|
||||
|
||||
#define PEI_SMM_ACCESS_PPI_GUID \
|
||||
{ \
|
||||
0x268f33a9, 0xcccd, 0x48be, 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 \
|
||||
}
|
||||
|
||||
typedef struct _PEI_SMM_ACCESS_PPI PEI_SMM_ACCESS_PPI;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_SMM_OPEN) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_SMM_ACCESS_PPI *This,
|
||||
IN UINTN DescriptorIndex
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This routine accepts a request to "open" a region of SMRAM. The
|
||||
region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
|
||||
The use of "open" means that the memory is visible from all PEIM
|
||||
and SMM agents.
|
||||
|
||||
Arguments:
|
||||
PeiServices - General purpose services available to every PEIM.
|
||||
This - Pointer to the SMM Access Interface.
|
||||
DescriptorIndex - Region of SMRAM to Open.
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - The region was successfully opened.
|
||||
EFI_DEVICE_ERROR - The region could not be opened because locked by
|
||||
chipset.
|
||||
EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
|
||||
--*/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_SMM_CLOSE) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_SMM_ACCESS_PPI *This,
|
||||
IN UINTN DescriptorIndex
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This routine accepts a request to "close" a region of SMRAM. The
|
||||
region could be legacy AB or TSEG near top of physical memory.
|
||||
The use of "close" means that the memory is only visible from SMM agents,
|
||||
not from PEIM.
|
||||
|
||||
Arguments:
|
||||
PeiServices - General purpose services available to every PEIM.
|
||||
This - Pointer to the SMM Access Interface.
|
||||
DescriptorIndex - Region of SMRAM to Close.
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - The region was successfully closed.
|
||||
EFI_DEVICE_ERROR - The region could not be closed because locked by
|
||||
chipset.
|
||||
EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
|
||||
|
||||
--*/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_SMM_LOCK) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_SMM_ACCESS_PPI *This,
|
||||
IN UINTN DescriptorIndex
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This routine accepts a request to "lock" SMRAM. The
|
||||
region could be legacy AB or TSEG near top of physical memory.
|
||||
The use of "lock" means that the memory can no longer be opened
|
||||
to PEIM.
|
||||
|
||||
Arguments:
|
||||
PeiServices - General purpose services available to every PEIM.
|
||||
This - Pointer to the SMM Access Interface.
|
||||
DescriptorIndex - Region of SMRAM to Lock.
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - The region was successfully locked.
|
||||
EFI_DEVICE_ERROR - The region could not be locked because at least
|
||||
one range is still open.
|
||||
EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
|
||||
|
||||
--*/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_SMM_CAPABILITIES) (
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_SMM_ACCESS_PPI *This,
|
||||
IN OUT UINTN *SmramMapSize,
|
||||
IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This routine services a user request to discover the SMRAM
|
||||
capabilities of this platform. This will report the possible
|
||||
ranges that are possible for SMRAM access, based upon the
|
||||
memory controller capabilities.
|
||||
|
||||
Arguments:
|
||||
PeiServices - General purpose services available to every PEIM.
|
||||
This - Pointer to the SMRAM Access Interface.
|
||||
SmramMapSize - Pointer to the variable containing size of the
|
||||
buffer to contain the description information.
|
||||
SmramMap - Buffer containing the data describing the Smram
|
||||
region descriptors.
|
||||
Returns:
|
||||
EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.
|
||||
EFI_SUCCESS - The user provided a sufficiently-sized buffer.
|
||||
--*/
|
||||
;
|
||||
|
||||
struct _PEI_SMM_ACCESS_PPI {
|
||||
PEI_SMM_OPEN Open;
|
||||
PEI_SMM_CLOSE Close;
|
||||
PEI_SMM_LOCK Lock;
|
||||
PEI_SMM_CAPABILITIES GetCapabilities;
|
||||
BOOLEAN LockState;
|
||||
BOOLEAN OpenState;
|
||||
};
|
||||
|
||||
extern EFI_GUID gPeiSmmAccessPpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,45 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
VlvMmioPolicy.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition details between ValleyView platform drivers during PEI phase.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLV_MMIO_POLICY_PPI_H_
|
||||
#define _VLV_MMIO_POLICY_PPI_H_
|
||||
|
||||
#define VLV_MMIO_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0xE767BF7F, 0x4DB6, 0x5B34, 0x10, 0x11, 0x4F, 0xBE, 0x4C, 0xA7, 0xAF, 0xD2 \
|
||||
}
|
||||
|
||||
extern EFI_GUID gVlvMmioPolicyPpiGuid;
|
||||
|
||||
|
||||
//
|
||||
// MRC Platform Policiy PPI
|
||||
//
|
||||
typedef struct _VLV_MMIO_POLICY_PPI {
|
||||
UINT16 MmioSize;
|
||||
} VLV_MMIO_POLICY_PPI;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif // _VLV_MMIO_POLICY_PPI_H_
|
||||
@@ -0,0 +1,41 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
VlvPeiInit.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition between ValleyView MRC and VlvInitPeim driver..
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLV_PEI_INIT_H_
|
||||
#define _VLV_PEI_INIT_H_
|
||||
|
||||
//
|
||||
// Define the VLV PEI Init PPI GUID
|
||||
//
|
||||
#define VLV_PEI_INIT_PPI_GUID \
|
||||
{ \
|
||||
0x9ea8911, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11 \
|
||||
}
|
||||
|
||||
//
|
||||
// Extern the GUID for PPI users.
|
||||
//
|
||||
extern EFI_GUID gVlvPeiInitPpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,112 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
VlvPolicy.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition details between ValleyView MRC and platform drivers during PEI phase.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLV_POLICY_PPI_H_
|
||||
#define _VLV_POLICY_PPI_H_
|
||||
|
||||
//
|
||||
// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}
|
||||
//
|
||||
#define VLV_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \
|
||||
}
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gVlvPolicyPpiGuid;
|
||||
|
||||
//
|
||||
// PPI revision number
|
||||
// Any backwards compatible changes to this PPI will result in an update in the revision number
|
||||
// Major changes will require publication of a new PPI
|
||||
//
|
||||
#define MRC_PLATFORM_POLICY_PPI_REVISION 1
|
||||
|
||||
#ifndef MAX_SOCKETS
|
||||
#define MAX_SOCKETS 4
|
||||
#endif
|
||||
|
||||
#define S3_TIMING_DATA_LEN 9
|
||||
#define S3_READ_TRAINING_DATA_LEN 16
|
||||
#define S3_WRITE_TRAINING_DATA_LEN 12
|
||||
|
||||
#ifndef S3_RESTORE_DATA_LEN
|
||||
#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
|
||||
#endif // S3_RESTORE_DATA_LEN
|
||||
#pragma pack(1)
|
||||
//
|
||||
// MRC Platform Data Structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 SpdAddressTable[MAX_SOCKETS];
|
||||
UINT8 TSonDimmSmbusAddress[MAX_SOCKETS];
|
||||
|
||||
UINT16 SmbusBar;
|
||||
UINT32 IchRcba;
|
||||
UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode)
|
||||
UINT32 WdbRegionSize;
|
||||
UINT32 SmBusAddress;
|
||||
UINT8 UserBd;
|
||||
UINT8 PlatformType;
|
||||
UINT8 FastBoot;
|
||||
UINT8 DynSR;
|
||||
} VLV_PLATFORM_DATA;
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT16 MmioSize;
|
||||
UINT16 GttSize;
|
||||
UINT8 IgdDvmt50PreAlloc;
|
||||
UINT8 PrimaryDisplay;
|
||||
UINT8 PAVPMode;
|
||||
UINT8 ApertureSize;
|
||||
UINT8 InternalGraphics;
|
||||
UINT8 IgdTurboEn;
|
||||
} GT_CONFIGURATION;
|
||||
|
||||
typedef struct {
|
||||
UINT8 EccSupport;
|
||||
UINT16 DdrFreqLimit;
|
||||
UINT8 MaxTolud;
|
||||
} MEMORY_CONFIGURATION;
|
||||
|
||||
|
||||
//
|
||||
// MRC Platform Policiy PPI
|
||||
//
|
||||
typedef struct _VLV_POLICY_PPI {
|
||||
UINT8 Revision;
|
||||
VLV_PLATFORM_DATA PlatformData;
|
||||
GT_CONFIGURATION GtConfig;
|
||||
MEMORY_CONFIGURATION MemConfig;
|
||||
VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE
|
||||
UINT8 ISPEn; //ISP (IUNIT) Device Enabled
|
||||
UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS
|
||||
} VLV_POLICY_PPI;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif // _VLV_POLICY_PPI_H_
|
||||
Reference in New Issue
Block a user