Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> Reviewed-by: Mike Wu <mike.wu@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
@@ -0,0 +1,54 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PchInitVar.h
|
||||
|
||||
Abstract:
|
||||
|
||||
This file defines variable shared between PCH Init DXE driver and PCH
|
||||
Init S3 Resume PEIM.
|
||||
|
||||
--*/
|
||||
#ifndef _PCH_INIT_VAR_H_
|
||||
#define _PCH_INIT_VAR_H_
|
||||
|
||||
#include <Protocol/PchPlatformPolicy.h>
|
||||
//
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||||
// Define the PCH Init Var GUID
|
||||
//
|
||||
#define PCH_INIT_VARIABLE_GUID {0xe6c2f70a, 0xb604, 0x4877,{0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb}}
|
||||
//
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||||
// Extern the GUID for PPI users.
|
||||
//
|
||||
extern EFI_GUID gPchInitVariableGuid;
|
||||
|
||||
#define PCH_INIT_VARIABLE_NAME L"PchInit"
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||||
|
||||
//
|
||||
// Define the Pch Init Variable structure
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 StorePosition;
|
||||
UINT32 ExecutePosition;
|
||||
} PCH_S3_PARAMETER_HEADER;
|
||||
|
||||
#pragma pack(1)
|
||||
typedef struct _PCH_INIT_VARIABLE {
|
||||
PCH_S3_PARAMETER_HEADER *PchS3Parameter;
|
||||
} PCH_INIT_VARIABLE;
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,40 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
SataControllerGuid.h
|
||||
|
||||
Abstract:
|
||||
|
||||
GUID for use in describing SataController
|
||||
|
||||
--*/
|
||||
#ifndef _SERIAL_ATA_CONTROLLER_GUID_H_
|
||||
#define _SERIAL_ATA_CONTROLLER_GUID_H_
|
||||
|
||||
#ifdef ECP_FLAG
|
||||
#define PCH_SATA_CONTROLLER_DRIVER_GUID \
|
||||
{ \
|
||||
0xbb929da9, 0x68f7, 0x4035, 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 \
|
||||
}
|
||||
#else
|
||||
#define PCH_SATA_CONTROLLER_DRIVER_GUID \
|
||||
{\
|
||||
0xbb929da9, 0x68f7, 0x4035, 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 \}
|
||||
|
||||
#endif
|
||||
|
||||
extern EFI_GUID gSataControllerDriverGuid;
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
//
|
||||
//
|
||||
/*++
|
||||
|
||||
Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
SmbusArpMap.h
|
||||
|
||||
Abstract:
|
||||
|
||||
GUID for use in describing SMBus devices that were ARPed during PEI.
|
||||
|
||||
--*/
|
||||
#ifndef _EFI_SMBUS_ARP_MAP_GUID_H_
|
||||
#define _EFI_SMBUS_ARP_MAP_GUID_H_
|
||||
|
||||
#define EFI_SMBUS_ARP_MAP_GUID \
|
||||
{ \
|
||||
0x707be83e, 0x0bf6, 0x40a5, 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 \
|
||||
}
|
||||
|
||||
extern EFI_GUID gEfiSmbusArpMapGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
Vlv2Variable.h
|
||||
|
||||
Abstract:
|
||||
|
||||
GUID used to define ValleyView2 variable.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _VLV2_VARIABLE_GUID_H_
|
||||
#define _VLV2_VARIABLE_GUID_H_
|
||||
|
||||
#define EFI_VLV2_VARIABLE \
|
||||
{ \
|
||||
0x10ba6bbe, 0xa97e, 0x41c3, {0x9a, 0x07, 0x60, 0x7a, 0xd9, 0xbd, 0x60, 0xe5 } \
|
||||
}
|
||||
extern EFI_GUID gEfiVlv2VariableGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,132 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
/*++
|
||||
|
||||
Module Name:
|
||||
|
||||
CEATA.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Header file for chipset CE-AT spec.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _CE_ATA_H
|
||||
#define _CE_ATA_H
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
|
||||
#define DATA_UNIT_SIZE 512
|
||||
|
||||
|
||||
#define CMD60 60
|
||||
#define CMD61 61
|
||||
|
||||
|
||||
#define RW_MULTIPLE_REGISTER CMD60
|
||||
#define RW_MULTIPLE_BLOCK CMD61
|
||||
|
||||
|
||||
#define CE_ATA_SIG_CE 0xCE
|
||||
#define CE_ATA_SIG_AA 0xAA
|
||||
|
||||
|
||||
#define Reg_Features_Exp 01
|
||||
#define Reg_SectorCount_Exp 02
|
||||
#define Reg_LBALow_Exp 03
|
||||
#define Reg_LBAMid_Exp 04
|
||||
#define Reg_LBAHigh_Exp 05
|
||||
#define Reg_Control 06
|
||||
#define Reg_Features_Error 09
|
||||
#define Reg_SectorCount 10
|
||||
#define Reg_LBALow 11
|
||||
#define Reg_LBAMid 12
|
||||
#define Reg_LBAHigh 13
|
||||
#define Reg_Device_Head 14
|
||||
#define Reg_Command_Status 15
|
||||
|
||||
#define Reg_scrTempC 0x80
|
||||
#define Reg_scrTempMaxP 0x84
|
||||
#define Reg_scrTempMinP 0x88
|
||||
#define Reg_scrStatus 0x8C
|
||||
#define Reg_scrReallocsA 0x90
|
||||
#define Reg_scrERetractsA 0x94
|
||||
#define Reg_scrCapabilities 0x98
|
||||
#define Reg_scrControl 0xC0
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT8 Reserved0;
|
||||
UINT8 Features_Exp;
|
||||
UINT8 SectorCount_Exp;
|
||||
UINT8 LBALow_Exp;
|
||||
UINT8 LBAMid_Exp;
|
||||
UINT8 LBAHigh_Exp;
|
||||
UINT8 Control;
|
||||
UINT8 Reserved1[2];
|
||||
UINT8 Features_Error;
|
||||
UINT8 SectorCount;
|
||||
UINT8 LBALow;
|
||||
UINT8 LBAMid;
|
||||
UINT8 LBAHigh;
|
||||
UINT8 Device_Head;
|
||||
UINT8 Command_Status;
|
||||
} TASK_FILE;
|
||||
|
||||
|
||||
//
|
||||
//Reduced ATA command set
|
||||
//
|
||||
#define IDENTIFY_DEVICE 0xEC
|
||||
#define READ_DMA_EXT 0x25
|
||||
#define WRITE_DMA_EXT 0x35
|
||||
#define STANDBY_IMMEDIATE 0xE0
|
||||
#define FLUSH_CACHE_EXT 0xEA
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT16 Reserved0[10];
|
||||
UINT16 SerialNumber[10];
|
||||
UINT16 Reserved1[3];
|
||||
UINT16 FirmwareRevision[4];
|
||||
UINT16 ModelNumber[20];
|
||||
UINT16 Reserved2[33];
|
||||
UINT16 MajorVersion;
|
||||
UINT16 Reserved3[19];
|
||||
UINT16 MaximumLBA[4];
|
||||
UINT16 Reserved4[2];
|
||||
UINT16 Sectorsize;
|
||||
UINT16 Reserved5;
|
||||
UINT16 DeviceGUID[4];
|
||||
UINT16 Reserved6[94];
|
||||
UINT16 Features;
|
||||
UINT16 MaxWritesPerAddress;
|
||||
UINT16 Reserved7[47];
|
||||
UINT16 IntegrityWord;
|
||||
} IDENTIFY_DEVICE_DATA;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,355 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
/*++
|
||||
|
||||
Module Name:
|
||||
|
||||
MMC.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Header file for Industry MMC 4.2 spec.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _MMC_H
|
||||
#define _MMC_H
|
||||
|
||||
#pragma pack(1)
|
||||
//
|
||||
//Command definition
|
||||
//
|
||||
|
||||
#define CMD0 0
|
||||
#define CMD1 1
|
||||
#define CMD2 2
|
||||
#define CMD3 3
|
||||
#define CMD4 4
|
||||
#define CMD6 6
|
||||
#define CMD7 7
|
||||
#define CMD8 8
|
||||
#define CMD9 9
|
||||
#define CMD10 10
|
||||
#define CMD11 11
|
||||
#define CMD12 12
|
||||
#define CMD13 13
|
||||
#define CMD14 14
|
||||
#define CMD15 15
|
||||
#define CMD16 16
|
||||
#define CMD17 17
|
||||
#define CMD18 18
|
||||
#define CMD19 19
|
||||
#define CMD20 20
|
||||
#define CMD23 23
|
||||
#define CMD24 24
|
||||
#define CMD25 25
|
||||
#define CMD26 26
|
||||
#define CMD27 27
|
||||
#define CMD28 28
|
||||
#define CMD29 29
|
||||
#define CMD30 30
|
||||
#define CMD35 35
|
||||
#define CMD36 36
|
||||
#define CMD38 38
|
||||
#define CMD39 39
|
||||
#define CMD40 40
|
||||
#define CMD42 42
|
||||
#define CMD55 55
|
||||
#define CMD56 56
|
||||
|
||||
|
||||
|
||||
#define GO_IDLE_STATE CMD0
|
||||
#define SEND_OP_COND CMD1
|
||||
#define ALL_SEND_CID CMD2
|
||||
#define SET_RELATIVE_ADDR CMD3
|
||||
#define SET_DSR CMD4
|
||||
#define SWITCH CMD6
|
||||
#define SELECT_DESELECT_CARD CMD7
|
||||
#define SEND_EXT_CSD CMD8
|
||||
#define SEND_CSD CMD9
|
||||
#define SEND_CID CMD10
|
||||
#define READ_DAT_UNTIL_STOP CMD11
|
||||
#define STOP_TRANSMISSION CMD12
|
||||
#define SEND_STATUS CMD13
|
||||
#define BUSTEST_R CMD14
|
||||
#define GO_INACTIVE_STATE CMD15
|
||||
#define SET_BLOCKLEN CMD16
|
||||
#define READ_SINGLE_BLOCK CMD17
|
||||
#define READ_MULTIPLE_BLOCK CMD18
|
||||
#define BUSTEST_W CMD19
|
||||
#define WRITE_DAT_UNTIL_STOP CMD20
|
||||
#define SET_BLOCK_COUNT CMD23
|
||||
#define WRITE_BLOCK CMD24
|
||||
#define WRITE_MULTIPLE_BLOCK CMD25
|
||||
#define PROGRAM_CID CMD26
|
||||
#define PROGRAM_CSD CMD27
|
||||
#define SET_WRITE_PROT CMD28
|
||||
#define CLR_WRITE_PROT CMD29
|
||||
#define SEND_WRITE_PROT CMD30
|
||||
#define ERASE_GROUP_START CMD35
|
||||
#define ERASE_GROUP_END CMD36
|
||||
#define ERASE CMD38
|
||||
#define FAST_IO CMD39
|
||||
#define GO_IRQ_STATE CMD40
|
||||
#define LOCK_UNLOCK CMD42
|
||||
#define APP_CMD CMD55
|
||||
#define GEN_CMD CMD56
|
||||
|
||||
#define B_PERM_WP_DIS 0x10
|
||||
#define B_PWR_WP_EN 0x01
|
||||
#define US_PERM_WP_DIS 0x10
|
||||
#define US_PWR_WP_EN 0x01
|
||||
|
||||
#define FREQUENCY_OD (400 * 1000)
|
||||
#define FREQUENCY_MMC_PP (26 * 1000 * 1000)
|
||||
#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)
|
||||
|
||||
#define DEFAULT_DSR_VALUE 0x404
|
||||
|
||||
//
|
||||
//Registers definition
|
||||
//
|
||||
|
||||
typedef struct {
|
||||
UINT32 Reserved0: 7; // 0
|
||||
UINT32 V170_V195: 1; // 1.70V - 1.95V
|
||||
UINT32 V200_V260: 7; // 2.00V - 2.60V
|
||||
UINT32 V270_V360: 9; // 2.70V - 3.60V
|
||||
UINT32 Reserved1: 5; // 0
|
||||
UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
|
||||
UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
|
||||
} OCR;
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT8 NotUsed: 1; // 1
|
||||
UINT8 CRC: 7; // CRC7 checksum
|
||||
UINT8 MDT; // Manufacturing date
|
||||
UINT32 PSN; // Product serial number
|
||||
UINT8 PRV; // Product revision
|
||||
UINT8 PNM[6]; // Product name
|
||||
UINT16 OID; // OEM/Application ID
|
||||
UINT8 MID; // Manufacturer ID
|
||||
} CID;
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT8 NotUsed: 1; // 1 [0:0]
|
||||
UINT8 CRC: 7; // CRC [7:1]
|
||||
UINT8 ECC: 2; // ECC code [9:8]
|
||||
UINT8 FILE_FORMAT: 2; // File format [11:10]
|
||||
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
|
||||
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
|
||||
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
|
||||
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
|
||||
UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]
|
||||
UINT16 Reserved0: 4; // 0 [20:17]
|
||||
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
|
||||
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
|
||||
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
|
||||
UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
|
||||
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
|
||||
UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]
|
||||
UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]
|
||||
UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]
|
||||
UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
|
||||
UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
|
||||
UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
|
||||
UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
|
||||
UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
|
||||
UINT32 C_SIZELow2: 2;// Device size [73:62]
|
||||
UINT32 C_SIZEHigh10: 10;// Device size [73:62]
|
||||
UINT32 Reserved1: 2; // 0 [75:74]
|
||||
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
|
||||
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
|
||||
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
|
||||
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
|
||||
UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
|
||||
UINT32 CCC: 12;// Card command classes [95:84]
|
||||
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
|
||||
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
|
||||
UINT8 TAAC ; // Data read access-time 1 [119:112]
|
||||
UINT8 Reserved2: 2; // 0 [121:120]
|
||||
UINT8 SPEC_VERS: 4; // System specification version [125:122]
|
||||
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
|
||||
} CSD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Reserved133_0[134]; // [133:0] 0
|
||||
UINT8 SEC_BAD_BLOCK_MGMNT; // [134] Bad Block Management mode
|
||||
UINT8 Reserved135; // [135] 0
|
||||
UINT8 ENH_START_ADDR[4]; // [139:136] Enhanced User Data Start Address
|
||||
UINT8 ENH_SIZE_MULT[3]; // [142:140] Enhanced User Data Start Size
|
||||
UINT8 GP_SIZE_MULT_1[3]; // [145:143] GPP1 Size
|
||||
UINT8 GP_SIZE_MULT_2[3]; // [148:146] GPP2 Size
|
||||
UINT8 GP_SIZE_MULT_3[3]; // [151:149] GPP3 Size
|
||||
UINT8 GP_SIZE_MULT_4[3]; // [154:152] GPP4 Size
|
||||
UINT8 PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting
|
||||
UINT8 PARTITIONS_ATTRIBUTES; // [156] Partitions attributes
|
||||
UINT8 MAX_ENH_SIZE_MULT[3]; // [159:157] GPP4 Start Size
|
||||
UINT8 PARTITIONING_SUPPORT; // [160] Partitioning Support
|
||||
UINT8 HPI_MGMT; // [161] HPI management
|
||||
UINT8 RST_n_FUNCTION; // [162] H/W reset function
|
||||
UINT8 BKOPS_EN; // [163] Enable background operations handshake
|
||||
UINT8 BKOPS_START; // [164] Manually start background operations
|
||||
UINT8 Reserved165; // [165] 0
|
||||
UINT8 WR_REL_PARAM; // [166] Write reliability parameter register
|
||||
UINT8 WR_REL_SET; // [167] Write reliability setting register
|
||||
UINT8 RPMB_SIZE_MULT; // [168] RPMB Size
|
||||
UINT8 FW_CONFIG; // [169] FW configuration
|
||||
UINT8 Reserved170; // [170] 0
|
||||
UINT8 USER_WP; // [171] User area write protection
|
||||
UINT8 Reserved172; // [172] 0
|
||||
UINT8 BOOT_WP; // [173] Boot area write protection
|
||||
UINT8 Reserved174; // [174] 0
|
||||
UINT8 ERASE_GROUP_DEF; // [175] High density erase group definition
|
||||
UINT8 Reserved176; // [176] 0
|
||||
UINT8 BOOT_BUS_WIDTH; // [177] Boot bus width
|
||||
UINT8 BOOT_CONFIG_PROT; // [178] Boot config protection
|
||||
UINT8 PARTITION_CONFIG; // [179] Partition config
|
||||
UINT8 Reserved180; // [180] 0
|
||||
UINT8 ERASED_MEM_CONT; // [181] Erased Memory Content
|
||||
UINT8 Reserved182; // [182] 0
|
||||
UINT8 BUS_WIDTH; // [183] Bus Width Mode
|
||||
UINT8 Reserved184; // [184] 0
|
||||
UINT8 HS_TIMING; // [185] High Speed Interface Timing
|
||||
UINT8 Reserved186; // [186] 0
|
||||
UINT8 POWER_CLASS; // [187] Power Class
|
||||
UINT8 Reserved188; // [188] 0
|
||||
UINT8 CMD_SET_REV; // [189] Command Set Revision
|
||||
UINT8 Reserved190; // [190] 0
|
||||
UINT8 CMD_SET; // [191] Command Set
|
||||
UINT8 EXT_CSD_REV; // [192] Extended CSD Revision
|
||||
UINT8 Reserved193; // [193] 0
|
||||
UINT8 CSD_STRUCTURE; // [194] CSD Structure Version
|
||||
UINT8 Reserved195; // [195] 0
|
||||
UINT8 CARD_TYPE; // [196] Card Type
|
||||
UINT8 Reserved197; // [197] 0
|
||||
UINT8 OUT_OF_INTERRUPT_TIME; // [198] Out-of-interrupt busy timing
|
||||
UINT8 PARTITION_SWITCH_TIME; // [199] Partition switching timing
|
||||
UINT8 PWR_CL_52_195; // [200] Power Class for 52MHz @ 1.95V
|
||||
UINT8 PWR_CL_26_195; // [201] Power Class for 26MHz @ 1.95V
|
||||
UINT8 PWR_CL_52_360; // [202] Power Class for 52MHz @ 3.6V
|
||||
UINT8 PWR_CL_26_360; // [203] Power Class for 26MHz @ 3.6V
|
||||
UINT8 Reserved204; // [204] 0
|
||||
UINT8 MIN_PERF_R_4_26; // [205] Minimum Read Performance for 4bit @26MHz
|
||||
UINT8 MIN_PERF_W_4_26; // [206] Minimum Write Performance for 4bit @26MHz
|
||||
UINT8 MIN_PERF_R_8_26_4_52; // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz
|
||||
UINT8 MIN_PERF_W_8_26_4_52; // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz
|
||||
UINT8 MIN_PERF_R_8_52; // [209] Minimum Read Performance for 8bit @52MHz
|
||||
UINT8 MIN_PERF_W_8_52; // [210] Minimum Write Performance for 8bit @52MHz
|
||||
UINT8 Reserved211; // [211] 0
|
||||
UINT8 SEC_COUNT[4]; // [215:212] Sector Count
|
||||
UINT8 Reserved216; // [216] 0
|
||||
UINT8 S_A_TIMEOUT; // [217] Sleep/awake timeout
|
||||
UINT8 Reserved218; // [218] 0
|
||||
UINT8 S_C_VCCQ; // [219] Sleep current (VCCQ)
|
||||
UINT8 S_C_VCC; // [220] Sleep current (VCC)
|
||||
UINT8 HC_WP_GRP_SIZE; // [221] High-capacity write protect group size
|
||||
UINT8 REL_WR_SEC_C; // [222] Reliable write sector count
|
||||
UINT8 ERASE_TIMEOUT_MULT; // [223] High-capacity erase timeout
|
||||
UINT8 HC_ERASE_GRP_SIZE; // [224] High-capacity erase unit size
|
||||
UINT8 ACC_SIZE; // [225] Access size
|
||||
UINT8 BOOT_SIZE_MULTI; // [226] Boot partition size
|
||||
UINT8 Reserved227; // [227] 0
|
||||
UINT8 BOOT_INFO; // [228] Boot information
|
||||
UINT8 SEC_TRIM_MULT; // [229] Secure TRIM Multiplier
|
||||
UINT8 SEC_ERASE_MULT; // [230] Secure Erase Multiplier
|
||||
UINT8 SEC_FEATURE_SUPPORT; // [231] Secure Feature support
|
||||
UINT8 TRIM_MULT; // [232] TRIM Multiplier
|
||||
UINT8 Reserved233; // [233] 0
|
||||
UINT8 MIN_PERF_DDR_R_8_52; // [234] Min Read Performance for 8-bit @ 52MHz
|
||||
UINT8 MIN_PERF_DDR_W_8_52; // [235] Min Write Performance for 8-bit @ 52MHz
|
||||
UINT8 Reserved237_236[2]; // [237:236] 0
|
||||
UINT8 PWR_CL_DDR_52_195; // [238] Power class for 52MHz, DDR at 1.95V
|
||||
UINT8 PWR_CL_DDR_52_360; // [239] Power class for 52MHz, DDR at 3.6V
|
||||
UINT8 Reserved240; // [240] 0
|
||||
UINT8 INI_TIMEOUT_AP; // [241] 1st initialization time after partitioning
|
||||
UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors
|
||||
UINT8 BKOPS_STATUS; // [246] Background operations status
|
||||
UINT8 Reserved501_247[255]; // [501:247] 0
|
||||
UINT8 BKOPS_SUPPORT; // [502] Background operations support
|
||||
UINT8 HPI_FEATURES; // [503] HPI features
|
||||
UINT8 S_CMD_SET; // [504] Sector Count
|
||||
UINT8 Reserved511_505[7]; // [511:505] Sector Count
|
||||
} EXT_CSD;
|
||||
|
||||
|
||||
//
|
||||
//Card Status definition
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode
|
||||
UINT32 Reserved1: 2; //Reserved for Application Specific commands
|
||||
UINT32 Reserved2: 1; //
|
||||
UINT32 SAPP_CMD: 1; //
|
||||
UINT32 Reserved3: 1; //Reserved
|
||||
UINT32 SWITCH_ERROR: 1; //
|
||||
UINT32 READY_FOR_DATA: 1; //
|
||||
UINT32 CURRENT_STATE: 4; //
|
||||
UINT32 ERASE_RESET: 1; //
|
||||
UINT32 Reserved4: 1; //Reserved
|
||||
UINT32 WP_ERASE_SKIP: 1; //
|
||||
UINT32 CID_CSD_OVERWRITE: 1; //
|
||||
UINT32 OVERRUN: 1; //
|
||||
UINT32 UNDERRUN: 1; //
|
||||
UINT32 ERROR: 1; //
|
||||
UINT32 CC_ERROR: 1; //
|
||||
UINT32 CARD_ECC_FAILED: 1; //
|
||||
UINT32 ILLEGAL_COMMAND: 1; //
|
||||
UINT32 COM_CRC_ERROR: 1; //
|
||||
UINT32 LOCK_UNLOCK_FAILED: 1; //
|
||||
UINT32 CARD_IS_LOCKED: 1; //
|
||||
UINT32 WP_VIOLATION: 1; //
|
||||
UINT32 ERASE_PARAM: 1; //
|
||||
UINT32 ERASE_SEQ_ERROR: 1; //
|
||||
UINT32 BLOCK_LEN_ERROR: 1; //
|
||||
UINT32 ADDRESS_MISALIGN: 1; //
|
||||
UINT32 ADDRESS_OUT_OF_RANGE:1; //
|
||||
} CARD_STATUS;
|
||||
|
||||
typedef struct {
|
||||
UINT32 CmdSet: 3;
|
||||
UINT32 Reserved0: 5;
|
||||
UINT32 Value: 8;
|
||||
UINT32 Index: 8;
|
||||
UINT32 Access: 2;
|
||||
UINT32 Reserved1: 6;
|
||||
} SWITCH_ARGUMENT;
|
||||
|
||||
#define CommandSet_Mode 0
|
||||
#define SetBits_Mode 1
|
||||
#define ClearBits_Mode 2
|
||||
#define WriteByte_Mode 3
|
||||
|
||||
|
||||
#define Idle_STATE 0
|
||||
#define Ready_STATE 1
|
||||
#define Ident_STATE 2
|
||||
#define Stby_STATE 3
|
||||
#define Tran_STATE 4
|
||||
#define Data_STATE 5
|
||||
#define Rcv_STATE 6
|
||||
#define Prg_STATE 7
|
||||
#define Dis_STATE 8
|
||||
#define Btst_STATE 9
|
||||
|
||||
|
||||
|
||||
#pragma pack()
|
||||
#endif
|
||||
@@ -0,0 +1,163 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
/*++
|
||||
Module Name:
|
||||
|
||||
SDCard.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Header file for Industry SD Card 2.0 spec.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _SD_CARD_H
|
||||
#define _SD_CARD_H
|
||||
|
||||
#include "Mmc.h"
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
#define CHECK_PATTERN 0xAA
|
||||
|
||||
#define ACMD6 6
|
||||
#define ACMD13 13
|
||||
#define ACMD23 23
|
||||
#define ACMD41 41
|
||||
#define ACMD42 42
|
||||
#define ACMD51 51
|
||||
|
||||
|
||||
#define SWITCH_FUNC CMD6
|
||||
#define SEND_IF_COND CMD8
|
||||
|
||||
|
||||
#define SET_BUS_WIDTH ACMD6
|
||||
#define SD_STATUS ACMD13
|
||||
#define SET_WR_BLK_ERASE_COUNT ACMD23
|
||||
#define SD_SEND_OP_COND ACMD41
|
||||
#define SET_CLR_CARD_DETECT ACMD42
|
||||
#define SEND_SCR ACMD51
|
||||
|
||||
|
||||
|
||||
#define SD_BUS_WIDTH_1 0
|
||||
#define SD_BUS_WIDTH_4 2
|
||||
|
||||
|
||||
|
||||
#define FREQUENCY_SD_PP (25 * 1000 * 1000)
|
||||
#define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000)
|
||||
|
||||
|
||||
#define SD_SPEC_10 0
|
||||
#define SD_SPEC_11 1
|
||||
#define SD_SPEC_20 2
|
||||
|
||||
|
||||
#define VOLTAGE_27_36 0x1
|
||||
|
||||
typedef struct {
|
||||
UINT8 NotUsed: 1; // 1 [0:0]
|
||||
UINT8 CRC: 7; // CRC [7:1]
|
||||
UINT8 ECC: 2; // ECC code [9:8]
|
||||
UINT8 FILE_FORMAT: 2; // File format [11:10]
|
||||
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
|
||||
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
|
||||
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
|
||||
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
|
||||
UINT16 Reserved0: 5; // 0 [20:16]
|
||||
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
|
||||
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
|
||||
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
|
||||
UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
|
||||
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
|
||||
UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
|
||||
UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
|
||||
UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
|
||||
UINT16 Reserved1: 1; // 0 [47:47]
|
||||
|
||||
UINT32 C_SIZE: 22; // Device size [69:48]
|
||||
UINT32 Reserved2: 6; // 0 [75:70]
|
||||
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
|
||||
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
|
||||
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
|
||||
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
|
||||
|
||||
UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
|
||||
UINT16 CCC: 12; // Card command classes [95:84]
|
||||
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
|
||||
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
|
||||
UINT8 TAAC ; // Data read access-time 1 [119:112]
|
||||
UINT8 Reserved3: 6; // 0 [125:120]
|
||||
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
|
||||
} CSD_SDV2;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Reserved0;
|
||||
UINT32 Reserved1: 16;
|
||||
UINT32 SD_BUS_WIDTH: 4;
|
||||
UINT32 SD_SECURITY: 3;
|
||||
UINT32 DATA_STAT_AFTER_ERASE: 1;
|
||||
UINT32 SD_SPEC: 4;
|
||||
UINT32 SCR_STRUCT: 4;
|
||||
} SCR;
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT8 Reserved0[50];
|
||||
UINT8 ERASE_OFFSET: 2;
|
||||
UINT8 ERASE_TIMEOUT: 6;
|
||||
UINT16 ERASE_SIZE;
|
||||
UINT8 Reserved1: 4;
|
||||
UINT8 AU_SIZE: 4;
|
||||
UINT8 PERFORMANCE_MOVE;
|
||||
UINT8 SPEED_CLASS;
|
||||
UINT32 SIZE_OF_PROTECTED_AREA;
|
||||
UINT32 SD_CARD_TYPE: 16;
|
||||
UINT32 Reserved2: 13;
|
||||
UINT32 SECURED_MODE: 1;
|
||||
UINT32 DAT_BUS_WIDTH: 2;
|
||||
} SD_STATUS_REG;
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT8 Reserved0[34];
|
||||
UINT16 Group1BusyStatus;
|
||||
UINT16 Group2BusyStatus;
|
||||
UINT16 Group3BusyStatus;
|
||||
UINT16 Group4BusyStatus;
|
||||
UINT16 Group5BusyStatus;
|
||||
UINT16 Group6BusyStatus;
|
||||
UINT8 DataStructureVersion;
|
||||
UINT8 Group21Status;
|
||||
UINT8 Group43Status;
|
||||
UINT8 Group65Status;
|
||||
UINT16 Group1Function;
|
||||
UINT16 Group2Function;
|
||||
UINT16 Group3Function;
|
||||
UINT16 Group4Function;
|
||||
UINT16 Group5Function;
|
||||
UINT16 Group6Function;
|
||||
UINT16 MaxCurrent;
|
||||
} SWITCH_STATUS;
|
||||
|
||||
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,175 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
I2CRegs.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Register Definitions for I2C Driver/PEIM.
|
||||
|
||||
--*/
|
||||
#include <Uefi.h>
|
||||
#include <Library/IoLib.h>
|
||||
|
||||
#ifndef I2C_REGS_A0_H
|
||||
#define I2C_REGS_A0_H
|
||||
|
||||
//
|
||||
// FIFO write workaround value.
|
||||
//
|
||||
#define FIFO_WRITE_DELAY 2
|
||||
|
||||
//
|
||||
// MMIO Register Definitions
|
||||
//
|
||||
#define R_IC_CON ( 0x00) // I2C Control
|
||||
#define B_IC_RESTART_EN BIT5
|
||||
#define B_IC_SLAVE_DISABLE BIT6
|
||||
#define V_SPEED_STANDARD 0x02
|
||||
#define V_SPEED_FAST 0x04
|
||||
#define V_SPEED_HIGH 0x06
|
||||
#define B_MASTER_MODE BIT0
|
||||
|
||||
#define R_IC_TAR ( 0x04) // I2C Target Address
|
||||
#define IC_TAR_10BITADDR_MASTER BIT12
|
||||
|
||||
#define R_IC_SAR ( 0x08) // I2C Slave Address
|
||||
#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address
|
||||
#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command
|
||||
|
||||
#define B_READ_CMD BIT8 // 1 = read, 0 = write
|
||||
#define B_CMD_STOP BIT9 // 1 = STOP
|
||||
#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
|
||||
|
||||
#define V_WRITE_CMD_MASK ( 0xFF)
|
||||
|
||||
#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count
|
||||
#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count
|
||||
#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count
|
||||
#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count
|
||||
#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count
|
||||
#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count
|
||||
#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
|
||||
#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
|
||||
#define I2C_INTR_GEN_CALL BIT11 // General call received
|
||||
#define I2C_INTR_START_DET BIT10
|
||||
#define I2C_INTR_STOP_DET BIT9
|
||||
#define I2C_INTR_ACTIVITY BIT8
|
||||
#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
|
||||
#define I2C_INTR_TX_EMPTY BIT4
|
||||
#define I2C_INTR_TX_OVER BIT3
|
||||
#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
|
||||
#define I2C_INTR_RX_OVER BIT1
|
||||
#define I2C_INTR_RX_UNDER BIT0
|
||||
#define R_IC_RAW_INTR_STAT ( 0x34) // I2C Raw Interrupt Status
|
||||
#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
|
||||
#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
|
||||
#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
|
||||
#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
|
||||
#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
|
||||
#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
|
||||
#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
|
||||
#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
|
||||
#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
|
||||
#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
|
||||
#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
|
||||
#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
|
||||
#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
|
||||
#define R_IC_ENABLE ( 0x6C) // I2C Enable
|
||||
#define R_IC_STATUS ( 0x70) // I2C Status
|
||||
|
||||
#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
|
||||
|
||||
#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
|
||||
#define STAT_RFF BIT4 // RX FIFO is completely full
|
||||
#define STAT_RFNE BIT3 // RX FIFO is not empty
|
||||
#define STAT_TFE BIT2 // TX FIFO is completely empty
|
||||
#define STAT_TFNF BIT1 // TX FIFO is not full
|
||||
|
||||
#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
|
||||
#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
|
||||
#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register
|
||||
#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register
|
||||
#define R_IC_DMA_CR ( 0x88) // DMA Control Register
|
||||
#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
|
||||
#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
|
||||
#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
|
||||
#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register
|
||||
#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register
|
||||
#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
|
||||
#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
|
||||
#define R_IC_COMP_TYPE ( 0xFC) // Component Type
|
||||
|
||||
#define R_IC_CLK_GATE ( 0xC0) // Clock Gate
|
||||
|
||||
#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
|
||||
#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
|
||||
#define I2C_FS_SCL_HCNT_VALUE_100M 0x54
|
||||
#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
|
||||
#define I2C_HS_SCL_HCNT_VALUE_100M 0x7
|
||||
#define I2C_HS_SCL_LCNT_VALUE_100M 0xE
|
||||
|
||||
#define IC_TAR_10BITADDR_MASTER BIT12
|
||||
#define FIFO_SIZE 32
|
||||
#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
|
||||
#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
|
||||
#define I2C_INTR_GEN_CALL BIT11 // General call received
|
||||
#define I2C_INTR_START_DET BIT10
|
||||
#define I2C_INTR_STOP_DET BIT9
|
||||
#define I2C_INTR_ACTIVITY BIT8
|
||||
#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
|
||||
#define I2C_INTR_TX_EMPTY BIT4
|
||||
#define I2C_INTR_TX_OVER BIT3
|
||||
#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
|
||||
#define I2C_INTR_RX_OVER BIT1
|
||||
#define I2C_INTR_RX_UNDER BIT0
|
||||
|
||||
EFI_STATUS ProgramPciLpssI2C (
|
||||
IN UINT8 BusNo
|
||||
);
|
||||
EFI_STATUS ByteReadI2C_Basic(
|
||||
IN UINT8 BusNo,
|
||||
IN UINT8 SlaveAddress,
|
||||
IN UINTN ReadBytes,
|
||||
OUT UINT8 *ReadBuffer,
|
||||
IN UINT8 Start,
|
||||
IN UINT8 End
|
||||
);
|
||||
EFI_STATUS ByteWriteI2C_Basic(
|
||||
IN UINT8 BusNo,
|
||||
IN UINT8 SlaveAddress,
|
||||
IN UINTN WriteBytes,
|
||||
IN UINT8 *WriteBuffer,
|
||||
IN UINT8 Start,
|
||||
IN UINT8 End
|
||||
);
|
||||
|
||||
EFI_STATUS ByteReadI2C(
|
||||
IN UINT8 BusNo,
|
||||
IN UINT8 SlaveAddress,
|
||||
IN UINT8 Offset,
|
||||
IN UINTN ReadBytes,
|
||||
OUT UINT8 *ReadBuffer
|
||||
);
|
||||
EFI_STATUS ByteWriteI2C(
|
||||
IN UINT8 BusNo,
|
||||
IN UINT8 SlaveAddress,
|
||||
IN UINT8 Offset,
|
||||
IN UINTN WriteBytes,
|
||||
IN UINT8 *WriteBuffer
|
||||
);
|
||||
|
||||
#endif // I2C_REGS_A0_H
|
||||
@@ -0,0 +1,121 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
@file
|
||||
PchPlatformLib.h
|
||||
|
||||
@brief
|
||||
Header file for PchPlatform Lib.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_PLATFORM_LIB_H_
|
||||
#define _PCH_PLATFORM_LIB_H_
|
||||
|
||||
///
|
||||
/// Timeout value used when Sending / Receiving messages.
|
||||
/// NOTE: this must cover the longest possible wait time
|
||||
/// between message being sent and response being available.
|
||||
/// e.g. Virtual function readiness might take some time.
|
||||
///
|
||||
VOID
|
||||
EFIAPI
|
||||
PchPmTimerStall (
|
||||
IN UINTN Microseconds
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
Delay for at least the request number of microseconds.
|
||||
This function would be called by runtime driver, please do not use any MMIO marco here.
|
||||
|
||||
@param[in] Microseconds Number of microseconds to delay.
|
||||
|
||||
@retval NONE
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
PchIsSpiDescriptorMode (
|
||||
IN UINTN SpiBase
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
Check whether SPI is in descriptor mode
|
||||
|
||||
@param[in] SpiBase The PCH Spi Base Address
|
||||
|
||||
@retval TRUE SPI is in descriptor mode
|
||||
@retval FALSE SPI is not in descriptor mode
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
PCH_STEPPING
|
||||
EFIAPI
|
||||
PchStepping (
|
||||
VOID
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
Return Pch stepping type
|
||||
|
||||
@param[in] None
|
||||
|
||||
@retval PCH_STEPPING Pch stepping type
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
BOOLEAN
|
||||
IsPchSupported (
|
||||
VOID
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
Determine if PCH is supported
|
||||
|
||||
@param[in] None
|
||||
|
||||
@retval TRUE PCH is supported
|
||||
@retval FALSE PCH is not supported
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PchAlternateAccessMode (
|
||||
IN UINTN IlbBase,
|
||||
IN BOOLEAN AmeCtrl
|
||||
)
|
||||
/**
|
||||
|
||||
This function can be called to enable/disable Alternate Access Mode
|
||||
|
||||
@param[in] IlbBase The PCH ILB Base Address
|
||||
@param[in] AmeCtrl If TRUE, enable Alternate Access Mode.
|
||||
If FALSE, disable Alternate Access Mode.
|
||||
|
||||
@retval NONE
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,526 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchAccess.h
|
||||
|
||||
@brief
|
||||
Macros that simplify accessing PCH devices's PCI registers.
|
||||
|
||||
** NOTE ** these macros assume the PCH device is on BUS 0
|
||||
|
||||
**/
|
||||
#ifndef _PCH_ACCESS_H_
|
||||
#define _PCH_ACCESS_H_
|
||||
|
||||
#include "PchRegs.h"
|
||||
#include "PchCommonDefinitions.h"
|
||||
|
||||
#ifndef STALL_ONE_MICRO_SECOND
|
||||
#define STALL_ONE_MICRO_SECOND 1
|
||||
#endif
|
||||
#ifndef STALL_ONE_SECOND
|
||||
#define STALL_ONE_SECOND 1000000
|
||||
#endif
|
||||
|
||||
///
|
||||
/// Memory Mapped PCI Access macros
|
||||
///
|
||||
///
|
||||
/// PCI Device MM Base
|
||||
///
|
||||
#ifndef MmPciAddress
|
||||
#define MmPciAddress(Segment, Bus, Device, Function, Register) \
|
||||
((UINTN) PatchPcdGet64 (PcdPciExpressBaseAddress) + \
|
||||
(UINTN) (Bus << 20) + \
|
||||
(UINTN) (Device << 15) + \
|
||||
(UINTN) (Function << 12) + \
|
||||
(UINTN) (Register) \
|
||||
)
|
||||
#endif
|
||||
///
|
||||
/// Pch Controller PCI access macros
|
||||
///
|
||||
#define PCH_RCRB_BASE ( \
|
||||
MmioRead32 (MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
PCI_FUNCTION_NUMBER_PCH_LPC), \
|
||||
R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \
|
||||
)
|
||||
|
||||
///
|
||||
/// Device 0x1b, Function 0
|
||||
///
|
||||
#define PchAzaliaPciCfg32(Register) \
|
||||
MmioRead32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register) \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg32Or(Register, OrData) \
|
||||
MmioOr32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg32And(Register, AndData) \
|
||||
MmioAnd32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg16(Register) \
|
||||
MmioRead16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register) \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg16Or(Register, OrData) \
|
||||
MmioOr16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg16And(Register, AndData) \
|
||||
MmioAnd16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData, \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register))
|
||||
|
||||
#define PchAzaliaPciCfg8Or(Register, OrData) \
|
||||
MmioOr8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg8And(Register, AndData) \
|
||||
MmioAnd8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_AZALIA, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData, \
|
||||
OrData \
|
||||
)
|
||||
|
||||
///
|
||||
/// Device 0x1f, Function 0
|
||||
///
|
||||
#define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
|
||||
|
||||
#define PchLpcMmioOr32 (Register, OrData) \
|
||||
MmioOr32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchLpcPciCfg32And(Register, AndData) \
|
||||
MmioAnd32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData, \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchLpcPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
|
||||
|
||||
#define PchLpcPciCfg16Or(Register, OrData) \
|
||||
MmioOr16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchLpcPciCfg16And(Register, AndData) \
|
||||
MmioAndThenOr16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData, \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
|
||||
|
||||
#define PchLpcPciCfg8Or(Register, OrData) \
|
||||
MmioOr8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchLpcPciCfg8And(Register, AndData) \
|
||||
MmioAnd8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_LPC, \
|
||||
0, \
|
||||
Register), \
|
||||
AndData, \
|
||||
OrData \
|
||||
)
|
||||
|
||||
|
||||
///
|
||||
/// SATA device 0x13, Function 0
|
||||
///
|
||||
#define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
|
||||
|
||||
#define PchSataPciCfg32Or(Register, OrData) \
|
||||
MmioOr32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchSataPciCfg32And(Register, AndData) \
|
||||
MmioAnd32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr32 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
AndData, \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
|
||||
|
||||
#define PchSataPciCfg16Or(Register, OrData) \
|
||||
MmioOr16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchSataPciCfg16And(Register, AndData) \
|
||||
MmioAndThenOr16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr16 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
AndData, \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchSataPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
|
||||
|
||||
#define PchSataPciCfg8Or(Register, OrData) \
|
||||
MmioOr8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
OrData \
|
||||
)
|
||||
|
||||
#define PchSataPciCfg8And(Register, AndData) \
|
||||
MmioAnd8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
AndData \
|
||||
)
|
||||
|
||||
#define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \
|
||||
MmioAndThenOr8 ( \
|
||||
MmPciAddress (0, \
|
||||
DEFAULT_PCI_BUS_NUMBER_PCH, \
|
||||
PCI_DEVICE_NUMBER_PCH_SATA, \
|
||||
PCI_FUNCTION_NUMBER_PCH_SATA, \
|
||||
Register), \
|
||||
AndData, \
|
||||
OrData \
|
||||
)
|
||||
|
||||
|
||||
///
|
||||
/// Root Complex Register Block
|
||||
///
|
||||
#define PchMmRcrb32(Register) MmioRead32 (PCH_RCRB_BASE + Register)
|
||||
|
||||
#define PchMmRcrb32Or(Register, OrData) MmioOr32 (PCH_RCRB_BASE + Register, OrData)
|
||||
|
||||
#define PchMmRcrb32And(Register, AndData) MmioAnd32 (PCH_RCRB_BASE + Register, AndData)
|
||||
|
||||
#define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)
|
||||
|
||||
#define PchMmRcrb16(Register) MmioRead16 (PCH_RCRB_BASE + Register)
|
||||
|
||||
#define PchMmRcrb16Or(Register, OrData) MmioOr16 (PCH_RCRB_BASE + Register, OrData)
|
||||
|
||||
#define PchMmRcrb16And(Register, AndData) MmioAnd16 (PCH_RCRB_BASE + Register, AndData)
|
||||
|
||||
#define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData)
|
||||
|
||||
#define PchMmRcrb8(Register) MmioRead8 (PCH_RCRB_BASE + Register)
|
||||
|
||||
#define PchMmRcrb8Or(Register, OrData) MmioOr8 (PCH_RCRB_BASE + Register, OrData)
|
||||
|
||||
#define PchMmRcrb8And(Register, AndData) MmioAnd8 (PCH_RCRB_BASE + Register, AndData)
|
||||
|
||||
#define PchMmRcrb8AndThenOr(Register, AndData, OrData) MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData)
|
||||
|
||||
|
||||
///
|
||||
/// Message Bus
|
||||
///
|
||||
|
||||
///
|
||||
/// Message Bus Registers
|
||||
///
|
||||
#define MC_MCR 0x000000D0 // Cunit Message Control Register
|
||||
#define MC_MDR 0x000000D4 // Cunit Message Data Register
|
||||
#define MC_MCRX 0x000000D8 // Cunit Message Control Register Extension
|
||||
|
||||
///
|
||||
/// Message Bus API
|
||||
///
|
||||
#define MSG_BUS_ENABLED 0x000000F0
|
||||
#define MSGBUS_MASKHI 0xFFFFFF00
|
||||
#define MSGBUS_MASKLO 0x000000FF
|
||||
#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7
|
||||
|
||||
#define PchMsgBusRead32(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \
|
||||
{ \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
(Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
|
||||
}
|
||||
|
||||
#define PchMsgBusAnd32(PortId, Register, Dbuff, AndData, ReadOpCode, WriteOpCode) \
|
||||
{ \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
(Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
}
|
||||
|
||||
#define PchMsgBusOr32(PortId, Register, Dbuff, OrData, ReadOpCode, WriteOpCode) \
|
||||
{ \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
(Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff | OrData)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
}
|
||||
|
||||
#define PchMsgBusAndThenOr32(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \
|
||||
{ \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
(Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
}
|
||||
|
||||
typedef struct _PCH_MSG_BUS_TABLE_STRUCT {
|
||||
UINT32 PortId;
|
||||
UINT32 Address;
|
||||
UINT32 AndMask;
|
||||
UINT32 OrMask;
|
||||
UINT32 ReadOpCode;
|
||||
UINT32 WriteOpCode;
|
||||
} PCH_MSG_BUS_TABLE_STRUCT_TABLE_STRUCT;
|
||||
|
||||
#ifndef _S3SUPPORT_
|
||||
#define _S3SUPPORT_
|
||||
UINTN MCRX;
|
||||
UINTN MCR;
|
||||
//
|
||||
// In S3 execute, we should follow the MSG BUS access procedure to restore the saving data.
|
||||
// To do so, we adopt READ ->> SAVE
|
||||
// Indirect IO access: (According BayTrail-M EDS chapter 3.6)
|
||||
// 1. Write Index port into MSG BUS_MCRX first.
|
||||
// 2. Write content to data register which is called MSG BUS_MDR.
|
||||
// 3. Send "message bus control" to complete the procedure.
|
||||
//
|
||||
#define S3BootScriptSaveMsgBusToMemWrite(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \
|
||||
{ \
|
||||
MCRX = (UINTN) Register & MSGBUS_MASKHI; \
|
||||
MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) MCRX); \
|
||||
S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX),1, (VOID *) (UINTN) &MCRX); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \
|
||||
(Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
|
||||
S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR),1, (VOID *) &Dbuff); \
|
||||
MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
|
||||
S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1, (VOID *) (UINTN) &MCR); \
|
||||
}
|
||||
|
||||
//
|
||||
// This macro combines two function: 1. PchMsgBusAndThenOr32 () 2. S3 boot script save
|
||||
//
|
||||
#define PchMsgBusAndThenOr32AddToS3Save(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \
|
||||
{ \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
(Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
|
||||
MCRX = (UINTN) Register & MSGBUS_MASKHI; \
|
||||
MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) MCRX); \
|
||||
S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX),1,(VOID *) (UINTN) &MCRX); \
|
||||
MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \
|
||||
(Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
|
||||
S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR),1,(VOID *) &Dbuff); \
|
||||
MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \
|
||||
S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1,(VOID *) (UINTN) &MCR); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,216 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PchCommonDefinitions.h
|
||||
|
||||
Abstract:
|
||||
|
||||
This header file provides common definitions for PCH
|
||||
|
||||
--*/
|
||||
#ifndef _PCH_COMMON_DEFINITIONS_H_
|
||||
#define _PCH_COMMON_DEFINITIONS_H_
|
||||
|
||||
//
|
||||
// MMIO access macros
|
||||
//
|
||||
#define PchMmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register))
|
||||
|
||||
//
|
||||
// 32 bit MMIO access
|
||||
//
|
||||
#define PchMmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))
|
||||
|
||||
#define PchMmio32(BaseAddr, Register) *PchMmio32Ptr (BaseAddr, Register)
|
||||
|
||||
#define PchMmio32Or(BaseAddr, Register, OrData) \
|
||||
PchMmio32 (BaseAddr, Register) = (UINT32) \
|
||||
(PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))
|
||||
|
||||
#define PchMmio32And(BaseAddr, Register, AndData) \
|
||||
PchMmio32 (BaseAddr, Register) = (UINT32) \
|
||||
(PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))
|
||||
|
||||
#define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \
|
||||
PchMmio32 (BaseAddr, Register) = (UINT32) \
|
||||
((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
|
||||
|
||||
//
|
||||
// 16 bit MMIO access
|
||||
//
|
||||
#define PchMmio16Ptr(BaseAddr, Register) ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register))
|
||||
|
||||
#define PchMmio16(BaseAddr, Register) *PchMmio16Ptr (BaseAddr, Register)
|
||||
|
||||
#define PchMmio16Or(BaseAddr, Register, OrData) \
|
||||
PchMmio16 (BaseAddr, Register) = (UINT16) \
|
||||
(PchMmio16 (BaseAddr, Register) | (UINT16) (OrData))
|
||||
|
||||
#define PchMmio16And(BaseAddr, Register, AndData) \
|
||||
PchMmio16 (BaseAddr, Register) = (UINT16) \
|
||||
(PchMmio16 (BaseAddr, Register) & (UINT16) (AndData))
|
||||
|
||||
#define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \
|
||||
PchMmio16 (BaseAddr, Register) = (UINT16) \
|
||||
((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
|
||||
|
||||
//
|
||||
// 8 bit MMIO access
|
||||
//
|
||||
#define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register))
|
||||
|
||||
#define PchMmio8(BaseAddr, Register) *PchMmio8Ptr (BaseAddr, Register)
|
||||
|
||||
#define PchMmio8Or(BaseAddr, Register, OrData) \
|
||||
PchMmio8 (BaseAddr, Register) = (UINT8) \
|
||||
(PchMmio8 (BaseAddr, Register) | (UINT8) (OrData))
|
||||
|
||||
#define PchMmio8And(BaseAddr, Register, AndData) \
|
||||
PchMmio8 (BaseAddr, Register) = (UINT8) \
|
||||
(PchMmio8 (BaseAddr, Register) & (UINT8) (AndData))
|
||||
|
||||
#define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \
|
||||
PchMmio8 (BaseAddr, Register) = (UINT8) \
|
||||
((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
|
||||
|
||||
//
|
||||
// Memory Mapped PCI Access macros
|
||||
//
|
||||
#define PCH_PCI_EXPRESS_BASE_ADDRESS 0xE0000000
|
||||
//
|
||||
// PCI Device MM Base
|
||||
//
|
||||
#define PchPciDeviceMmBase(Bus, Device, Function) \
|
||||
( \
|
||||
(UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
|
||||
(Function << 12) \
|
||||
)
|
||||
|
||||
//
|
||||
// PCI Device MM Address
|
||||
//
|
||||
#define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \
|
||||
( \
|
||||
(UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
|
||||
(Function << 12) + (UINTN) (Register) \
|
||||
)
|
||||
|
||||
//
|
||||
// 32 bit PCI access
|
||||
//
|
||||
#define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \
|
||||
((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
|
||||
|
||||
#define PchMmPci32(Segment, Bus, Device, Function, Register) *PchMmPci32Ptr (Segment, Bus, Device, Function, Register)
|
||||
|
||||
#define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \
|
||||
PchMmPci32 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))
|
||||
|
||||
#define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \
|
||||
PchMmPci32 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))
|
||||
|
||||
#define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
|
||||
PchMmPci32 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
|
||||
|
||||
//
|
||||
// 16 bit PCI access
|
||||
//
|
||||
#define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \
|
||||
((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
|
||||
|
||||
#define PchMmPci16(Segment, Bus, Device, Function, Register) *PchMmPci16Ptr (Segment, Bus, Device, Function, Register)
|
||||
|
||||
#define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \
|
||||
PchMmPci16 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))
|
||||
|
||||
#define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \
|
||||
PchMmPci16 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))
|
||||
|
||||
#define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
|
||||
PchMmPci16 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
|
||||
|
||||
//
|
||||
// 8 bit PCI access
|
||||
//
|
||||
#define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \
|
||||
((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
|
||||
|
||||
#define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register)
|
||||
|
||||
#define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \
|
||||
PchMmPci8 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))
|
||||
|
||||
#define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \
|
||||
PchMmPci8 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))
|
||||
|
||||
#define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
|
||||
PchMmPci8 ( \
|
||||
Segment, \
|
||||
Bus, \
|
||||
Device, \
|
||||
Function, \
|
||||
Register \
|
||||
) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,211 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchRegs.h
|
||||
|
||||
@brief
|
||||
Register names for VLV SC.
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_REGS_H_
|
||||
#define _PCH_REGS_H_
|
||||
|
||||
///
|
||||
/// Bit Definitions. BUGBUG: drive these definitions to code base. Should not need
|
||||
/// to be part of chipset modules
|
||||
///
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x0001
|
||||
#define BIT1 0x0002
|
||||
#define BIT2 0x0004
|
||||
#define BIT3 0x0008
|
||||
#define BIT4 0x0010
|
||||
#define BIT5 0x0020
|
||||
#define BIT6 0x0040
|
||||
#define BIT7 0x0080
|
||||
#define BIT8 0x0100
|
||||
#define BIT9 0x0200
|
||||
#define BIT10 0x0400
|
||||
#define BIT11 0x0800
|
||||
#define BIT12 0x1000
|
||||
#define BIT13 0x2000
|
||||
#define BIT14 0x4000
|
||||
#define BIT15 0x8000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
#define BIT32 0x100000000
|
||||
#define BIT33 0x200000000
|
||||
#define BIT34 0x400000000
|
||||
#define BIT35 0x800000000
|
||||
#define BIT36 0x1000000000
|
||||
#define BIT37 0x2000000000
|
||||
#define BIT38 0x4000000000
|
||||
#define BIT39 0x8000000000
|
||||
#define BIT40 0x10000000000
|
||||
#define BIT41 0x20000000000
|
||||
#define BIT42 0x40000000000
|
||||
#define BIT43 0x80000000000
|
||||
#define BIT44 0x100000000000
|
||||
#define BIT45 0x200000000000
|
||||
#define BIT46 0x400000000000
|
||||
#define BIT47 0x800000000000
|
||||
#define BIT48 0x1000000000000
|
||||
#define BIT49 0x2000000000000
|
||||
#define BIT50 0x4000000000000
|
||||
#define BIT51 0x8000000000000
|
||||
#define BIT52 0x10000000000000
|
||||
#define BIT53 0x20000000000000
|
||||
#define BIT54 0x40000000000000
|
||||
#define BIT55 0x80000000000000
|
||||
#define BIT56 0x100000000000000
|
||||
#define BIT57 0x200000000000000
|
||||
#define BIT58 0x400000000000000
|
||||
#define BIT59 0x800000000000000
|
||||
#define BIT60 0x1000000000000000
|
||||
#define BIT61 0x2000000000000000
|
||||
#define BIT62 0x4000000000000000
|
||||
#define BIT63 0x8000000000000000
|
||||
#endif
|
||||
///
|
||||
/// The default PCH PCI bus number
|
||||
///
|
||||
#define DEFAULT_PCI_BUS_NUMBER_PCH 0
|
||||
|
||||
///
|
||||
/// Default Vendor ID and Subsystem ID
|
||||
///
|
||||
#define V_PCH_INTEL_VENDOR_ID 0x8086
|
||||
#define V_PCH_DEFAULT_SID 0x7270
|
||||
#define V_PCH_DEFAULT_SVID_SID (V_PCH_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16))
|
||||
|
||||
///
|
||||
/// Include device register definitions
|
||||
///
|
||||
#include "PchRegs/PchRegsHda.h"
|
||||
#include "PchRegs/PchRegsLpss.h"
|
||||
#include "PchRegs/PchRegsPcie.h"
|
||||
#include "PchRegs/PchRegsPcu.h"
|
||||
#include "PchRegs/PchRegsRcrb.h"
|
||||
#include "PchRegs/PchRegsSata.h"
|
||||
#include "PchRegs/PchRegsScc.h"
|
||||
#include "PchRegs/PchRegsSmbus.h"
|
||||
#include "PchRegs/PchRegsSpi.h"
|
||||
#include "PchRegs/PchRegsUsb.h"
|
||||
//#include "PchRegs/PchRegsLpe.h"
|
||||
|
||||
///
|
||||
/// Device IDS that are PCH Server specific
|
||||
///
|
||||
#define IS_PCH_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
(DeviceId == V_PCH_LPC_DEVICE_ID_0) || \
|
||||
(DeviceId == V_PCH_LPC_DEVICE_ID_1) || \
|
||||
(DeviceId == V_PCH_LPC_DEVICE_ID_2) || \
|
||||
(DeviceId == V_PCH_LPC_DEVICE_ID_3) \
|
||||
)
|
||||
|
||||
#define IS_PCH_VLV_LPC_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
IS_PCH_DEVICE_ID (DeviceId) \
|
||||
)
|
||||
|
||||
#define IS_PCH_VLV_SATA_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
IS_PCH_VLV_SATA_AHCI_DEVICE_ID (DeviceId) || \
|
||||
IS_PCH_VLV_SATA_MODE_DEVICE_ID (DeviceId) || \
|
||||
IS_PCH_VLV_SATA_RAID_DEVICE_ID (DeviceId) \
|
||||
)
|
||||
|
||||
#define IS_PCH_VLV_SATA_AHCI_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
(DeviceId == V_PCH_SATA_DEVICE_ID_D_AHCI) || \
|
||||
(DeviceId == V_PCH_SATA_DEVICE_ID_M_AHCI) \
|
||||
)
|
||||
|
||||
#define IS_PCH_VLV_SATA_RAID_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
(DeviceId == V_PCH_SATA_DEVICE_ID_D_RAID) || \
|
||||
(DeviceId == V_PCH_SATA_DEVICE_ID_M_RAID) \
|
||||
)
|
||||
|
||||
#define IS_PCH_VLV_SATA_MODE_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
(DeviceId == V_PCH_SATA_DEVICE_ID_D_IDE) || \
|
||||
(DeviceId == V_PCH_SATA_DEVICE_ID_M_IDE) \
|
||||
)
|
||||
#define IS_PCH_VLV_USB_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
(DeviceId == V_PCH_USB_DEVICE_ID_0) || \
|
||||
(DeviceId == V_PCH_USB_DEVICE_ID_1) \
|
||||
)
|
||||
#define IS_PCH_VLV_PCIE_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
(DeviceId == V_PCH_PCIE_DEVICE_ID_0) || \
|
||||
(DeviceId == V_PCH_PCIE_DEVICE_ID_1) || \
|
||||
(DeviceId == V_PCH_PCIE_DEVICE_ID_2) || \
|
||||
(DeviceId == V_PCH_PCIE_DEVICE_ID_3) || \
|
||||
(DeviceId == V_PCH_PCIE_DEVICE_ID_4) || \
|
||||
(DeviceId == V_PCH_PCIE_DEVICE_ID_5) || \
|
||||
(DeviceId == V_PCH_PCIE_DEVICE_ID_6) || \
|
||||
(DeviceId == V_PCH_PCIE_DEVICE_ID_7) \
|
||||
)
|
||||
|
||||
///
|
||||
/// Any device ID that is Valleyview SC
|
||||
///
|
||||
#define IS_PCH_VLV_DEVICE_ID(DeviceId) \
|
||||
( \
|
||||
IS_PCH_VLV_LPC_DEVICE_ID (DeviceId) || \
|
||||
IS_PCH_VLV_SATA_DEVICE_ID (DeviceId) || \
|
||||
IS_PCH_VLV_USB_DEVICE_ID (DeviceId) || \
|
||||
IS_PCH_VLV_PCIE_DEVICE_ID (DeviceId) || \
|
||||
(DeviceId) == V_PCH_SMBUS_DEVICE_ID || \
|
||||
(DeviceId) == V_PCH_HDA_DEVICE_ID_0 || \
|
||||
(DeviceId) == V_PCH_HDA_DEVICE_ID_1 \
|
||||
)
|
||||
|
||||
#define IS_SUPPORTED_DEVICE_ID(DeviceId) IS_PCH_VLV_DEVICE_ID (DeviceId)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,56 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchRegsHda.h
|
||||
|
||||
@brief
|
||||
Register names for PCH High Definition Audio device.
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_REGS_HDA_H_
|
||||
#define _PCH_REGS_HDA_H_
|
||||
|
||||
///
|
||||
/// Azalia Controller Registers (D27:F0)
|
||||
///
|
||||
#define PCI_DEVICE_NUMBER_PCH_AZALIA 27
|
||||
#define PCI_FUNCTION_NUMBER_PCH_AZALIA 0
|
||||
|
||||
#define R_PCH_HDA_PCS 0x54 // Power Management Control and Status
|
||||
#define B_PCH_HDA_PCS_DATA 0xFF000000 // Data, does not apply
|
||||
#define B_PCH_HDA_PCS_CCE BIT23 // Bus Power Control Enable, does not apply
|
||||
#define B_PCH_HDA_PCS_PMES BIT15 // PME Status
|
||||
#define B_PCH_HDA_PCS_PMEE BIT8 // PME Enable
|
||||
#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) // Power State - D0/D3 Hot
|
||||
#define V_PCH_HDA_PCS_PS0 0x00
|
||||
#define V_PCH_HDA_PCS_PS3 0x03
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,492 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PchRegsLpss.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Register names for VLV Low Input Output (LPSS) module.
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
--*/
|
||||
#ifndef _PCH_REGS_LPSS_H_
|
||||
#define _PCH_REGS_LPSS_H_
|
||||
|
||||
|
||||
//
|
||||
// Low Power Input Output (LPSS) Module Registers
|
||||
//
|
||||
|
||||
//
|
||||
// LPSS DMAC Modules
|
||||
// PCI Config Space Registers
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30
|
||||
#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0
|
||||
|
||||
#define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID
|
||||
#define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID
|
||||
#define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command
|
||||
#define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA
|
||||
#define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA
|
||||
#define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List
|
||||
#define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
|
||||
#define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable
|
||||
#define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable
|
||||
#define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable
|
||||
#define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable
|
||||
|
||||
#define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code
|
||||
#define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code
|
||||
#define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID
|
||||
|
||||
#define R_PCH_LPSS_DMAC_CLHB 0x0C
|
||||
#define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23
|
||||
#define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type
|
||||
#define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer
|
||||
#define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size
|
||||
|
||||
#define R_PCH_LPSS_DMAC_BAR 0x10 // BAR
|
||||
#define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address
|
||||
#define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000
|
||||
#define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14
|
||||
#define B_PCH_LPSS_DMAC_BAR_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1
|
||||
#define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address
|
||||
#define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID
|
||||
#define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID
|
||||
#define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR
|
||||
#define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
|
||||
|
||||
#define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer
|
||||
#define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power
|
||||
|
||||
#define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt
|
||||
#define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency
|
||||
#define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000
|
||||
#define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin
|
||||
#define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line
|
||||
|
||||
#define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID
|
||||
#define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support
|
||||
#define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version
|
||||
#define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability
|
||||
#define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability
|
||||
|
||||
#define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status
|
||||
#define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status
|
||||
#define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable
|
||||
#define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset
|
||||
#define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State
|
||||
|
||||
#define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID
|
||||
#define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID
|
||||
|
||||
|
||||
//
|
||||
// LPSS I2C Module
|
||||
// PCI Config Space Registers
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7
|
||||
|
||||
#define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID
|
||||
#define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID
|
||||
#define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command
|
||||
#define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
|
||||
#define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
|
||||
#define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
|
||||
#define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
|
||||
#define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable
|
||||
#define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
|
||||
#define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
|
||||
#define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
|
||||
|
||||
#define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code
|
||||
#define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code
|
||||
#define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID
|
||||
|
||||
#define R_PCH_LPSS_I2C_CLHB 0x0C
|
||||
#define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23
|
||||
#define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type
|
||||
#define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer
|
||||
#define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size
|
||||
|
||||
#define R_PCH_LPSS_I2C_BAR 0x10 // BAR
|
||||
#define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address
|
||||
#define V_PCH_LPSS_I2C_BAR_SIZE 0x1000
|
||||
#define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12
|
||||
#define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1
|
||||
#define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address
|
||||
#define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID
|
||||
#define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID
|
||||
#define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR
|
||||
#define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
|
||||
|
||||
#define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer
|
||||
#define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power
|
||||
|
||||
#define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt
|
||||
#define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency
|
||||
#define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000
|
||||
#define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin
|
||||
#define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line
|
||||
|
||||
#define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID
|
||||
#define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support
|
||||
#define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version
|
||||
#define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability
|
||||
#define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability
|
||||
|
||||
#define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status
|
||||
#define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status
|
||||
#define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable
|
||||
#define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset
|
||||
#define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State
|
||||
|
||||
#define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID
|
||||
#define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID
|
||||
|
||||
//
|
||||
// LPSS I2C Module
|
||||
// Memory Space Registers
|
||||
//
|
||||
#define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset
|
||||
#define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
|
||||
#define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
|
||||
|
||||
//
|
||||
// LPSS PWM Modules
|
||||
// PCI Config Space Registers
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2
|
||||
|
||||
#define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID
|
||||
#define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID
|
||||
#define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command
|
||||
#define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA
|
||||
#define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA
|
||||
#define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List
|
||||
#define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
|
||||
#define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable
|
||||
#define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable
|
||||
#define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable
|
||||
#define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable
|
||||
|
||||
#define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code
|
||||
#define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code
|
||||
#define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID
|
||||
|
||||
#define R_PCH_LPSS_PWM_CLHB 0x0C
|
||||
#define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23
|
||||
#define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type
|
||||
#define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer
|
||||
#define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size
|
||||
|
||||
#define R_PCH_LPSS_PWM_BAR 0x10 // BAR
|
||||
#define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address
|
||||
#define V_PCH_LPSS_PWM_BAR_SIZE 0x1000
|
||||
#define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12
|
||||
#define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1
|
||||
#define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address
|
||||
#define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID
|
||||
#define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID
|
||||
#define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR
|
||||
#define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
|
||||
|
||||
#define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer
|
||||
#define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power
|
||||
|
||||
#define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt
|
||||
#define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency
|
||||
#define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000
|
||||
#define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin
|
||||
#define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line
|
||||
|
||||
#define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID
|
||||
#define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support
|
||||
#define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version
|
||||
#define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability
|
||||
#define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability
|
||||
|
||||
#define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status
|
||||
#define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status
|
||||
#define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable
|
||||
#define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset
|
||||
#define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State
|
||||
|
||||
#define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID
|
||||
#define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID
|
||||
|
||||
//
|
||||
// LPSS PWM Module
|
||||
// Memory Space Registers
|
||||
//
|
||||
#define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset
|
||||
#define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
|
||||
#define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset
|
||||
|
||||
//
|
||||
// LPSS HSUART Modules
|
||||
// PCI Config Space Registers
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4
|
||||
|
||||
#define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID
|
||||
#define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID
|
||||
#define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command
|
||||
#define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA
|
||||
#define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA
|
||||
#define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List
|
||||
#define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
|
||||
#define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable
|
||||
#define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable
|
||||
#define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable
|
||||
#define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable
|
||||
|
||||
#define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code
|
||||
#define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code
|
||||
#define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID
|
||||
|
||||
#define R_PCH_LPSS_HSUART_CLHB 0x0C
|
||||
#define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23
|
||||
#define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type
|
||||
#define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer
|
||||
#define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size
|
||||
|
||||
#define R_PCH_LPSS_HSUART_BAR 0x10 // BAR
|
||||
#define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address
|
||||
#define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000
|
||||
#define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12
|
||||
#define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1
|
||||
#define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address
|
||||
#define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID
|
||||
#define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID
|
||||
#define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR
|
||||
#define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
|
||||
|
||||
#define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer
|
||||
#define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power
|
||||
|
||||
#define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt
|
||||
#define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency
|
||||
#define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000
|
||||
#define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin
|
||||
#define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line
|
||||
|
||||
#define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID
|
||||
#define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support
|
||||
#define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version
|
||||
#define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability
|
||||
#define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability
|
||||
|
||||
#define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status
|
||||
#define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status
|
||||
#define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable
|
||||
#define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset
|
||||
#define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State
|
||||
|
||||
#define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID
|
||||
#define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID
|
||||
|
||||
//
|
||||
// LPSS HSUART Module
|
||||
// Memory Space Registers
|
||||
//
|
||||
#define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters
|
||||
#define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
|
||||
#define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
|
||||
#define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
|
||||
#define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable
|
||||
|
||||
#define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset
|
||||
#define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
|
||||
#define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset
|
||||
|
||||
//
|
||||
// LPSS SPI Module
|
||||
// PCI Config Space Registers
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30
|
||||
#define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5
|
||||
|
||||
#define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID
|
||||
#define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID
|
||||
#define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command
|
||||
#define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA
|
||||
#define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA
|
||||
#define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List
|
||||
#define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
|
||||
#define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable
|
||||
#define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable
|
||||
#define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable
|
||||
#define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable
|
||||
|
||||
#define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code
|
||||
#define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code
|
||||
#define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID
|
||||
|
||||
#define R_PCH_LPSS_SPI_CLHB 0x0C
|
||||
#define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23
|
||||
#define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type
|
||||
#define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer
|
||||
#define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size
|
||||
|
||||
#define R_PCH_LPSS_SPI_BAR 0x10 // BAR
|
||||
#define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address
|
||||
#define V_PCH_LPSS_SPI_BAR_SIZE 0x1000
|
||||
#define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12
|
||||
#define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1
|
||||
#define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address
|
||||
#define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator
|
||||
#define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable
|
||||
#define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type
|
||||
#define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space
|
||||
|
||||
#define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID
|
||||
#define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID
|
||||
#define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID
|
||||
|
||||
#define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR
|
||||
#define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
|
||||
|
||||
#define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer
|
||||
#define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power
|
||||
|
||||
#define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt
|
||||
#define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency
|
||||
#define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000
|
||||
#define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin
|
||||
#define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line
|
||||
|
||||
#define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID
|
||||
#define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support
|
||||
#define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version
|
||||
#define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability
|
||||
#define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability
|
||||
|
||||
#define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status
|
||||
#define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status
|
||||
#define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
|
||||
#define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset
|
||||
#define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State
|
||||
|
||||
#define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID
|
||||
#define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID
|
||||
|
||||
//
|
||||
// LPSS SPI Module
|
||||
// Memory Space Registers
|
||||
//
|
||||
#define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters
|
||||
#define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
|
||||
#define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
|
||||
#define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
|
||||
#define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable
|
||||
|
||||
#define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset
|
||||
#define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
|
||||
#define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,89 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchRegsPcie.h
|
||||
|
||||
@brief
|
||||
Register names for VLV PCI-E root port devices
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
--*/
|
||||
#ifndef _PCH_REGS_PCIE_H_
|
||||
#define _PCH_REGS_PCIE_H_
|
||||
|
||||
#define PCH_PCIE_MAX_ROOT_PORTS 4
|
||||
|
||||
///
|
||||
/// VLV PCI Express Root Ports (D28:F0~F3)
|
||||
///
|
||||
#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28
|
||||
#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
|
||||
#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
|
||||
#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
|
||||
#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
|
||||
|
||||
#define R_PCH_PCIE_ID 0x00 // Identifiers
|
||||
#define B_PCH_PCIE_ID_DID 0xFFFF0000 // Device ID
|
||||
#define V_PCH_PCIE_DEVICE_ID_0 0x0F48 // PCIE Root Port #1
|
||||
#define V_PCH_PCIE_DEVICE_ID_1 0x0F4A // PCIE Root Port #2
|
||||
#define V_PCH_PCIE_DEVICE_ID_2 0x0F4C // PCIE Root Port #3
|
||||
#define V_PCH_PCIE_DEVICE_ID_3 0x0F4E // PCIE Root Port #4
|
||||
#define B_PCH_PCIE_ID_VID 0x0000FFFF // Vendor ID
|
||||
#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID
|
||||
|
||||
|
||||
#define R_PCH_PCIE_BNUM_SLT 0x18 // Bus Numbers; Secondary Latency Timer
|
||||
#define B_PCH_PCIE_BNUM_SLT_SLT 0xFF000000 // Secondary Latency Timer
|
||||
#define B_PCH_PCIE_BNUM_SLT_SBBN 0x00FF0000 // Subordinate Bus Number
|
||||
#define B_PCH_PCIE_BNUM_SLT_SCBN 0x0000FF00 // Secondary Bus Number
|
||||
#define B_PCH_PCIE_BNUM_SLT_PBN 0x000000FF // Primary Bus Number
|
||||
#define R_PCH_PCIE_CAPP 0x34 // Capabilities List Pointer
|
||||
#define B_PCH_PCIE_CAPP 0xFF // Capabilities Pointer
|
||||
|
||||
#define R_PCH_PCIE_SLCTL_SLSTS 0x58 // Slot Control; Slot Status
|
||||
#define S_PCH_PCIE_SLCTL_SLSTS 4
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_DLLSC BIT24 // Data Link Layer State Changed
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_PFD BIT17 // Power Fault Detected
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE BIT12 // Data Link Layer State Changed Enable
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_PCC BIT10 // Power Controller Control
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_HPE BIT5 // Hot Plug Interrupt Enable
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable
|
||||
#define B_PCH_PCIE_SLCTL_SLSTS_PDE BIT3 // Presence Detect Changed Enable
|
||||
|
||||
#define R_PCH_PCIE_SVID 0x94 // Subsystem Vendor IDs
|
||||
#define S_PCH_PCIE_SVID 4
|
||||
#define B_PCH_PCIE_SVID_SID 0xFFFF0000 // Subsystem Identifier
|
||||
#define B_PCH_PCIE_SVID_SVID 0x0000FFFF // Subsystem Vendor Identifier
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,54 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchRegsRcrb.h
|
||||
|
||||
@brief
|
||||
Register names for VLV Chipset Configuration Registers
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_REGS_RCRB_H_
|
||||
#define _PCH_REGS_RCRB_H_
|
||||
|
||||
///
|
||||
/// Chipset Configuration Registers (Memory space)
|
||||
/// RCBA
|
||||
///
|
||||
#define R_PCH_RCRB_GCS 0x00 // General Control and Status
|
||||
#define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size
|
||||
#define B_PCH_RCRB_GCS_BBS (BIT11 | BIT10) // Boot BIOS Straps
|
||||
#define V_PCH_RCRB_GCS_BBS_SPI (3 << 10) // Boot BIOS strapped to SPI
|
||||
#define V_PCH_RCRB_GCS_BBS_LPC (0 << 10) // Boot BIOS strapped to LPC
|
||||
#define B_PCH_RCRB_GCS_TS BIT1 // Top Swap
|
||||
#define B_PCH_RCRB_GCS_BILD BIT0 // BIOS Interface Lock-Down
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,251 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchRegsSata.h
|
||||
|
||||
@brief
|
||||
Register names for VLV SATA controllers
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_REGS_SATA_H_
|
||||
#define _PCH_REGS_SATA_H_
|
||||
|
||||
///
|
||||
/// VLV SATA Message Bus
|
||||
///
|
||||
#define PCH_SATA_PHY_PORT_ID 0xA3 // SATA PHY Port ID
|
||||
#define PCH_SATA_PHY_MMIO_READ_OPCODE 0x00 // CUnit to SATA PHY MMIO Read Opcode
|
||||
#define PCH_SATA_PHY_MMIO_WRITE_OPCODE 0x01 // CUnit to SATA PHY MMIO Write Opcode
|
||||
|
||||
///
|
||||
/// SATA Controller Registers (D19:F0)
|
||||
///
|
||||
#define PCI_DEVICE_NUMBER_PCH_SATA 19
|
||||
#define PCI_FUNCTION_NUMBER_PCH_SATA 0
|
||||
|
||||
#define R_PCH_SATA_ID 0x00 // Identifiers
|
||||
#define B_PCH_SATA_ID_DID 0xFFFF0000 // Device ID
|
||||
#define B_PCH_SATA_ID_VID 0x0000FFFF // Vendor ID
|
||||
#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID
|
||||
#define V_PCH_SATA_DEVICE_ID_D_IDE 0x0F20 // Desktop IDE Mode (Ports 0 and 1)
|
||||
#define V_PCH_SATA_DEVICE_ID_D_AHCI 0x0F22 // Desktop AHCI Mode (Ports 0 and 1)
|
||||
#define V_PCH_SATA_DEVICE_ID_D_RAID 0x2822 // Desktop RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]
|
||||
|
||||
#define V_PCH_SATA_DEVICE_ID_M_IDE 0x0F21 // Mobile IDE Mode (Ports 0 and 1)
|
||||
#define V_PCH_SATA_DEVICE_ID_M_AHCI 0x0F23 // Mobile AHCI Mode (Ports 0 and 1)
|
||||
#define V_PCH_SATA_DEVICE_ID_M_RAID 0x282A // Mobile RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]
|
||||
|
||||
#define R_PCH_SATA_COMMAND 0x04 // Command
|
||||
#define B_PCH_SATA_COMMAND_INT_DIS BIT10 // Interrupt Disable
|
||||
#define B_PCH_SATA_COMMAND_FBE BIT9 // Fast Back-to-back Enable
|
||||
#define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable
|
||||
#define B_PCH_SATA_COMMAND_WCC BIT7 // Wait Cycle Enable
|
||||
#define B_PCH_SATA_COMMAND_PER BIT6 // Parity Error Response Enable
|
||||
#define B_PCH_SATA_COMMAND_VPS BIT5 // VGA Palette Snooping Enable
|
||||
#define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable
|
||||
#define B_PCH_SATA_COMMAND_SCE BIT3 // Special Cycle Enable
|
||||
#define B_PCH_SATA_COMMAND_BME BIT2 // Bus Master Enable
|
||||
#define B_PCH_SATA_COMMAND_MSE BIT1 // Memory Space Enable
|
||||
#define B_PCH_SATA_COMMAND_IOSE BIT0 // I/O Space Enable
|
||||
|
||||
#define R_PCH_SATA_PCISTS 0x06 // Device Status
|
||||
#define B_PCH_SATA_PCISTS_DPE BIT15 // Detected Parity Error
|
||||
#define B_PCH_SATA_PCISTS_SSE BIT14 // Signaled System Error
|
||||
#define B_PCH_SATA_PCISTS_RMA BIT13 // Received Master-Abort Status
|
||||
#define B_PCH_SATA_PCISTS_RTA BIT12 // Received Target-Abort Status
|
||||
#define B_PCH_SATA_PCISTS_STA BIT11 // Signaled Target-Abort Status
|
||||
#define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 | BIT9) // DEVSEL# Timing Status
|
||||
#define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected
|
||||
#define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List
|
||||
#define B_PCH_SATA_PCISTS_ITNS BIT3 // Interrupt Status
|
||||
|
||||
#define R_PCH_SATA_RID 0x08 // Revision ID (8 bits)
|
||||
|
||||
#define R_PCH_SATA_PI_REGISTER 0x09 // Programming Interface (8 bits)
|
||||
#define B_PCH_SATA_PI_REGISTER_SNC BIT3 // Secondary Mode Native Capable
|
||||
#define B_PCH_SATA_PI_REGISTER_SNE BIT2 // Secondary Mode Native Enable
|
||||
#define B_PCH_SATA_PI_REGISTER_PNC BIT1 // Primary Mode Native Capable
|
||||
#define B_PCH_SATA_PI_REGISTER_PNE BIT0 // Primary Mode Native Enable
|
||||
|
||||
#define R_PCH_SATA_CC 0x0A // Class Code
|
||||
#define B_PCH_SATA_CC_BCC 0xFF00 // Base Class Code
|
||||
#define B_PCH_SATA_CC_SCC 0x00FF // Sub Class Code
|
||||
#define V_PCH_SATA_CC_SCC_IDE 0x01
|
||||
#define V_PCH_SATA_CC_SCC_AHCI 0x06
|
||||
#define V_PCH_SATA_CC_SCC_RAID 0x04
|
||||
|
||||
#define R_PCH_SATA_CLS 0x0C // Cache Line Size (8 bits)
|
||||
#define B_PCH_SATA_CLS 0xFF
|
||||
|
||||
#define R_PCH_SATA_MLT 0x0D // Master Latency Timer (8 bits)
|
||||
#define B_PCH_SATA_MLT 0xFF
|
||||
|
||||
#define R_PCH_SATA_HTYPE 0x0E // Header Type
|
||||
#define B_PCH_SATA_HTYPE_MFD BIT7 // Multi-function Device
|
||||
#define B_PCH_SATA_HTYPE_HL 0x7F // Header Layout
|
||||
|
||||
#define R_PCH_SATA_PCMD_BAR 0x10 // Primary Command Block Base Address
|
||||
#define B_PCH_SATA_PCMD_BAR_BA 0x0000FFF8 // Base Address
|
||||
#define B_PCH_SATA_PCMD_BAR_RTE BIT0 // Resource Type Indicator
|
||||
|
||||
#define R_PCH_SATA_PCTL_BAR 0x14 // Primary Control Block Base Address
|
||||
#define B_PCH_SATA_PCTL_BAR_BA 0x0000FFFC // Base Address
|
||||
#define B_PCH_SATA_PCTL_BAR_RTE BIT0 // Resource Type Indicator
|
||||
|
||||
#define R_PCH_SATA_SCMD_BAR 0x18 // Secondary Command Block Base Address
|
||||
#define B_PCH_SATA_SCMD_BAR_BA 0x0000FFF8 // Base Address
|
||||
#define B_PCH_SATA_SCMD_BAR_RTE BIT0 // Resource Type Indicator
|
||||
|
||||
#define R_PCH_SATA_SCTL_BAR 0x1C // Secondary Control Block Base Address
|
||||
#define B_PCH_SATA_SCTL_BAR_BA 0x0000FFFC // Base Address
|
||||
#define B_PCH_SATA_SCTL_BAR_RTE BIT0 // Resource Type Indicator
|
||||
|
||||
#define R_PCH_SATA_LBAR 0x20 // Legacy IDE Base Address / AHCI Index Data Pair Base Address
|
||||
#define B_PCH_SATA_LBAR_BA 0x0000FFE0 // Base Address
|
||||
#define B_PCH_SATA_LBAR_BA4 BIT4 // Base Address 4
|
||||
#define B_PCH_SATA_LBAR_RTE BIT0 // Resource Type Indicator
|
||||
|
||||
#define R_PCH_SATA_SIDPBA 0x24 // Serial ATA Index Data Pair Base Address
|
||||
#define R_PCH_SATA_ABAR 0x24 // AHCI Base Address
|
||||
#define B_PCH_SATA_ABAR_BA 0xFFFFF800 // AHCI Memory Base Address (When CC.SCC not equal 0x01)
|
||||
#define V_PCH_SATA_ABAR_LENGTH 0x800 // AHCI Memory Length (When CC.SCC not equal 0x01)
|
||||
#define N_PCH_SATA_ABAR_ALIGNMENT 11 // AHCI Base Address Alignment (When CC.SCC not equal 0x01)
|
||||
#define B_PCH_SATA_SIDPBA_BA 0x0000FFF0 // Serial ATA Index Data Pair IO Base Address (When CC.SCC equal 0x01)
|
||||
#define V_PCH_SATA_SIDPBA_LENGTH 0x10 // Serial ATA Index Data Pair IO Length (When CC.SCC equal 0x01)
|
||||
#define N_PCH_SATA_SIDPBA_ALIGNMENT 4 // Serial ATA Index Data Pair Base Address Alignment (When CC.SCC not equal 0x01)
|
||||
#define B_PCH_SATA_ABAR_PF BIT3 // Prefetchable
|
||||
#define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type
|
||||
#define B_PCH_SATA_ABAR_RTE BIT0 // Resource Type Indicator
|
||||
|
||||
#define R_PCH_SATA_SS 0x2C // Sub System Identifiers
|
||||
#define B_PCH_SATA_SS_SSID 0xFFFF0000 // Subsystem ID
|
||||
#define B_PCH_SATA_SS_SSVID 0x0000FFFF // Subsystem Vendor ID
|
||||
|
||||
#define R_PCH_SATA_AHCI_CAP_PTR 0x34 // Capabilities Pointer (8 bits)
|
||||
#define B_PCH_SATA_AHCI_CAP_PTR 0xFF
|
||||
|
||||
#define R_PCH_SATA_INTR 0x3C // Interrupt Information
|
||||
#define B_PCH_SATA_INTR_IPIN 0xFFFF0000 // Interrupt Pin
|
||||
#define B_PCH_SATA_INTR_ILINE 0x0000FFFF // Interrupt Line
|
||||
|
||||
#define R_PCH_SATA_PMCS 0x74 // PCI Power Management Control and Status
|
||||
#define B_PCH_SATA_PMCS_PMES BIT15 // PME Status
|
||||
#define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable
|
||||
#define B_PCH_SATA_PMCS_NSFRST BIT3 // No Soft Reset
|
||||
#define V_PCH_SATA_PMCS_NSFRST_1 0x01
|
||||
#define V_PCH_SATA_PMCS_NSFRST_0 0x00
|
||||
#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State
|
||||
#define V_PCH_SATA_PMCS_PS_3 0x03
|
||||
#define V_PCH_SATA_PMCS_PS_0 0x00
|
||||
|
||||
#define R_PCH_SATA_MAP 0x90 // Port Mapping Register
|
||||
#define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable
|
||||
#define B_PCH_SATA_PORT6_DISABLED BIT14
|
||||
#define B_PCH_SATA_PORT5_DISABLED BIT13
|
||||
#define B_PCH_SATA_PORT4_DISABLED BIT12
|
||||
#define B_PCH_SATA_PORT3_DISABLED BIT11
|
||||
#define B_PCH_SATA_PORT2_DISABLED BIT10
|
||||
#define B_PCH_SATA_PORT1_DISABLED BIT9
|
||||
#define B_PCH_SATA_PORT0_DISABLED BIT8
|
||||
#define B_PCH_SATA_MAP_SMS_MASK (BIT7 | BIT6) // SATA Mode Select
|
||||
#define V_PCH_SATA_MAP_SMS_IDE 0x00
|
||||
#define V_PCH_SATA_MAP_SMS_AHCI 0x40
|
||||
#define V_PCH_SATA_MAP_SMS_RAID 0x80
|
||||
#define B_PCH_SATA_PORT_TO_CONTROLLER_CFG BIT5 // SATA Port-to-Controller Configuration
|
||||
|
||||
#define R_PCH_SATA_PCS 0x92 // Port Control and Status
|
||||
#define S_PCH_SATA_PCS 0x2
|
||||
#define B_PCH_SATA_PCS_OOB_RETRY BIT15 // OOB Retry Mode
|
||||
#define B_PCH_SATA_PCS_PORT6_DET BIT14 // Port 6 Present
|
||||
#define B_PCH_SATA_PCS_PORT5_DET BIT13 // Port 5 Present
|
||||
#define B_PCH_SATA_PCS_PORT4_DET BIT12 // Port 4 Present
|
||||
#define B_PCH_SATA_PCS_PORT3_DET BIT11 // Port 3 Present
|
||||
#define B_PCH_SATA_PCS_PORT2_DET BIT10 // Port 2 Present
|
||||
#define B_PCH_SATA_PCS_PORT1_DET BIT9 // Port 1 Present
|
||||
#define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present
|
||||
#define B_PCH_SATA_PCS_PORT5_EN BIT5 // Port 5 Enabled
|
||||
#define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled
|
||||
#define B_PCH_SATA_PCS_PORT3_EN BIT3 // Port 3 Enabled
|
||||
#define B_PCH_SATA_PCS_PORT2_EN BIT2 // Port 2 Enabled
|
||||
#define B_PCH_SATA_PCS_PORT1_EN BIT1 // Port 1 Enabled
|
||||
#define B_PCH_SATA_PCS_PORT0_EN BIT0 // Port 0 Enabled
|
||||
|
||||
#define R_PCH_SATA_AHCI_PI 0x0C // Ports Implemented
|
||||
#define B_PCH_SATA_PORT_MASK 0x3F
|
||||
#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 // Port 5 Implemented
|
||||
#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented
|
||||
#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 // Port 3 Implemented
|
||||
#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 // Port 2 Implemented
|
||||
#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 // Port 1 Implemented
|
||||
#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 // Port 0 Implemented
|
||||
|
||||
#define R_PCH_SATA_AHCI_P0SSTS 0x128 // Port 0 Serial ATA Status
|
||||
#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 // Port 1 Serial ATA Status
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_IPM 0x00000F00 // Interface Power Management
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_SPD 0x000000F0 // Current Interface Speed
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_DET 0x0000000F // Device Detection
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003
|
||||
#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004
|
||||
|
||||
//
|
||||
// Macros of VLV capabilities for SATA controller which are used by SATA controller driver
|
||||
//
|
||||
//
|
||||
//
|
||||
// Define the individual capabilities of each SATA controller
|
||||
//
|
||||
#define PCH_SATA_MAX_CONTROLLERS 1 // Max SATA controllers number supported
|
||||
#define PCH_SATA_MAX_DEVICES 2 // Max SATA devices number of single SATA channel
|
||||
#define PCH_IDE_MAX_CHANNELS 2 // Max IDE channels number of single SATA controller
|
||||
#define PCH_IDE_MAX_DEVICES 2 // Max IDE devices number of single SATA channel
|
||||
#define PCH_AHCI_MAX_PORTS 2 // Max number of SATA ports in VLV
|
||||
#define PCH_IDE_MAX_PORTS 2 // Max number of IDE ports in VLV
|
||||
|
||||
//
|
||||
// GPIOS_14 SATA0GP is the SATA port 0 reset pin.
|
||||
//
|
||||
#define PCH_GPIO_SATA_PORT0_RESET 14
|
||||
//
|
||||
// GPIOS_15 SATA1GP is the SATA port 1 reset pin.
|
||||
//
|
||||
#define PCH_GPIO_SATA_PORT1_RESET 15
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,59 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PchRegsScc.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Register names for VLV SCC module.
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
--*/
|
||||
#ifndef _PCH_REGS_SCC_H_
|
||||
#define _PCH_REGS_SCC_H_
|
||||
|
||||
|
||||
//
|
||||
// SCC Modules Registers
|
||||
//
|
||||
|
||||
//
|
||||
// SCC SDIO Modules
|
||||
// PCI Config Space Registers
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_0 16
|
||||
#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_1 17
|
||||
#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_2 18
|
||||
#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_3 23
|
||||
|
||||
#define PCI_FUNCTION_NUMBER_PCH_SCC_SDIO 0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,155 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchRegsSmbus.h
|
||||
|
||||
@brief
|
||||
Register names for VLV Smbus Device.
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_REGS_SMBUS_H_
|
||||
#define _PCH_REGS_SMBUS_H_
|
||||
|
||||
///
|
||||
/// SMBus Controller Registers (D31:F3)
|
||||
///
|
||||
#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
|
||||
#define PCI_FUNCTION_NUMBER_PCH_SMBUS 3
|
||||
|
||||
#define R_PCH_SMBUS_VENDOR_ID 0x00 // Vendor ID
|
||||
#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
|
||||
|
||||
#define R_PCH_SMBUS_DEVICE_ID 0x02 // Device ID
|
||||
#define V_PCH_SMBUS_DEVICE_ID 0x0F12
|
||||
|
||||
#define R_PCH_SMBUS_PCICMD 0x04 // CMD register enables/disables, Memory/IO space access and interrupt
|
||||
#define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 // Interrupt Disable
|
||||
#define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0'
|
||||
#define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 // SERR Enable - reserved as '0'
|
||||
#define B_PCH_SMBUS_PCICMD_WCC BIT7 // Wait Cycle Control - reserved as '0'
|
||||
#define B_PCH_SMBUS_PCICMD_PER BIT6 // Parity Error - reserved as '0'
|
||||
#define B_PCH_SMBUS_PCICMD_VPS BIT5 // VGA Palette Snoop - reserved as '0'
|
||||
#define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'
|
||||
#define B_PCH_SMBUS_PCICMD_SCE BIT3 // Special Cycle Enable - reserved as '0'
|
||||
#define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0'
|
||||
#define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable
|
||||
#define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable
|
||||
|
||||
#define R_PCH_SMBUS_BASE 0x20 // The I/O memory bar
|
||||
#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 // Base Address
|
||||
#define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator
|
||||
|
||||
#define R_PCH_SMBUS_SVID 0x2C // Subsystem Vendor ID
|
||||
#define B_PCH_SMBUS_SVID 0xFFFF // Subsystem Vendor ID
|
||||
|
||||
//
|
||||
// SMBus I/O Registers
|
||||
//
|
||||
#define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W
|
||||
#define B_PCH_SMBUS_HSTS_ALL 0xFF
|
||||
#define B_PCH_SMBUS_BYTE_DONE_STS BIT7 // Byte Done Status
|
||||
#define B_PCH_SMBUS_IUS BIT6 // In Use Status
|
||||
#define B_PCH_SMBUS_SMBALERT_STS BIT5 // SMBUS Alert
|
||||
#define B_PCH_SMBUS_FAIL BIT4 // Failed
|
||||
#define B_PCH_SMBUS_BERR BIT3 // Bus Error
|
||||
#define B_PCH_SMBUS_DERR BIT2 // Device Error
|
||||
#define B_PCH_SMBUS_ERRORS (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)
|
||||
#define B_PCH_SMBUS_INTR BIT1 // Interrupt
|
||||
#define B_PCH_SMBUS_HBSY BIT0 // Host Busy
|
||||
|
||||
#define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W
|
||||
#define B_PCH_SMBUS_PEC_EN BIT7 // Packet Error Checking Enable
|
||||
#define B_PCH_SMBUS_START BIT6 // Start
|
||||
#define B_PCH_SMBUS_LAST_BYTE BIT5 // Last Byte
|
||||
#define B_PCH_SMBUS_SMB_CMD 0x1C // SMB Command
|
||||
#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C // Block Process
|
||||
#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 // I2C Read
|
||||
#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block
|
||||
#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 // Process Call
|
||||
#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C // Word Data
|
||||
#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data
|
||||
#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 // Byte
|
||||
#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 // Quick
|
||||
#define B_PCH_SMBUS_KILL BIT1 // Kill
|
||||
#define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable
|
||||
|
||||
#define R_PCH_SMBUS_HCMD 0x03 // Host Command Register R/W
|
||||
#define B_PCH_SMBUS_HCMD 0xFF // Command to be transmitted
|
||||
|
||||
#define R_PCH_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W
|
||||
#define B_PCH_SMBUS_ADDRESS 0xFE // 7-bit address of the targeted slave
|
||||
#define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = write
|
||||
#define B_PCH_SMBUS_RW_SEL_READ 0x01 // Read
|
||||
#define B_PCH_SMBUS_RW_SEL_WRITE 0x00 // Write
|
||||
//
|
||||
#define R_PCH_SMBUS_HD0 0x05 // Data 0 Register R/W
|
||||
#define R_PCH_SMBUS_HD1 0x06 // Data 1 Register R/W
|
||||
#define R_PCH_SMBUS_HBD 0x07 // Host Block Data Register R/W
|
||||
#define R_PCH_SMBUS_PEC 0x08 // Packet Error Check Data Register R/W
|
||||
|
||||
#define R_PCH_SMBUS_RSA 0x09 // Receive Slave Address Register R/W
|
||||
#define B_PCH_SMBUS_SLAVE_ADDR 0x7F // TCO slave address (Not used, reserved)
|
||||
|
||||
#define R_PCH_SMBUS_SD 0x0A // Receive Slave Data Register R/W
|
||||
|
||||
#define R_PCH_SMBUS_AUXS 0x0C // Auxiliary Status Register R/WC
|
||||
#define B_PCH_SMBUS_CRCE BIT0 // CRC Error
|
||||
//
|
||||
#define R_PCH_SMBUS_AUXC 0x0D // Auxiliary Control Register R/W
|
||||
#define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer
|
||||
#define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC
|
||||
|
||||
#define R_PCH_SMBUS_SMLC 0x0E // SMLINK Pin Control Register R/W
|
||||
#define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported
|
||||
#define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported
|
||||
#define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported
|
||||
|
||||
|
||||
#define R_PCH_SMBUS_SMBC 0x0F // SMBus Pin Control Register R/W
|
||||
#define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control
|
||||
#define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status
|
||||
#define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status
|
||||
|
||||
#define R_PCH_SMBUS_SSTS 0x10 // Slave Status Register R/WC
|
||||
#define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status
|
||||
|
||||
#define R_PCH_SMBUS_SCMD 0x11 // Slave Command Register R/W
|
||||
#define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported
|
||||
#define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable
|
||||
#define B_PCH_SMBUS_HOST_NOTIFY_INTREN BIT0 // Host Notify Interrupt Enable
|
||||
|
||||
#define R_PCH_SMBUS_NDA 0x14 // Notify Device Address Register RO
|
||||
#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE // Device Address
|
||||
|
||||
#define R_PCH_SMBUS_NDLB 0x16 // Notify Data Low Byte Register RO
|
||||
#define R_PCH_SMBUS_NDHB 0x17 // Notify Data High Byte Register RO
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,119 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchRegsSpi.h
|
||||
|
||||
@brief
|
||||
Register names for PCH SPI device.
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_REGS_SPI_H_
|
||||
#define _PCH_REGS_SPI_H_
|
||||
|
||||
///
|
||||
/// SPI Host Interface Registers
|
||||
///
|
||||
|
||||
#define R_PCH_SPI_HSFS 0x04 // Hardware Sequencing Flash Status Register (16bits)
|
||||
#define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down
|
||||
#define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid
|
||||
#define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status
|
||||
#define B_PCH_SPI_HSFS_SCIP BIT5 // SPI Cycle in Progress
|
||||
#define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) // Block / Sector Erase Size
|
||||
#define V_PCH_SPI_HSFS_BERASE_256B 0x00 // Block/Sector = 256 Bytes
|
||||
#define V_PCH_SPI_HSFS_BERASE_4K 0x01 // Block/Sector = 4K Bytes
|
||||
#define V_PCH_SPI_HSFS_BERASE_8K 0x10 // Block/Sector = 8K Bytes
|
||||
#define V_PCH_SPI_HSFS_BERASE_64K 0x11 // Block/Sector = 64K Bytes
|
||||
#define B_PCH_SPI_HSFS_AEL BIT2 // Access Error Log
|
||||
#define B_PCH_SPI_HSFS_FCERR BIT1 // Flash Cycle Error
|
||||
#define B_PCH_SPI_HSFS_FDONE BIT0 // Flash Cycle Done
|
||||
|
||||
#define R_PCH_SPI_PR0 0x74 // Protected Region 0 Register
|
||||
#define B_PCH_SPI_PR0_WPE BIT31 // Write Protection Enable
|
||||
#define B_PCH_SPI_PR0_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]
|
||||
#define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
|
||||
#define B_PCH_SPI_PR0_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]
|
||||
|
||||
#define R_PCH_SPI_PREOP 0x94 // Prefix Opcode Configuration Register (16 bits)
|
||||
#define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask
|
||||
#define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask
|
||||
|
||||
#define R_PCH_SPI_OPTYPE 0x96 // Opcode Type Configuration
|
||||
#define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
|
||||
#define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) // Opcode Type 6 Mask
|
||||
#define B_PCH_SPI_OPTYPE5_MASK (BIT11 | BIT10) // Opcode Type 5 Mask
|
||||
#define B_PCH_SPI_OPTYPE4_MASK (BIT9 | BIT8) // Opcode Type 4 Mask
|
||||
#define B_PCH_SPI_OPTYPE3_MASK (BIT7 | BIT6) // Opcode Type 3 Mask
|
||||
#define B_PCH_SPI_OPTYPE2_MASK (BIT5 | BIT4) // Opcode Type 2 Mask
|
||||
#define B_PCH_SPI_OPTYPE1_MASK (BIT3 | BIT2) // Opcode Type 1 Mask
|
||||
#define B_PCH_SPI_OPTYPE0_MASK (BIT1 | BIT0) // Opcode Type 0 Mask
|
||||
#define V_PCH_SPI_OPTYPE_RDNOADDR 0x00 // Read cycle type without address
|
||||
#define V_PCH_SPI_OPTYPE_WRNOADDR 0x01 // Write cycle type without address
|
||||
#define V_PCH_SPI_OPTYPE_RDADDR 0x02 // Address required; Read cycle type
|
||||
#define V_PCH_SPI_OPTYPE_WRADDR 0x03 // Address required; Write cycle type
|
||||
|
||||
#define R_PCH_SPI_OPMENU0 0x98 // Opcode Menu Configuration 0 (32bits)
|
||||
#define R_PCH_SPI_OPMENU1 0x9C // Opcode Menu Configuration 1 (32bits)
|
||||
|
||||
#define R_PCH_SPI_IND_LOCK 0xA4 // Indvidual Lock
|
||||
#define B_PCH_SPI_IND_LOCK_PR0 BIT2 // PR0 LockDown
|
||||
|
||||
|
||||
#define R_PCH_SPI_FDOC 0xB0 // Flash Descriptor Observability Control Register (32 bits)
|
||||
#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select
|
||||
#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 // Flash Signature and Descriptor Map
|
||||
#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 // Component
|
||||
#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 // Region
|
||||
#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 // Master
|
||||
#define V_PCH_SPI_FDOC_FDSS_VLVS 0x4000 // Soft Straps
|
||||
#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC // Flash Descriptor Section Index
|
||||
|
||||
#define R_PCH_SPI_FDOD 0xB4 // Flash Descriptor Observability Data Register (32 bits)
|
||||
|
||||
#define R_PCH_SPI_BCR 0xFC // BIOS Control Register
|
||||
#define S_PCH_SPI_BCR 1
|
||||
#define B_PCH_SPI_BCR_SMM_BWP BIT5 // SMM BIOS Write Protect Disable
|
||||
#define B_PCH_SPI_BCR_SRC (BIT3 | BIT2) // SPI Read Configuration (SRC)
|
||||
#define V_PCH_SPI_BCR_SRC_PREF_EN_CACHE_EN 0x08 // Prefetch Enable, Cache Enable
|
||||
#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 // Prefetch Disable, Cache Disable
|
||||
#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_EN 0x00 // Prefetch Disable, Cache Enable
|
||||
#define B_PCH_SPI_BCR_BLE BIT1 // Lock Enable (LE)
|
||||
#define B_PCH_SPI_BCR_BIOSWE BIT0 // Write Protect Disable (WPD)
|
||||
#define N_PCH_SPI_BCR_BLE 1
|
||||
#define N_PCH_SPI_BCR_BIOSWE 0
|
||||
|
||||
//
|
||||
// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
|
||||
//
|
||||
#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 // Flash Valid Signature
|
||||
#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,98 @@
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchRegsUsb.h
|
||||
|
||||
@brief
|
||||
Register names for PCH USB devices.
|
||||
|
||||
Conventions:
|
||||
|
||||
- Prefixes:
|
||||
Definitions beginning with "R_" are registers
|
||||
Definitions beginning with "B_" are bits within registers
|
||||
Definitions beginning with "V_" are meaningful values of bits within the registers
|
||||
Definitions beginning with "S_" are register sizes
|
||||
Definitions beginning with "N_" are the bit position
|
||||
- In general, PCH registers are denoted by "_PCH_" in register names
|
||||
- Registers / bits that are different between PCH generations are denoted by
|
||||
"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
|
||||
- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
|
||||
at the end of the register/bit names
|
||||
- Registers / bits of new devices introduced in a PCH generation will be just named
|
||||
as "_PCH_" without <generation_name> inserted.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_REGS_USB_H_
|
||||
#define _PCH_REGS_USB_H_
|
||||
|
||||
///
|
||||
/// USB Definitions
|
||||
///
|
||||
|
||||
typedef enum {
|
||||
PchEhci1 = 0,
|
||||
PchEhciControllerMax
|
||||
} PCH_USB20_CONTROLLER_TYPE;
|
||||
|
||||
#define PCH_USB_MAX_PHYSICAL_PORTS 4 /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.
|
||||
#define PCH_EHCI_MAX_PORTS 4 /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.
|
||||
#define PCH_HSIC_MAX_PORTS 2
|
||||
#define PCH_XHCI_MAX_USB3_PORTS 1
|
||||
|
||||
#define PCI_DEVICE_NUMBER_PCH_USB 29
|
||||
#define PCI_FUNCTION_NUMBER_PCH_EHCI 0
|
||||
|
||||
#define R_PCH_USB_VENDOR_ID 0x00 // Vendor ID
|
||||
#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID
|
||||
|
||||
#define R_PCH_USB_DEVICE_ID 0x02 // Device ID
|
||||
#define V_PCH_USB_DEVICE_ID_0 0x0F34 // EHCI#1
|
||||
|
||||
#define R_PCH_EHCI_SVID 0x2C // USB2 Subsystem Vendor ID
|
||||
#define B_PCH_EHCI_SVID 0xFFFF // USB2 Subsystem Vendor ID Mask
|
||||
|
||||
#define R_PCH_EHCI_PWR_CNTL_STS 0x54 // Power Management Control / Status
|
||||
#define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 // PME Status
|
||||
#define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) // Data Scale
|
||||
#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) // Data Select
|
||||
#define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 // Power Enable
|
||||
#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State
|
||||
#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0 0 // D0 State
|
||||
#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) // D3 Hot State
|
||||
|
||||
///
|
||||
/// USB3 (XHCI) related definitions
|
||||
///
|
||||
#define PCI_DEVICE_NUMBER_PCH_XHCI 20
|
||||
#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
|
||||
//
|
||||
/////
|
||||
///// XHCI PCI Config Space registers
|
||||
/////
|
||||
|
||||
#define R_PCH_XHCI_SVID 0x2C
|
||||
#define B_PCH_XHCI_SVID 0xFFFF
|
||||
|
||||
|
||||
#define R_PCH_XHCI_PWR_CNTL_STS 0x74
|
||||
#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
|
||||
#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
|
||||
#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9)
|
||||
#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
|
||||
#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
|
||||
#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,81 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchInit.h
|
||||
|
||||
@brief
|
||||
This file defines the PCH Init PPI
|
||||
|
||||
**/
|
||||
#ifndef _PCH_INIT_H_
|
||||
#define _PCH_INIT_H_
|
||||
|
||||
//
|
||||
// Define the PCH Init PPI GUID
|
||||
//
|
||||
|
||||
|
||||
#include <Protocol/PchPlatformPolicy.h>
|
||||
#define PCH_INIT_PPI_GUID \
|
||||
{ \
|
||||
0x9ea894a, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x95 \
|
||||
}
|
||||
extern EFI_GUID gPchInitPpiGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _PCH_INIT_PPI PCH_INIT_PPI;
|
||||
|
||||
///
|
||||
/// Data structure definitions
|
||||
///
|
||||
typedef enum _CPU_STRAP_OPERATION {
|
||||
GetCpuStrapSetData,
|
||||
SetCpuStrapSetData,
|
||||
LockCpuStrapSetData
|
||||
} CPU_STRAP_OPERATION;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PCH_USB_INIT) (
|
||||
IN EFI_PEI_SERVICES **PeiServices
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
The function performing USB init in PEI phase. This could be used by USB recovery
|
||||
or debug features that need USB initialization during PEI phase.
|
||||
Note: Before executing this function, please be sure that PCH_INIT_PPI.Initialize
|
||||
has been done and PchUsbPolicyPpi has been installed.
|
||||
|
||||
@param[in] PeiServices General purpose services available to every PEIM
|
||||
|
||||
@retval EFI_SUCCESS The function completed successfully
|
||||
@retval Others All other error conditions encountered result in an ASSERT.
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
///
|
||||
/// PCH_INIT_PPI Structure Definition
|
||||
///
|
||||
struct _PCH_INIT_PPI {
|
||||
PCH_USB_INIT UsbInit;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,40 @@
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PchPeiInit.h
|
||||
|
||||
Abstract:
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PCH_PEI_INIT_H_
|
||||
#define _PCH_PEI_INIT_H_
|
||||
|
||||
//
|
||||
// Define the PCH PEI Init PPI GUID
|
||||
//
|
||||
#define PCH_PEI_INIT_PPI_GUID \
|
||||
{ \
|
||||
0xACB93B08, 0x5CDC, 0x4A8F, 0x93, 0xD4, 0x6, 0xE3, 0x42, 0xDF, 0x18, 0x2E \
|
||||
}
|
||||
|
||||
//
|
||||
// Extern the GUID for PPI users.
|
||||
//
|
||||
extern EFI_GUID gPchPeiInitPpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,167 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchPlatformPolicy.h
|
||||
|
||||
@brief
|
||||
PCH policy PPI produced by a platform driver specifying various
|
||||
expected PCH settings. This PPI is consumed by the PCH PEI modules.
|
||||
|
||||
**/
|
||||
#ifndef PCH_PLATFORM_POLICY_H_
|
||||
#define PCH_PLATFORM_POLICY_H_
|
||||
//
|
||||
// External include files do NOT need to be explicitly specified in real EDKII
|
||||
// environment
|
||||
//
|
||||
|
||||
|
||||
#include "PchRegs.h"
|
||||
|
||||
//
|
||||
#define PCH_PLATFORM_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \
|
||||
}
|
||||
|
||||
extern EFI_GUID gPchPlatformPolicyPpiGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;
|
||||
|
||||
///
|
||||
/// PPI revision number
|
||||
/// Any backwards compatible changes to this PPI will result in an update in the revision number
|
||||
/// Major changes will require publication of a new PPI
|
||||
///
|
||||
/// Revision 1: Original version
|
||||
///
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_1 1
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_2 2
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_3 3
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_4 4
|
||||
#define PCH_PLATFORM_POLICY_PPI_REVISION_5 5
|
||||
//
|
||||
// Generic definitions for device enabling/disabling used by PCH code.
|
||||
//
|
||||
#define PCH_DEVICE_ENABLE 1
|
||||
#define PCH_DEVICE_DISABLE 0
|
||||
|
||||
typedef struct {
|
||||
UINT8 ThermalDataReportEnable : 1; // OBSOLETE from Revision 5 !!! DO NOT USE !!!
|
||||
UINT8 MchTempReadEnable : 1;
|
||||
UINT8 PchTempReadEnable : 1;
|
||||
UINT8 CpuEnergyReadEnable : 1;
|
||||
UINT8 CpuTempReadEnable : 1;
|
||||
UINT8 Cpu2TempReadEnable : 1;
|
||||
UINT8 TsOnDimmEnable : 1;
|
||||
UINT8 Dimm1TempReadEnable : 1;
|
||||
|
||||
UINT8 Dimm2TempReadEnable : 1;
|
||||
UINT8 Dimm3TempReadEnable : 1;
|
||||
UINT8 Dimm4TempReadEnable : 1;
|
||||
UINT8 Rsvdbits : 5;
|
||||
} PCH_THERMAL_REPORT_CONTROL;
|
||||
//
|
||||
// ---------------------------- HPET Config -----------------------------
|
||||
//
|
||||
typedef struct {
|
||||
BOOLEAN Enable; /// Determines if enable HPET function
|
||||
UINT32 Base; /// The HPET base address
|
||||
} PCH_HPET_CONFIG;
|
||||
|
||||
|
||||
///
|
||||
/// ---------------------------- SATA Config -----------------------------
|
||||
///
|
||||
typedef enum {
|
||||
PchSataModeIde,
|
||||
PchSataModeAhci,
|
||||
PchSataModeRaid,
|
||||
PchSataModeMax
|
||||
} PCH_SATA_MODE;
|
||||
|
||||
///
|
||||
/// ---------------------------- PCI Express Config -----------------------------
|
||||
///
|
||||
typedef enum {
|
||||
PchPcieAuto,
|
||||
PchPcieGen1,
|
||||
PchPcieGen2
|
||||
} PCH_PCIE_SPEED;
|
||||
|
||||
typedef struct {
|
||||
PCH_PCIE_SPEED PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];
|
||||
} PCH_PCIE_CONFIG;
|
||||
|
||||
///
|
||||
/// ---------------------------- IO APIC Config -----------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 IoApicId;
|
||||
} PCH_IOAPIC_CONFIG;
|
||||
|
||||
///
|
||||
/// --------------------- Low Power Input Output Config ------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled
|
||||
UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled
|
||||
UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled
|
||||
UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled
|
||||
UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled
|
||||
UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled
|
||||
UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled
|
||||
UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled
|
||||
UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled
|
||||
UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled
|
||||
UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled
|
||||
UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled
|
||||
UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled
|
||||
UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled
|
||||
UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled
|
||||
UINT8 Rsvdbits : 2;
|
||||
} PEI_PCH_LPSS_CONFIG;
|
||||
|
||||
///
|
||||
/// ------------ General PCH Platform Policy PPI definition ------------
|
||||
///
|
||||
struct _PCH_PLATFORM_POLICY_PPI {
|
||||
UINT8 Revision;
|
||||
UINT8 BusNumber; // Bus Number of the PCH device
|
||||
UINT32 SpiBase; // SPI Base Address.
|
||||
UINT32 PmcBase; // PMC Base Address.
|
||||
UINT32 SmbmBase; // SMB Memory Base Address.
|
||||
UINT32 IoBase; // IO Base Address.
|
||||
UINT32 IlbBase; // Intel Legacy Block Base Address.
|
||||
UINT32 PUnitBase; // PUnit Base Address.
|
||||
UINT32 Rcba; // Root Complex Base Address.
|
||||
UINT32 MphyBase; // MPHY Base Address.
|
||||
UINT16 AcpiBase; // ACPI I/O Base address.
|
||||
UINT16 GpioBase; // GPIO Base address
|
||||
PCH_HPET_CONFIG *HpetConfig;
|
||||
PCH_SATA_MODE SataMode;
|
||||
PCH_PCIE_CONFIG *PcieConfig;
|
||||
PCH_IOAPIC_CONFIG *IoApicConfig;
|
||||
PEI_PCH_LPSS_CONFIG *LpssConfig;
|
||||
BOOLEAN EnableRmh; // Determines if enable USB RMH function
|
||||
BOOLEAN EhciPllCfgEnable;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,75 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchUsbPolicy.h
|
||||
|
||||
@brief
|
||||
PCH Usb policy PPI produced by a platform driver specifying
|
||||
various expected PCH Usb settings. This PPI is consumed by the
|
||||
PCH PEI drivers.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_USB_POLICY_H_
|
||||
#define _PCH_USB_POLICY_H_
|
||||
|
||||
//
|
||||
// PCH Usb policy provided by platform for PEI phase
|
||||
//
|
||||
|
||||
#ifndef ECP_FLAG
|
||||
#include <PiPei.h>
|
||||
#endif
|
||||
|
||||
#include "PchRegs.h"
|
||||
#include <Protocol/PchPlatformPolicy.h>
|
||||
|
||||
#define PCH_USB_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0xc02b0573, 0x2b4e, 0x4a31, 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c \
|
||||
}
|
||||
|
||||
extern EFI_GUID gPchUsbPolicyPpiGuid;
|
||||
|
||||
typedef struct _PCH_USB_POLICY_PPI PCH_USB_POLICY_PPI;
|
||||
|
||||
///
|
||||
/// PPI revision number
|
||||
/// Any backwards compatible changes to this PPI will result in an update in the revision number
|
||||
/// Major changes will require publication of a new PPI
|
||||
///
|
||||
/// Revision 1: Original version
|
||||
///
|
||||
#define PCH_USB_POLICY_PPI_REVISION_1 1
|
||||
|
||||
///
|
||||
/// Generic definitions for device enabling/disabling used by PCH code.
|
||||
///
|
||||
#define PCH_DEVICE_ENABLE 1
|
||||
#define PCH_DEVICE_DISABLE 0
|
||||
|
||||
#define EHCI_MODE 1
|
||||
|
||||
struct _PCH_USB_POLICY_PPI {
|
||||
UINT8 Revision;
|
||||
PCH_USB_CONFIG *UsbConfig;
|
||||
UINT8 Mode;
|
||||
UINTN EhciMemBaseAddr;
|
||||
UINT32 EhciMemLength;
|
||||
UINTN XhciMemBaseAddr;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,236 @@
|
||||
/** @file
|
||||
Block IO protocol as defined in the UEFI 2.0 specification.
|
||||
|
||||
The Block IO protocol is used to abstract block devices like hard drives,
|
||||
DVD-ROMs and floppy drives.
|
||||
|
||||
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __PEI_BLOCK_IO_H__
|
||||
#define __PEI_BLOCK_IO_H__
|
||||
// {BC5FA650-EDBB-4d0d-B3A3-D98907F847DF}
|
||||
#ifndef ECP_FLAG
|
||||
#define PEI_BLOCK_IO_PPI_GUID \
|
||||
{ \
|
||||
0xbc5fa650, 0xedbb, 0x4d0d, { 0xb3, 0xa3, 0xd9, 0x89, 0x7, 0xf8, 0x47, 0xdf } \
|
||||
}
|
||||
#endif
|
||||
typedef struct _PEI_BLOCK_IO_PPI PEI_BLOCK_IO_PPI;
|
||||
|
||||
|
||||
/**
|
||||
Reset the Block Device.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
@param ExtendedVerification Driver may perform diagnostics on reset.
|
||||
|
||||
@retval EFI_SUCCESS The device was reset.
|
||||
@retval EFI_DEVICE_ERROR The device is not functioning properly and could
|
||||
not be reset.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_BLOCK_RESET)(
|
||||
IN PEI_BLOCK_IO_PPI *This,
|
||||
IN BOOLEAN ExtendedVerification
|
||||
);
|
||||
|
||||
/**
|
||||
Read BufferSize bytes from Lba into Buffer.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
@param MediaId Id of the media, changes every time the media is replaced.
|
||||
@param Lba The starting Logical Block Address to read from
|
||||
@param BufferSize Size of Buffer, must be a multiple of device block size.
|
||||
@param Buffer A pointer to the destination buffer for the data. The caller is
|
||||
responsible for either having implicit or explicit ownership of the buffer.
|
||||
|
||||
@retval EFI_SUCCESS The data was read correctly from the device.
|
||||
@retval EFI_DEVICE_ERROR The device reported an error while performing the read.
|
||||
@retval EFI_NO_MEDIA There is no media in the device.
|
||||
@retval EFI_MEDIA_CHANGED The MediaId does not matched the current device.
|
||||
@retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
|
||||
@retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
|
||||
or the buffer is not on proper alignment.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_BLOCK_READ)(
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_BLOCK_IO_PPI *This,
|
||||
IN UINT32 MediaId,
|
||||
IN EFI_LBA Lba,
|
||||
IN UINTN BufferSize,
|
||||
OUT VOID *Buffer
|
||||
);
|
||||
|
||||
/**
|
||||
Write BufferSize bytes from Lba into Buffer.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
@param MediaId The media ID that the write request is for.
|
||||
@param Lba The starting logical block address to be written. The caller is
|
||||
responsible for writing to only legitimate locations.
|
||||
@param BufferSize Size of Buffer, must be a multiple of device block size.
|
||||
@param Buffer A pointer to the source buffer for the data.
|
||||
|
||||
@retval EFI_SUCCESS The data was written correctly to the device.
|
||||
@retval EFI_WRITE_PROTECTED The device can not be written to.
|
||||
@retval EFI_DEVICE_ERROR The device reported an error while performing the write.
|
||||
@retval EFI_NO_MEDIA There is no media in the device.
|
||||
@retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device.
|
||||
@retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device.
|
||||
@retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
|
||||
or the buffer is not on proper alignment.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_BLOCK_WRITE)(
|
||||
IN EFI_PEI_SERVICES **PeiServices,
|
||||
IN PEI_BLOCK_IO_PPI *This,
|
||||
IN UINT32 MediaId,
|
||||
IN EFI_LBA Lba,
|
||||
IN UINTN BufferSize,
|
||||
IN VOID *Buffer
|
||||
);
|
||||
|
||||
/**
|
||||
Flush the Block Device.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
|
||||
@retval EFI_SUCCESS All outstanding data was written to the device
|
||||
@retval EFI_DEVICE_ERROR The device reported an error while writting back the data
|
||||
@retval EFI_NO_MEDIA There is no media in the device.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_BLOCK_FLUSH)(
|
||||
IN PEI_BLOCK_IO_PPI *This
|
||||
);
|
||||
|
||||
/**
|
||||
Block IO read only mode data and updated only via members of BlockIO
|
||||
**/
|
||||
typedef struct {
|
||||
///
|
||||
/// The curent media Id. If the media changes, this value is changed.
|
||||
///
|
||||
UINT32 MediaId;
|
||||
|
||||
///
|
||||
/// TRUE if the media is removable; otherwise, FALSE.
|
||||
///
|
||||
BOOLEAN RemovableMedia;
|
||||
|
||||
///
|
||||
/// TRUE if there is a media currently present in the device;
|
||||
/// othersise, FALSE. THis field shows the media present status
|
||||
/// as of the most recent ReadBlocks() or WriteBlocks() call.
|
||||
///
|
||||
BOOLEAN MediaPresent;
|
||||
|
||||
///
|
||||
/// TRUE if LBA 0 is the first block of a partition; otherwise
|
||||
/// FALSE. For media with only one partition this would be TRUE.
|
||||
///
|
||||
BOOLEAN LogicalPartition;
|
||||
|
||||
///
|
||||
/// TRUE if the media is marked read-only otherwise, FALSE.
|
||||
/// This field shows the read-only status as of the most recent WriteBlocks () call.
|
||||
///
|
||||
BOOLEAN ReadOnly;
|
||||
|
||||
///
|
||||
/// TRUE if the WriteBlock () function caches write data.
|
||||
///
|
||||
BOOLEAN WriteCaching;
|
||||
|
||||
///
|
||||
/// The intrinsic block size of the device. If the media changes, then
|
||||
/// this field is updated.
|
||||
///
|
||||
UINT32 BlockSize;
|
||||
|
||||
///
|
||||
/// Supplies the alignment requirement for any buffer to read or write block(s).
|
||||
///
|
||||
UINT32 IoAlign;
|
||||
|
||||
///
|
||||
/// The last logical block address on the device.
|
||||
/// If the media changes, then this field is updated.
|
||||
///
|
||||
EFI_LBA LastBlock;
|
||||
|
||||
///
|
||||
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
|
||||
/// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to
|
||||
/// a physical block boundary.
|
||||
///
|
||||
EFI_LBA LowestAlignedLba;
|
||||
|
||||
///
|
||||
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
|
||||
/// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks
|
||||
/// per physical block.
|
||||
///
|
||||
UINT32 LogicalBlocksPerPhysicalBlock;
|
||||
|
||||
///
|
||||
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
|
||||
/// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length
|
||||
/// granularity as a number of logical blocks.
|
||||
///
|
||||
UINT32 OptimalTransferLengthGranularity;
|
||||
#ifdef ECP_FLAG
|
||||
} PEI_BLOCK_IO_MEDIA2;
|
||||
#else
|
||||
} PEI_BLOCK_IO_MEDIA;
|
||||
#endif
|
||||
#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000
|
||||
#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001
|
||||
#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x00020031
|
||||
|
||||
///
|
||||
/// Revision defined in EFI1.1.
|
||||
///
|
||||
#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION
|
||||
|
||||
///
|
||||
/// This protocol provides control over block devices.
|
||||
///
|
||||
struct _PEI_BLOCK_IO_PPI {
|
||||
///
|
||||
/// The revision to which the block IO interface adheres. All future
|
||||
/// revisions must be backwards compatible. If a future version is not
|
||||
/// back wards compatible, it is not the same GUID.
|
||||
///
|
||||
UINT64 Revision;
|
||||
///
|
||||
/// Pointer to the EFI_BLOCK_IO_MEDIA data for this device.
|
||||
///
|
||||
PEI_BLOCK_IO_MEDIA *Media;
|
||||
PEI_BLOCK_RESET Reset;
|
||||
PEI_BLOCK_READ ReadBlocks;
|
||||
PEI_BLOCK_WRITE WriteBlocks;
|
||||
PEI_BLOCK_FLUSH FlushBlocks;
|
||||
};
|
||||
|
||||
//extern EFI_GUID gEfiBlockIoProtocolGuid;
|
||||
extern EFI_GUID gPeiBlockIoPpiGuid;
|
||||
#endif
|
||||
@@ -0,0 +1,365 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
Spi.h
|
||||
|
||||
@brief
|
||||
This file defines the EFI SPI PPI which implements the
|
||||
Intel(R) PCH SPI Host Controller Compatibility Interface.
|
||||
|
||||
**/
|
||||
#ifndef _PEI_SDHC_H_
|
||||
#define _PEI_SDHC_H_
|
||||
|
||||
|
||||
|
||||
//
|
||||
#define PEI_SDHC_PPI_GUID \
|
||||
{ \
|
||||
0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \
|
||||
}
|
||||
typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;
|
||||
|
||||
#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01
|
||||
|
||||
typedef enum {
|
||||
ResponseNo = 0,
|
||||
ResponseR1,
|
||||
ResponseR1b,
|
||||
ResponseR2,
|
||||
ResponseR3,
|
||||
ResponseR4,
|
||||
ResponseR5,
|
||||
ResponseR5b,
|
||||
ResponseR6,
|
||||
ResponseR7
|
||||
} RESPONSE_TYPE;
|
||||
|
||||
typedef enum {
|
||||
NoData = 0,
|
||||
InData,
|
||||
OutData
|
||||
} TRANSFER_TYPE;
|
||||
|
||||
typedef enum {
|
||||
Reset_Auto = 0,
|
||||
Reset_DAT,
|
||||
Reset_CMD,
|
||||
Reset_DAT_CMD,
|
||||
Reset_All
|
||||
} RESET_TYPE;
|
||||
|
||||
|
||||
|
||||
typedef enum {
|
||||
SDMA = 0,
|
||||
ADMA2,
|
||||
PIO
|
||||
} DMA_MOD;
|
||||
|
||||
typedef struct {
|
||||
UINT32 HighSpeedSupport: 1; //High speed supported
|
||||
UINT32 V18Support: 1; //1.8V supported
|
||||
UINT32 V30Support: 1; //3.0V supported
|
||||
UINT32 V33Support: 1; //3.3V supported
|
||||
UINT32 Reserved0: 4;
|
||||
UINT32 BusWidth4: 1; // 4 bit width
|
||||
UINT32 BusWidth8: 1; // 8 bit width
|
||||
UINT32 Reserved1: 6;
|
||||
UINT32 SDMASupport: 1;
|
||||
UINT32 ADMA2Support: 1;
|
||||
UINT32 DmaMode: 2;
|
||||
UINT32 Reserved2: 12;
|
||||
UINT32 BoundarySize;
|
||||
}HOST_CAPABILITY;
|
||||
|
||||
|
||||
#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
|
||||
#define PCI_IF_STANDARD_HOST_NO_DMA 0x00
|
||||
#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01
|
||||
|
||||
//
|
||||
//MMIO Registers definition for MMC/SDIO controller
|
||||
//
|
||||
#define MMIO_DMAADR 0x00
|
||||
#define MMIO_BLKSZ 0x04
|
||||
#define MMIO_BLKCNT 0x06
|
||||
#define MMIO_CMDARG 0x08
|
||||
#define MMIO_XFRMODE 0x0C
|
||||
#define MMIO_SDCMD 0x0E
|
||||
#define MMIO_RESP 0x10
|
||||
#define MMIO_BUFDATA 0x20
|
||||
#define MMIO_PSTATE 0x24
|
||||
#define MMIO_HOSTCTL 0x28
|
||||
#define MMIO_PWRCTL 0x29
|
||||
#define MMIO_BLKGAPCTL 0x2A
|
||||
#define MMIO_WAKECTL 0x2B
|
||||
#define MMIO_CLKCTL 0x2C
|
||||
#define MMIO_TOCTL 0x2E
|
||||
#define MMIO_SWRST 0x2F
|
||||
#define MMIO_NINTSTS 0x30
|
||||
#define MMIO_ERINTSTS 0x32
|
||||
#define MMIO_NINTEN 0x34
|
||||
#define MMIO_ERINTEN 0x36
|
||||
#define MMIO_NINTSIGEN 0x38
|
||||
#define MMIO_ERINTSIGEN 0x3A
|
||||
#define MMIO_AC12ERRSTS 0x3C
|
||||
#define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2
|
||||
#define MMIO_CAP 0x40
|
||||
#define MMIO_CAP2 0x44 //hphang <- New in VLV2
|
||||
#define MMIO_MCCAP 0x48
|
||||
#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2
|
||||
#define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2
|
||||
#define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2
|
||||
#define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2
|
||||
#define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2
|
||||
#define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2
|
||||
#define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2
|
||||
#define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2
|
||||
#define MMIO_SLTINTSTS 0xFC
|
||||
#define MMIO_CTRLRVER 0xFE
|
||||
#define MMIO_SRST 0x1FC
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT16 CommandIndex,
|
||||
IN UINT32 Argument,
|
||||
IN TRANSFER_TYPE DataType,
|
||||
IN UINT8 *Buffer, OPTIONAL
|
||||
IN UINT32 BufferSize,
|
||||
IN RESPONSE_TYPE ResponseType,
|
||||
IN UINT32 TimeOut,
|
||||
OUT UINT32 *ResponseData OPTIONAL
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set max clock frequency of the host, the actual frequency
|
||||
may not be the same as MaxFrequency. It depends on
|
||||
the max frequency the host can support, divider, and host
|
||||
speed mode.
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
MaxFrequency - Max frequency in HZ
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 MaxFrequency
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set bus width of the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
BusWidth - Bus width in 1, 4, 8 bits
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 BusWidth
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set Host mode in DDR
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
SetHostDdrMode - True for DDR Mode set, false for normal mode
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 DdrMode
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set voltage which could supported by the host.
|
||||
Support 0(Power off the host), 1.8V, 3.0V, 3.3V
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
Voltage - Units in 0.1 V
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 Voltage
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Reset the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
ResetAll - TRUE to reset all
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN RESET_TYPE ResetType
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Reset the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
Enable - TRUE to enable, FALSE to disable
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN BOOLEAN Enable
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Find whether these is a card inserted into the slot. If so
|
||||
init the host. If not, return EFI_NOT_FOUND.
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_NOT_FOUND
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set the Block length
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
BlockLength - card supportes block length
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (
|
||||
IN PEI_SD_CONTROLLER_PPI *This,
|
||||
IN UINT32 BlockLength
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set the Block length
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
BlockLength - card supportes block length
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
|
||||
typedef EFI_STATUS
|
||||
(EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(
|
||||
IN PEI_SD_CONTROLLER_PPI *This
|
||||
);
|
||||
|
||||
//
|
||||
// Interface structure for the EFI SD Host I/O Protocol
|
||||
//
|
||||
struct _PEI_SD_CONTROLLER_PPI {
|
||||
UINT32 Revision;
|
||||
HOST_CAPABILITY HostCapability;
|
||||
EFI_SD_CONTROLLER_PPI_SEND_COMMAND SendCommand;
|
||||
EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY SetClockFrequency;
|
||||
EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH SetBusWidth;
|
||||
EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE SetHostVoltage;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode;
|
||||
EFI_SD_CONTROLLER_PPI_RESET_SD_HOST ResetSdHost;
|
||||
EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;
|
||||
EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;
|
||||
EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH SetBlockLength;
|
||||
EFI_SD_CONTROLLER_PPI_SETUP_DEVICE SetupDevice;
|
||||
};
|
||||
// Extern the GUID for PPI users.
|
||||
//
|
||||
extern EFI_GUID gPeiSdhcPpiGuid;
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
//
|
||||
//
|
||||
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
SmbusPolicy.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Smbus Policy PPI as defined in EFI 2.0
|
||||
|
||||
--*/
|
||||
#ifndef _PEI_SMBUS_POLICY_PPI_H
|
||||
#define _PEI_SMBUS_POLICY_PPI_H
|
||||
|
||||
#define PEI_SMBUS_POLICY_PPI_GUID \
|
||||
{ \
|
||||
0x63b6e435, 0x32bc, 0x49c6, 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c \
|
||||
}
|
||||
|
||||
typedef struct _PEI_SMBUS_POLICY_PPI PEI_SMBUS_POLICY_PPI;
|
||||
|
||||
typedef struct _PEI_SMBUS_POLICY_PPI {
|
||||
UINTN BaseAddress;
|
||||
UINT32 PciAddress;
|
||||
UINT8 NumRsvdAddress;
|
||||
UINT8 *RsvdAddress;
|
||||
} PEI_SMBUS_POLICY_PPI;
|
||||
|
||||
extern EFI_GUID gPeiSmbusPolicyPpiGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,48 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
Spi.h
|
||||
|
||||
@brief
|
||||
This file defines the EFI SPI PPI which implements the
|
||||
Intel(R) PCH SPI Host Controller Compatibility Interface.
|
||||
|
||||
**/
|
||||
#ifndef _PEI_SPI_H_
|
||||
#define _PEI_SPI_H_
|
||||
|
||||
|
||||
#include <Protocol/Spi.h>
|
||||
|
||||
|
||||
//
|
||||
#define PEI_SPI_PPI_GUID \
|
||||
{ \
|
||||
0xa38c6898, 0x2b5c, 0x4ff6, 0x93, 0x26, 0x2e, 0x63, 0x21, 0x2e, 0x56, 0xc2 \
|
||||
}
|
||||
// Extern the GUID for PPI users.
|
||||
//
|
||||
extern EFI_GUID gPeiSpiPpiGuid;
|
||||
|
||||
///
|
||||
/// Reuse the EFI_SPI_PROTOCOL definitions
|
||||
/// This is possible becaues the PPI implementation does not rely on a PeiService pointer,
|
||||
/// as it uses EDKII Glue Lib to do IO accesses
|
||||
///
|
||||
typedef EFI_SPI_PROTOCOL PEI_SPI_PPI;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,129 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
ActiveBios.h
|
||||
|
||||
@brief
|
||||
This protocol is used to report and control what BIOS is mapped to the
|
||||
BIOS address space anchored at 4GB boundary.
|
||||
|
||||
This protocol is EFI compatible.
|
||||
|
||||
E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped
|
||||
to PCI, SPI, or FWH.
|
||||
|
||||
**/
|
||||
#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_
|
||||
#define _EFI_ACTIVE_BIOS_PROTOCOL_H_
|
||||
|
||||
|
||||
|
||||
|
||||
//
|
||||
#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xebbe2d1b, 0x1647, 0x4bda, 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a \
|
||||
}
|
||||
extern EFI_GUID gEfiActiveBiosProtocolGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL;
|
||||
|
||||
///
|
||||
/// Protocol definitions
|
||||
///
|
||||
typedef enum {
|
||||
ActiveBiosStateSpi,
|
||||
ActiveBiosStatePci, /// Obsolete since VLV
|
||||
ActiveBiosStateLpc,
|
||||
ActiveBiosStateMax
|
||||
} EFI_ACTIVE_BIOS_STATE;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) (
|
||||
IN EFI_ACTIVE_BIOS_PROTOCOL * This,
|
||||
IN EFI_ACTIVE_BIOS_STATE DesiredState,
|
||||
IN UINTN Key
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
Change the current active BIOS settings to the requested state.
|
||||
The caller is responsible for requesting a supported state from
|
||||
the EFI_ACTIVE_BIOS_STATE selections.
|
||||
This will fail if someone has locked the interface and the correct key is
|
||||
not provided.
|
||||
|
||||
@param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.
|
||||
@param[in] DesiredState The requested state to configure the system for.
|
||||
@param[in] Key If the interface is locked, Key must be the Key
|
||||
returned from the LockState function call.
|
||||
|
||||
@retval EFI_SUCCESS The function completed successfully
|
||||
@retval EFI_ACCESS_DENIED The interface is currently locked.
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) (
|
||||
IN EFI_ACTIVE_BIOS_PROTOCOL * This,
|
||||
IN BOOLEAN Lock,
|
||||
IN OUT UINTN *Key
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
@brief
|
||||
Lock the current active BIOS state from further changes. This allows a
|
||||
caller to implement a critical section. This is optionally supported
|
||||
functionality. Size conscious implementations may choose to require
|
||||
callers cooperate without support from this protocol.
|
||||
|
||||
@param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.
|
||||
@param[in] Lock TRUE to lock the current state, FALSE to unlock.
|
||||
@param[in] Key If Lock is TRUE, then a key will be returned. If
|
||||
Lock is FALSE, the key returned from the prior call
|
||||
to lock the protocol must be provided to unlock the
|
||||
protocol. The value of Key is undefined except that
|
||||
it cannot be 0.
|
||||
|
||||
@retval EFI_SUCCESS Command succeed.
|
||||
@exception EFI_UNSUPPORTED The function is not supported.
|
||||
@retval EFI_ACCESS_DENIED The interface is currently locked.
|
||||
@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
|
||||
|
||||
**/
|
||||
|
||||
///
|
||||
/// Protocol definition
|
||||
///
|
||||
/// Note that some functions are optional. This means that they may be NULL.
|
||||
/// Caller is required to verify that an optional function is defined by checking
|
||||
/// that the value is not NULL.
|
||||
///
|
||||
struct _EFI_ACTIVE_BIOS_PROTOCOL {
|
||||
EFI_ACTIVE_BIOS_STATE State;
|
||||
EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE SetState;
|
||||
EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE LockState;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,131 @@
|
||||
/**
|
||||
This protocol is used to report and control what BIOS is mapped to the
|
||||
BIOS address space anchored at 4GB boundary.
|
||||
|
||||
This protocol is EFI compatible.
|
||||
|
||||
E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped
|
||||
to PCI, SPI, or FWH.
|
||||
|
||||
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
**/
|
||||
|
||||
|
||||
#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_
|
||||
#define _EFI_ACTIVE_BIOS_PROTOCOL_H_
|
||||
|
||||
//
|
||||
// Define the protocol GUID
|
||||
//
|
||||
#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \
|
||||
{ 0xebbe2d1b, 0x1647, 0x4bda, {0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a} }
|
||||
|
||||
typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL;
|
||||
|
||||
//
|
||||
// Protocol definitions
|
||||
//
|
||||
typedef enum {
|
||||
ActiveBiosStateSpi,
|
||||
ActiveBiosStatePci,
|
||||
ActiveBiosStateLpc,
|
||||
ActiveBiosStateMax
|
||||
} EFI_ACTIVE_BIOS_STATE;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) (
|
||||
IN EFI_ACTIVE_BIOS_PROTOCOL *This,
|
||||
IN EFI_ACTIVE_BIOS_STATE DesiredState,
|
||||
IN UINTN Key
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Change the current active BIOS settings to the requested state.
|
||||
The caller is responsible for requesting a supported state from
|
||||
the EFI_ACTIVE_BIOS_STATE selections.
|
||||
|
||||
This will fail if someone has locked the interface and the correct key is
|
||||
not provided.
|
||||
|
||||
Arguments:
|
||||
|
||||
This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.
|
||||
DesiredState The requested state to configure the system for.
|
||||
Key If the interface is locked, Key must be the Key
|
||||
returned from the LockState function call.
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_SUCCESS Command succeed.
|
||||
EFI_ACCESS_DENIED The interface is currently locked.
|
||||
EFI_DEVICE_ERROR Device error, command aborts abnormally.
|
||||
|
||||
--*/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) (
|
||||
IN EFI_ACTIVE_BIOS_PROTOCOL *This,
|
||||
IN BOOLEAN Lock,
|
||||
IN OUT UINTN *Key
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Lock the current active BIOS state from further changes. This allows a
|
||||
caller to implement a critical section. This is optionally supported
|
||||
functionality. Size conscious implementations may choose to require
|
||||
callers cooperate without support from this protocol.
|
||||
|
||||
Arguments:
|
||||
|
||||
This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.
|
||||
Lock TRUE to lock the current state, FALSE to unlock.
|
||||
Key If Lock is TRUE, then a key will be returned. If
|
||||
Lock is FALSE, the key returned from the prior call
|
||||
to lock the protocol must be provided to unlock the
|
||||
protocol. The value of Key is undefined except that it
|
||||
will never be 0.
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_SUCCESS Command succeed.
|
||||
EFI_UNSUPPORTED The function is not supported.
|
||||
EFI_ACCESS_DENIED The interface is currently locked.
|
||||
EFI_DEVICE_ERROR Device error, command aborts abnormally.
|
||||
|
||||
--*/
|
||||
|
||||
//
|
||||
// Protocol definition
|
||||
//
|
||||
// Note that some functions are optional. This means that they may be NULL.
|
||||
// Caller is required to verify that an optional function is defined by checking
|
||||
// that the value is not NULL.
|
||||
//
|
||||
struct _EFI_ACTIVE_BIOS_PROTOCOL {
|
||||
EFI_ACTIVE_BIOS_STATE State;
|
||||
EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE SetState;
|
||||
EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE LockState;
|
||||
};
|
||||
|
||||
//
|
||||
// Extern the GUID for protocol users.
|
||||
//
|
||||
extern EFI_GUID gEfiActiveBiosProtocolGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,57 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
DxePchPolicyUpdateProtocol.h
|
||||
|
||||
Abstract:
|
||||
|
||||
PCH policy update protocol. This protocol is consumed by the PchDxePolicyInit driver
|
||||
|
||||
--*/
|
||||
#ifndef _DXE_PCH_POLICY_UPDATE_PROTOCOL_H_
|
||||
#define _DXE_PCH_POLICY_UPDATE_PROTOCOL_H_
|
||||
|
||||
#include "PchRegs.h"
|
||||
|
||||
|
||||
#ifdef ECP_FLAG
|
||||
#define DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x1a819e49, 0xd8ee, 0x48cb, 0x9a, 0x9c, 0xa, 0xa0, 0xd2, 0x81, 0xa, 0x38 \
|
||||
}
|
||||
#else
|
||||
#define DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x1a819e49, 0xd8ee, 0x48cb, \
|
||||
{ \
|
||||
0x9a, 0x9c, 0xa, 0xa0, 0xd2, 0x81, 0xa, 0x38 \
|
||||
} \
|
||||
}
|
||||
#endif
|
||||
|
||||
extern EFI_GUID gDxePchPolicyUpdateProtocolGuid;
|
||||
#define DXE_PCH_POLICY_UPDATE_PROTOCOL_REVISION_1 1
|
||||
|
||||
//
|
||||
// ------------ General PCH policy Update protocol definition ------------
|
||||
//
|
||||
struct _DXE_PCH_POLICY_UPDATE_PROTOCOL {
|
||||
UINT8 Revision;
|
||||
};
|
||||
|
||||
typedef struct _DXE_PCH_POLICY_UPDATE_PROTOCOL DXE_PCH_POLICY_UPDATE_PROTOCOL;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,48 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
/*++
|
||||
Module Name:
|
||||
|
||||
EmmcCardInfoProtocol.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition for EFI_EMMC_CARD_INFO_PROTOCOL
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
#ifndef _EMMC_CARD_INFO_H_
|
||||
#define _EMMC_CARD_INFO_H_
|
||||
|
||||
#define EFI_EMMC_CARD_INFO_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd } \
|
||||
}
|
||||
|
||||
typedef struct _EFI_EMMC_CARD_INFO_PROTOCOL EFI_EMMC_CARD_INFO_PROTOCOL;
|
||||
|
||||
|
||||
//
|
||||
// EMMC Card info Structures
|
||||
//
|
||||
struct _EFI_EMMC_CARD_INFO_PROTOCOL {
|
||||
CARD_DATA *CardData;
|
||||
};
|
||||
|
||||
extern EFI_GUID gEfiEmmcCardInfoProtocolGuid;
|
||||
#endif
|
||||
@@ -0,0 +1,167 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
Gpio.h
|
||||
|
||||
Abstract:
|
||||
|
||||
EFI 2.0 PEIM to provide platform specific information to other
|
||||
modules and to do some platform specific initialization.
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _PEI_GPIO_H
|
||||
#define _PEI_GPIO_H
|
||||
|
||||
//#include "Efi.h"
|
||||
//#include "EfiCommonLib.h"
|
||||
//#include "Pei.h"
|
||||
//#include "Numbers.h"
|
||||
|
||||
////
|
||||
//// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)
|
||||
////
|
||||
//// Field Descriptions:
|
||||
//// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode.
|
||||
//// I/O: Defines whether GPIOs are inputs (I) or outputs (O).
|
||||
//// (Note: Only meaningful for pins used as GPIOs.)
|
||||
//// LVL: This field gives you the initial value for "output" GPIO's.
|
||||
//// (Note: The output level is dependent upon whether the pin is inverted.)
|
||||
//// INV: Defines whether Input GPIOs activation level is inverted.
|
||||
//// (Note: Only affects the level sent to the GPE logic and does not
|
||||
//// affect the level read through the GPIO registers.)
|
||||
////
|
||||
//// Notes:
|
||||
//// 1. BoardID is GPIO [8:38:34]
|
||||
////
|
||||
////Signal UsedAs USE I/O LVL INV
|
||||
////--------------------------------------------------------------------------
|
||||
////GPIO0 Nonfunction G O H -
|
||||
////GPIO1 SMC_RUNTIME_SCI# G I - I
|
||||
////PIRQE#/GPIO2 Nonfunction G O H -
|
||||
////PIRQF#/GPIO3 Nonfunction G O H -
|
||||
////PIRQG#/GPIO4 Nonfunction G O H -
|
||||
////PIRQH#/GPIO5 Nonfunction G O H -
|
||||
////GPIO6 unused G O L -
|
||||
////GPIO7 unused G O L -
|
||||
////GPIO8 BOARD ID2 G I - -
|
||||
////GPIO9 unused G O L -
|
||||
////GPIO10 SMC_EXTSMI# G I - I
|
||||
////GPIO11 Nonfunction G O H -
|
||||
////GPIO12 unused G O L -
|
||||
////GPIO13 SMC_WAKE_SCI# G I - I
|
||||
////GPIO14 unused G O L -
|
||||
////GPIO15 unused G O L -
|
||||
////GPIO16 PM_DPRSLPVR N - - -
|
||||
////GNT5#/GPIO17 GNT5# N - - -
|
||||
////STPPCI#/GPIO18 PM_STPPCI# N - - -
|
||||
////STPCPU#/GPIO20 PM_STPCPU# N - - -
|
||||
////GPIO22 CRT_RefClk G I - -
|
||||
////GPIO23 unused G O L -
|
||||
////GPIO24 unused G O L -
|
||||
////GPIO25 DMI strap G O L -
|
||||
////GPIO26 unused G O L -
|
||||
////GPIO27 unused G O L -
|
||||
////GPIO28 RF_KILL# G O H -
|
||||
////OC5#/GPIO29 OC N - - -
|
||||
////OC6#/GPIO30 OC N - - -
|
||||
////OC7#/GPIO31 OC N - - -
|
||||
////CLKRUN#/GPIO32 PM_CLKRUN# N - - -
|
||||
////GPIO33 NC G O L -
|
||||
////GPIO34 BOARD ID0 G I - -
|
||||
////GPIO36 unused G O L -
|
||||
////GPIO38 BOARD ID1 G I - -
|
||||
////GPIO39 unused G O L -
|
||||
////GPIO48 unused G O L -
|
||||
////CPUPWRGD/GPIO49 H_PWRGD N - - -
|
||||
//
|
||||
//#define GPIO_USE_SEL_VAL 0x1FC0FFFF //GPIO1, 10, 13 is EC signal
|
||||
//#define GPIO_USE_SEL2_VAL 0x000100D6
|
||||
//#define GPIO_IO_SEL_VAL 0x00402502
|
||||
//#define GPIO_IO_SEL2_VAL 0x00000044
|
||||
//#define GPIO_LVL_VAL 0x1800083D
|
||||
//#define GPIO_LVL2_VAL 0x00000000
|
||||
//#define GPIO_INV_VAL 0x00002402
|
||||
//#define GPIO_BLNK_VAL 0x00000000
|
||||
//#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))
|
||||
|
||||
//
|
||||
// GPIO Register Settings for CedarRock and CedarFalls platforms
|
||||
//
|
||||
// GPIO Register Settings for NB10_CRB
|
||||
//---------------------------------------------------------------------------------
|
||||
//Signal Used As USE I/O LVL
|
||||
//---------------------------------------------------------------------------------
|
||||
//
|
||||
// GPIO0 FP_AUDIO_DETECT G I
|
||||
// GPIO1 SMC_RUNTIME_SCI# G I
|
||||
// GPIO2 INT_PIRQE_N N I
|
||||
// GPIO3 INT_PIRQF_N N I
|
||||
// GPIO4 INT_PIRQG_N N I
|
||||
// GPIO5 INT_PIRQH_N N I
|
||||
// GPIO6
|
||||
// GPIO7
|
||||
// GPIO8
|
||||
// GPIO9 LPC_SIO_PME G I
|
||||
// GPIO10 SMC_EXTSMI_N G I
|
||||
// GPIO11 SMBALERT- pullup N
|
||||
// GPIO12 ICH_GP12 G I
|
||||
// GPIO13 SMC_WAKE_SCI_N G I
|
||||
// GPIO14 LCD_PID0 G O H
|
||||
// GPIO15 CONFIG_MODE_N G I
|
||||
// GPIO16 PM_DPRSLPVR N
|
||||
// GPIO17 SPI_SELECT_STRAP1
|
||||
// /L_BKLTSEL0_N G I
|
||||
// GPIO18 PM_STPPCI_N N
|
||||
// GPIO19
|
||||
// GPIO20 PM_STPCPU_N N
|
||||
// GPIO21
|
||||
// GPIO22 REQ4B G I
|
||||
// GPIO23 L_DRQ1_N N
|
||||
// GPIO24 CRB_SV_DET_N G O H
|
||||
// GPIO25 DMI strap
|
||||
// / L_BKLTSEL1_N G O H
|
||||
// GPIO26 LCD_PID1 G O H
|
||||
// GPIO27 TPEV_DDR3L_DETECT G O H
|
||||
// GPIO28 RF_KILL G O H:enable
|
||||
// GPIO29 OC N
|
||||
// GPIO30 OC N
|
||||
// GPIO31 OC N
|
||||
// GPIO32 PM_CLKRUN_N Native
|
||||
// GPIO33 MFG_MODE_N G I
|
||||
// GPIO34 BOARD ID0 G I
|
||||
// GPIO35
|
||||
// GPIO36 SV_SET_UP G O H
|
||||
// GPIO37
|
||||
// GPIO38 BOARD ID1 G I
|
||||
// GPIO39 BOARD ID2 G I
|
||||
// GPIO48 FLASH_SEL0 N
|
||||
// GPIO49 H_PWRGD N
|
||||
|
||||
#define ICH_GPI_ROUTE_SMI(Gpio) ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))
|
||||
#define ICH_GPI_ROUTE_SCI(Gpio) ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))
|
||||
|
||||
#define GPIO_USE_SEL_VAL 0X1F42F7C3
|
||||
#define GPIO_USE_SEL2_VAL 0X000000D6
|
||||
#define GPIO_IO_SEL_VAL 0X1042B73F
|
||||
#define GPIO_IO_SEL2_VAL 0X000100C6
|
||||
#define GPIO_LVL_VAL 0X1F15F601
|
||||
#define GPIO_LVL2_VAL 0X000200D7
|
||||
#define GPIO_INV_VAL 0x00002602
|
||||
#define GPIO_BLNK_VAL 0x00040000
|
||||
#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,300 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
HwWatchdogTimer.h
|
||||
|
||||
Abstract:
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__
|
||||
#define __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__
|
||||
|
||||
#define EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_GUID \
|
||||
{ 0xd5b06d16, 0x2ea1, 0x4def, 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 }
|
||||
|
||||
#define EFI_WATCHDOG_TIMER_NOT_SUPPORTED_PROTOCOL_GUID \
|
||||
{ 0xe9e156ac, 0x3203, 0x4572, 0xac, 0xdf, 0x84, 0x4f, 0xdc, 0xdb, 0x6, 0xbf }
|
||||
|
||||
|
||||
#include <Guid/HwWatchdogTimerHob.h>
|
||||
|
||||
//
|
||||
// General Purpose Constants
|
||||
//
|
||||
#define ICH_INSTAFLUSH_GPIO BIT16 // BIT 16 in GPIO Level 2 is GPIO 48.
|
||||
#define B_INSTAFLUSH BIT4
|
||||
//
|
||||
// Other Watchdog timer values
|
||||
//
|
||||
#define WDT_COUNTDOWN_VALUE 0x14
|
||||
#define BDS_WDT_COUNTDOWN_VALUE 0x35
|
||||
|
||||
|
||||
//
|
||||
// Prototypes for the Watchdog Timer Driver Protocol
|
||||
//
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_WATCHDOG_START_TIMER) (
|
||||
VOID
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service begins the Watchdog Timer countdown. If the countdown completes prior to
|
||||
Stop Timer or Restart Timer the system will reset.
|
||||
|
||||
Arguments:
|
||||
None
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_WATCHDOG_RESET_TIMER) (
|
||||
VOID
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service resets the Watchdog Timer countdown and should only be called after the
|
||||
Start Timer function.
|
||||
|
||||
Arguments:
|
||||
None
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_WATCHDOG_RESTART_TIMER) (
|
||||
VOID
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service restarts the Watchdog Timer countdown and should only be called after the
|
||||
Start Timer function.
|
||||
|
||||
Arguments:
|
||||
None
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_WATCHDOG_STOP_TIMER) (
|
||||
VOID
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service disables the Watchdog Timer countdown.
|
||||
|
||||
Arguments:
|
||||
None
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_WATCHDOG_CHECK_TIMEOUT) (
|
||||
OUT HW_WATCHDOG_TIMEOUT *WatchdogTimeout
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service disables the Watchdog Timer countdown.
|
||||
|
||||
Arguments:
|
||||
None
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_WATCHDOG_FORCE_REBOOT) (
|
||||
IN BOOLEAN ForceTimeout,
|
||||
IN UINT8 ResetType
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service forces a reboot of the system due to a reset of the POWERGOOD_PS,
|
||||
POWERGOOD_CLK, and the BSEL Override
|
||||
|
||||
Arguments:
|
||||
None
|
||||
|
||||
Returns:
|
||||
This function should not return!
|
||||
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did not occur
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_WATCHDOG_KNOWN_RESET) (
|
||||
IN BOOLEAN AllowReset
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service notifies the Watchdog Timer of the fact that a known reset is occuring.
|
||||
|
||||
Arguments:
|
||||
AllowReset - TRUE if a Reset is currently expected
|
||||
FALSE if a Reset is not currently expected
|
||||
|
||||
Returns:
|
||||
This function should not return!
|
||||
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did not occur
|
||||
|
||||
--*/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_GET_TIMER_COUNT_DOWN_PERIOD)(
|
||||
OUT UINT32 *CountdownValue
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service reads the current Watchdog Timer countdown reload value.
|
||||
|
||||
Arguments:
|
||||
CountdownValue - pointer to UINT32 to return the value of the reload register.
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SET_TIMER_COUNT_DOWN_PERIOD)(
|
||||
OUT UINT32 CountdownValue
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service reads the current Watchdog Timer countdown reload value.
|
||||
|
||||
Arguments:
|
||||
CountdownValue - Value to set the reload register.
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PEI_WATCHDOG_CLEAR_TIMER_STATE) (
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service clears the state that indicates the Watchdog Timer fired.
|
||||
|
||||
Arguments:
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_STALL_WATCHDOG_COUNTDOWN) (
|
||||
IN BOOLEAN Stall
|
||||
);
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
This service disables the Watchdog Timer countdown. It also closes the recurring restart event
|
||||
if the event exists.
|
||||
|
||||
Arguments:
|
||||
Stall - TRUE = Stop the timer countdown
|
||||
FALSE = Start the timer countdown
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS - Operation completed successfully
|
||||
EFI_DEVICE_ERROR - The command was unsuccessful
|
||||
|
||||
--*/
|
||||
|
||||
typedef struct _EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL {
|
||||
EFI_WATCHDOG_START_TIMER StartWatchdogTimer;
|
||||
PEI_WATCHDOG_RESET_TIMER ResetWatchdogTimeout;
|
||||
EFI_WATCHDOG_RESTART_TIMER RestartWatchdogTimer;
|
||||
EFI_WATCHDOG_STOP_TIMER StopWatchdogTimer;
|
||||
EFI_WATCHDOG_CHECK_TIMEOUT CheckWatchdogTimeout;
|
||||
EFI_WATCHDOG_FORCE_REBOOT ForceReboot;
|
||||
EFI_WATCHDOG_KNOWN_RESET AllowKnownReset;
|
||||
EFI_GET_TIMER_COUNT_DOWN_PERIOD GetCountdownPeriod;
|
||||
EFI_SET_TIMER_COUNT_DOWN_PERIOD SetCountdownPeriod;
|
||||
PEI_WATCHDOG_CLEAR_TIMER_STATE ClearTimerState;
|
||||
EFI_STALL_WATCHDOG_COUNTDOWN StallWatchdogCountdown;
|
||||
} EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL;
|
||||
|
||||
extern EFI_GUID gEfiWatchdogTimerDriverProtocolGuid;
|
||||
extern EFI_GUID gEfiWatchdogTimerNotSupportedProtocolGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,170 @@
|
||||
/** @file
|
||||
I2C bus interface
|
||||
|
||||
This layer provides I/O access to an I2C device.
|
||||
|
||||
Copyright (c) 2012, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __I2C_BUS_H__
|
||||
#define __I2C_BUS_H__
|
||||
|
||||
#include <Protocol/I2cHostMcg.h>
|
||||
|
||||
///
|
||||
/// I2C bus protocol
|
||||
///
|
||||
typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL;
|
||||
|
||||
|
||||
/**
|
||||
Perform an I2C operation on the device
|
||||
|
||||
This routine must be called at or below TPL_NOTIFY. For synchronous
|
||||
requests this routine must be called at or below TPL_CALLBACK.
|
||||
|
||||
N.B. The typical consumers of this API are the third party I2C
|
||||
drivers. Extreme care must be taken by other consumers of this
|
||||
API to prevent confusing the third party I2C drivers due to a
|
||||
state change at the I2C device which the third party I2C drivers
|
||||
did not initiate. I2C platform drivers may use this API within
|
||||
these guidelines.
|
||||
|
||||
This routine queues an operation to the I2C controller for execution
|
||||
on the I2C bus.
|
||||
|
||||
As an upper layer driver writer, the following need to be provided
|
||||
to the platform vendor:
|
||||
|
||||
1. ACPI CID value or string - this is used to connect the upper layer
|
||||
driver to the device.
|
||||
2. Slave address array guidance when the I2C device uses more than one
|
||||
slave address. This is used to access the blocks of hardware within
|
||||
the I2C device.
|
||||
|
||||
@param[in] This Address of an EFI_I2C_BUS_PROTOCOL
|
||||
structure
|
||||
@param[in] SlaveAddressIndex Index into an array of slave addresses for
|
||||
the I2C device. The values in the array are
|
||||
specified by the board designer, with the
|
||||
I2C device driver writer providing the slave
|
||||
address order.
|
||||
|
||||
For devices that have a single slave address,
|
||||
this value must be zero. If the I2C device
|
||||
uses more than one slave address then the third
|
||||
party (upper level) I2C driver writer needs to
|
||||
specify the order of entries in the slave address
|
||||
array.
|
||||
|
||||
\ref ThirdPartyI2cDrivers "Third Party I2C Drivers"
|
||||
section in I2cMaster.h.
|
||||
@param[in] Event Event to set for asynchronous operations,
|
||||
NULL for synchronous operations
|
||||
@param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
|
||||
structure describing the I2C operation
|
||||
@param[out] I2cStatus Optional buffer to receive the I2C operation
|
||||
completion status
|
||||
|
||||
@retval EFI_SUCCESS The operation completed successfully.
|
||||
@retval EFI_ABORTED The request did not complete because the driver
|
||||
was shutdown.
|
||||
@retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value
|
||||
@retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.
|
||||
@retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.
|
||||
This could indicate the slave device is not present.
|
||||
@retval EFI_INVALID_PARAMETER RequestPacket is NULL
|
||||
@retval EFI_INVALID_PARAMETER TPL is too high
|
||||
@retval EFI_NO_RESPONSE The I2C device is not responding to the
|
||||
slave address. EFI_DEVICE_ERROR may also be
|
||||
returned if the controller can not distinguish
|
||||
when the NACK occurred.
|
||||
@retval EFI_NOT_FOUND I2C slave address exceeds maximum address
|
||||
@retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
|
||||
the event and then read status pointed to by
|
||||
the request packet.
|
||||
@retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
|
||||
@retval EFI_TIMEOUT The transaction did not complete within an internally
|
||||
specified timeout period.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_I2C_BUS_START_REQUEST) (
|
||||
IN CONST EFI_I2C_BUS_PROTOCOL *This,
|
||||
IN UINTN SlaveAddressIndex,
|
||||
IN EFI_EVENT Event OPTIONAL,
|
||||
IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,
|
||||
OUT EFI_STATUS *I2cStatus OPTIONAL
|
||||
);
|
||||
|
||||
///
|
||||
/// The I2C bus protocol enables access to a specific device on the I2C bus.
|
||||
///
|
||||
/// Each I2C device is described as an ACPI node (HID, UID and CID) within the
|
||||
/// platform layer. The I2C bus protocol enumerates the I2C devices in the
|
||||
/// platform and creates a unique handle and device path for each I2C device.
|
||||
///
|
||||
/// I2C slave addressing is abstracted to validate addresses and limit operation
|
||||
/// to the specified I2C device. The third party providing the I2C device support
|
||||
/// provides an ordered list of slave addresses for the I2C device to the team
|
||||
/// building the platform layer. The platform team must preserve the order of the
|
||||
/// supplied list. SlaveAddressCount is the number of entries in this list or
|
||||
/// array within the platform layer. The third party device support references
|
||||
/// a slave address using an index into the list or array in the range of zero
|
||||
/// to SlaveAddressCount - 1.
|
||||
///
|
||||
struct _EFI_I2C_BUS_PROTOCOL {
|
||||
///
|
||||
/// Start an I2C operation on the bus
|
||||
///
|
||||
EFI_I2C_BUS_START_REQUEST StartRequest;
|
||||
|
||||
///
|
||||
/// The maximum number of slave addresses for the I2C device. The caller may
|
||||
/// validate this value as a check on the platform layer's configuration. Slave
|
||||
/// address selection uses an index value in the range of zero to SlaveAddressCount - 1.
|
||||
///
|
||||
UINTN SlaveAddressCount;
|
||||
|
||||
///
|
||||
/// Hardware revision - Matches the ACPI _HRV value
|
||||
///
|
||||
/// The HardwareRevision value allows a single driver to support multiple hardware
|
||||
/// revisions and implement the necessary workarounds for limitations within the
|
||||
/// hardware.
|
||||
///
|
||||
UINT32 HardwareRevision;
|
||||
|
||||
///
|
||||
/// The maximum number of bytes the I2C host controller
|
||||
/// is able to receive from the I2C bus.
|
||||
///
|
||||
UINT32 MaximumReceiveBytes;
|
||||
|
||||
///
|
||||
/// The maximum number of bytes the I2C host controller
|
||||
/// is able to send on the I2C bus.
|
||||
///
|
||||
UINT32 MaximumTransmitBytes;
|
||||
|
||||
///
|
||||
/// The maximum number of bytes in the I2C bus transaction.
|
||||
///
|
||||
UINT32 MaximumTotalBytes;
|
||||
};
|
||||
|
||||
///
|
||||
/// GUID for the I2C bus protocol
|
||||
///
|
||||
extern EFI_GUID gEfiI2cBusProtocolGuid;
|
||||
|
||||
#endif // __I2C_BUS_H__
|
||||
@@ -0,0 +1,90 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
PchExtendedReset.h
|
||||
|
||||
Abstract:
|
||||
|
||||
PCH Extended Reset Protocol
|
||||
|
||||
--*/
|
||||
#ifndef _EFI_PCH_EXTENDED_RESET_H_
|
||||
#define _EFI_PCH_EXTENDED_RESET_H_
|
||||
|
||||
|
||||
|
||||
//
|
||||
#define EFI_PCH_EXTENDED_RESET_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xf0bbfca0, 0x684e, 0x48b3, 0xba, 0xe2, 0x6c, 0x84, 0xb8, 0x9e, 0x53, 0x39 \
|
||||
}
|
||||
extern EFI_GUID gEfiPchExtendedResetProtocolGuid;
|
||||
|
||||
//
|
||||
// Forward reference for ANSI C compatibility
|
||||
//
|
||||
typedef struct _EFI_PCH_EXTENDED_RESET_PROTOCOL EFI_PCH_EXTENDED_RESET_PROTOCOL;
|
||||
|
||||
//
|
||||
// Related Definitions
|
||||
//
|
||||
//
|
||||
// PCH Extended Reset Types
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 PowerCycle : 1; // 0: Disabled*; 1: Enabled
|
||||
UINT8 GlobalReset : 1; // 0: Disabled*; 1: Enabled
|
||||
UINT8 SusPwrDnAck : 1; // 0: Do Nothing;
|
||||
// 1: GPIO[30](SUS_PWR_DN_ACK) level is set low prior to Global Reset(for systems with an embedded controller)
|
||||
UINT8 RsvdBits : 5; // Reserved fields for future expansion w/o protocol change
|
||||
} PCH_EXTENDED_RESET_TYPES;
|
||||
|
||||
//
|
||||
// Member functions
|
||||
//
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_PCH_EXTENDED_RESET) (
|
||||
IN EFI_PCH_EXTENDED_RESET_PROTOCOL * This,
|
||||
IN PCH_EXTENDED_RESET_TYPES PchExtendedResetTypes
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Execute Pch Extended Reset from the host controller.
|
||||
|
||||
Arguments:
|
||||
|
||||
This - Pointer to the EFI_PCH_EXTENDED_RESET_PROTOCOL instance.
|
||||
PchExtendedResetTypes - Pch Extended Reset Types which includes PowerCycle, Globalreset.
|
||||
|
||||
Returns:
|
||||
|
||||
Does not return if the reset takes place.
|
||||
EFI_INVALID_PARAMETER - If ResetType is invalid.
|
||||
|
||||
--*/
|
||||
|
||||
//
|
||||
// Interface structure for the Pch Extended Reset Protocol
|
||||
//
|
||||
struct _EFI_PCH_EXTENDED_RESET_PROTOCOL {
|
||||
EFI_PCH_EXTENDED_RESET Reset;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,66 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchInfo.h
|
||||
|
||||
@brief
|
||||
This file defines the PCH Info Protocol.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_INFO_H_
|
||||
#define _PCH_INFO_H_
|
||||
|
||||
|
||||
#define EFI_PCH_INFO_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xd31f0400, 0x7d16, 0x4316, 0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b \
|
||||
}
|
||||
extern EFI_GUID gEfiPchInfoProtocolGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _EFI_PCH_INFO_PROTOCOL EFI_PCH_INFO_PROTOCOL;
|
||||
|
||||
///
|
||||
/// Protocol revision number
|
||||
/// Any backwards compatible changes to this protocol will result in an update in the revision number
|
||||
/// Major changes will require publication of a new protocol
|
||||
///
|
||||
/// Revision 1: Original version
|
||||
///
|
||||
#define PCH_INFO_PROTOCOL_REVISION_1 1
|
||||
#define PCH_INFO_PROTOCOL_REVISION_2 2
|
||||
|
||||
///
|
||||
/// RCVersion[7:0] is the release number.
|
||||
/// For example:
|
||||
/// VlvFramework 0.6.0-01 should be 00 06 00 01 (0x00060001)
|
||||
/// VlvFramework 0.6.2 should be 00 06 02 00 (0x00060200)
|
||||
///
|
||||
#define PCH_RC_VERSION 0x01000000
|
||||
|
||||
///
|
||||
/// Protocol definition
|
||||
///
|
||||
struct _EFI_PCH_INFO_PROTOCOL {
|
||||
UINT8 Revision;
|
||||
UINT8 BusNumber;
|
||||
UINT32 RCVersion;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,556 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchPlatformPolicy.h
|
||||
|
||||
@brief
|
||||
PCH policy protocol produced by a platform driver specifying various
|
||||
expected PCH settings. This protocol is consumed by the PCH drivers.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_PLATFORM_POLICY_H_
|
||||
#define _PCH_PLATFORM_POLICY_H_
|
||||
|
||||
|
||||
//
|
||||
#include "PchRegs.h"
|
||||
#ifndef ECP_FLAG
|
||||
#include "Uefi.h"
|
||||
#endif
|
||||
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x4b0165a9, 0x61d6, 0x4e23, 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 \
|
||||
}
|
||||
extern EFI_GUID gDxePchPlatformPolicyProtocolGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL DXE_PCH_PLATFORM_POLICY_PROTOCOL;
|
||||
|
||||
///
|
||||
/// Protocol revision number
|
||||
/// Any backwards compatible changes to this protocol will result in an update in the revision number
|
||||
/// Major changes will require publication of a new protocol
|
||||
///
|
||||
/// Revision 1: Original version
|
||||
///
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_8 8
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_9 9
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_10 10
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_11 11
|
||||
#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12 12
|
||||
|
||||
///
|
||||
/// Generic definitions for device enabling/disabling used by PCH code.
|
||||
///
|
||||
#define PCH_DEVICE_ENABLE 1
|
||||
#define PCH_DEVICE_DISABLE 0
|
||||
|
||||
///
|
||||
/// ---------------------------- Device Enabling ------------------------------
|
||||
///
|
||||
/// PCH Device enablings
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Lan : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 Azalia : 2; /// 0: Disable; 1: Enable; 2: Auto
|
||||
UINT8 Sata : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 Smbus : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 LpeEnabled : 2; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
|
||||
UINT8 Reserved[1]; /// Reserved fields for future expansion w/o protocol change
|
||||
} PCH_DEVICE_ENABLING;
|
||||
|
||||
///
|
||||
/// ---------------------------- USB Config -----------------------------
|
||||
///
|
||||
///
|
||||
/// Overcurrent pins
|
||||
///
|
||||
typedef enum {
|
||||
PchUsbOverCurrentPin0 = 0,
|
||||
PchUsbOverCurrentPin1,
|
||||
PchUsbOverCurrentPin2,
|
||||
PchUsbOverCurrentPin3,
|
||||
PchUsbOverCurrentPin4,
|
||||
PchUsbOverCurrentPin5,
|
||||
PchUsbOverCurrentPin6,
|
||||
PchUsbOverCurrentPin7,
|
||||
PchUsbOverCurrentPinSkip,
|
||||
PchUsbOverCurrentPinMax
|
||||
} PCH_USB_OVERCURRENT_PIN;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Enable : 1; /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled
|
||||
UINT8 Panel : 1; /// 0: Back Panel Port; 1: Front Panel Port.
|
||||
UINT8 Dock : 1; /// 0: Not docking port; 1: Docking Port.
|
||||
UINT8 Rsvdbits : 5;
|
||||
} PCH_USB_PORT_SETTINGS;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Enable : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 Rsvdbits : 7;
|
||||
} PCH_USB20_CONTROLLER_SETTINGS;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Enable : 2; /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode
|
||||
UINT8 Rsvdbits : 6;
|
||||
} PCH_USBOTG_CONTROLLER_SETTINGS;
|
||||
|
||||
#define PCH_XHCI_MODE_OFF 0
|
||||
#define PCH_XHCI_MODE_ON 1
|
||||
#define PCH_XHCI_MODE_AUTO 2
|
||||
#define PCH_XHCI_MODE_SMARTAUTO 3
|
||||
|
||||
#define PCH_EHCI_DEBUG_OFF 0
|
||||
#define PCH_EHCI_DEBUG_ON 1
|
||||
|
||||
#define PCH_USB_FRONT_PANEL 1
|
||||
#define PCH_USB_BACK_PANEL 0
|
||||
|
||||
typedef struct {
|
||||
UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto
|
||||
UINT8 PreBootSupport : 1; /// 0: No xHCI driver available; 1: xHCI driver available
|
||||
UINT8 XhciStreams : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 Rsvdbits : 4;
|
||||
} PCH_USB30_CONTROLLER_SETTINGS;
|
||||
|
||||
typedef struct {
|
||||
UINT8 UsbPerPortCtl : 1; /// 0: Disable; 1: Enable Per-port enable control
|
||||
UINT8 Ehci1Usbr : 1; /// 0: Disable; 1: Enable EHCI 1 USBR
|
||||
UINT8 RsvdBits : 6;
|
||||
PCH_USB_PORT_SETTINGS PortSettings[PCH_USB_MAX_PHYSICAL_PORTS];
|
||||
PCH_USB20_CONTROLLER_SETTINGS Usb20Settings[PchEhciControllerMax];
|
||||
PCH_USB30_CONTROLLER_SETTINGS Usb30Settings;
|
||||
PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings;
|
||||
PCH_USB_OVERCURRENT_PIN Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS];
|
||||
PCH_USB_OVERCURRENT_PIN Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS];
|
||||
///
|
||||
/// The length of Usb Port to configure the USB transmitter,
|
||||
/// Bits [16:4] represents length of Usb Port in inches using octal format and [3:0] is for the decimal Point.
|
||||
///
|
||||
UINT16 Usb20PortLength[PCH_EHCI_MAX_PORTS];
|
||||
UINT16 EhciDebug;
|
||||
UINT16 UsbXhciLpmSupport;
|
||||
|
||||
} PCH_USB_CONFIG;
|
||||
|
||||
///
|
||||
/// ---------------------------- PCI Express Config ----------------------
|
||||
///
|
||||
/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
|
||||
///
|
||||
typedef enum {
|
||||
PchPcieAspmDisabled,
|
||||
PchPcieAspmL0s,
|
||||
PchPcieAspmL1,
|
||||
PchPcieAspmL0sL1,
|
||||
PchPcieAspmAutoConfig,
|
||||
PchPcieAspmMax
|
||||
} PCH_PCI_EXPRESS_ASPM_CONTROL;
|
||||
|
||||
///
|
||||
/// Refer to PCH EDS for the PCH implementation values corresponding
|
||||
/// to below PCI-E spec defined ranges
|
||||
///
|
||||
typedef enum {
|
||||
PchPciECompletionTO_Default,
|
||||
PchPciECompletionTO_50_100us,
|
||||
PchPciECompletionTO_1_10ms,
|
||||
PchPciECompletionTO_16_55ms,
|
||||
PchPciECompletionTO_65_210ms,
|
||||
PchPciECompletionTO_260_900ms,
|
||||
PchPciECompletionTO_1_3P5s,
|
||||
PchPciECompletionTO_4_13s,
|
||||
PchPciECompletionTO_17_64s,
|
||||
PchPciECompletionTO_Disabled
|
||||
} PCH_PCIE_COMPLETION_TIMEOUT;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Enable : 1; /// Root Port enabling, 0: Disable; 1: Enable.
|
||||
UINT8 Hide : 1; /// Whether or not to hide the configuration space of this port
|
||||
UINT8 SlotImplemented : 1;
|
||||
UINT8 HotPlug : 1;
|
||||
UINT8 PmSci : 1;
|
||||
UINT8 ExtSync : 1; /// Extended Synch
|
||||
UINT8 Rsvdbits : 2;
|
||||
///
|
||||
/// Error handlings
|
||||
///
|
||||
UINT8 UnsupportedRequestReport : 1;
|
||||
UINT8 FatalErrorReport : 1;
|
||||
UINT8 NoFatalErrorReport : 1;
|
||||
UINT8 CorrectableErrorReport : 1;
|
||||
UINT8 PmeInterrupt : 1;
|
||||
UINT8 SystemErrorOnFatalError : 1;
|
||||
UINT8 SystemErrorOnNonFatalError : 1;
|
||||
UINT8 SystemErrorOnCorrectableError : 1;
|
||||
|
||||
UINT8 AdvancedErrorReporting : 1;
|
||||
UINT8 TransmitterHalfSwing : 1;
|
||||
UINT8 Reserved : 6; /// Reserved fields for future expansion w/o protocol change
|
||||
|
||||
UINT8 FunctionNumber; /// The function number this root port is mapped to.
|
||||
UINT8 PhysicalSlotNumber;
|
||||
PCH_PCIE_COMPLETION_TIMEOUT CompletionTimeout;
|
||||
PCH_PCI_EXPRESS_ASPM_CONTROL Aspm;
|
||||
} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG;
|
||||
|
||||
typedef struct {
|
||||
/**
|
||||
VendorId
|
||||
|
||||
The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
|
||||
|
||||
DeviceId
|
||||
|
||||
The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
|
||||
|
||||
RevId
|
||||
|
||||
The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
|
||||
|
||||
BaseClassCode
|
||||
|
||||
The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
|
||||
|
||||
SubClassCode
|
||||
|
||||
The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
|
||||
|
||||
|
||||
EndPointAspm
|
||||
|
||||
The override ASPM setting from End point
|
||||
**/
|
||||
UINT16 VendorId;
|
||||
UINT16 DeviceId;
|
||||
UINT8 RevId;
|
||||
UINT8 BaseClassCode;
|
||||
UINT8 SubClassCode;
|
||||
PCH_PCI_EXPRESS_ASPM_CONTROL EndPointAspm;
|
||||
} PCH_PCIE_DEVICE_ASPM_OVERRIDE;
|
||||
|
||||
typedef struct {
|
||||
UINT16 VendorId; ///< PCI configuration space offset 0
|
||||
UINT16 DeviceId; ///< PCI configuration space offset 2
|
||||
UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings
|
||||
/**
|
||||
SnoopLatency bit definition
|
||||
Note: All Reserved bits must be set to 0
|
||||
|
||||
BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
|
||||
When clear values in bits 9:0 will be ignored
|
||||
BITS[14:13] - Reserved
|
||||
BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
|
||||
000b - 1 ns
|
||||
001b - 32 ns
|
||||
010b - 1024 ns
|
||||
011b - 32,768 ns
|
||||
100b - 1,048,576 ns
|
||||
101b - 33,554,432 ns
|
||||
110b - Reserved
|
||||
111b - Reserved
|
||||
BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
|
||||
the scale in bits 12:10
|
||||
**/
|
||||
UINT16 SnoopLatency;
|
||||
/**
|
||||
NonSnoopLatency bit definition
|
||||
Note: All Reserved bits must be set to 0
|
||||
|
||||
BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
|
||||
When clear values in bits 9:0 will be ignored
|
||||
BITS[14:13] - Reserved
|
||||
BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
|
||||
000b - 1 ns
|
||||
001b - 32 ns
|
||||
010b - 1024 ns
|
||||
011b - 32,768 ns
|
||||
100b - 1,048,576 ns
|
||||
101b - 33,554,432 ns
|
||||
110b - Reserved
|
||||
111b - Reserved
|
||||
BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
|
||||
the scale in bits 12:10
|
||||
**/
|
||||
UINT16 NonSnoopLatency;
|
||||
} PCH_PCIE_DEVICE_LTR_OVERRIDE;
|
||||
|
||||
typedef struct {
|
||||
///
|
||||
/// Temp Bus Number range available to be assigned to
|
||||
/// each root port and its downstream devices for initialization
|
||||
/// of these devices before PCI Bus enumeration
|
||||
///
|
||||
UINT8 TempRootPortBusNumMin;
|
||||
UINT8 TempRootPortBusNumMax;
|
||||
PCH_PCI_EXPRESS_ROOT_PORT_CONFIG RootPort[PCH_PCIE_MAX_ROOT_PORTS];
|
||||
BOOLEAN RootPortClockGating;
|
||||
UINT8 NumOfDevAspmOverride; /// Number of PCI Express card Aspm setting override
|
||||
PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; /// The Pointer which is point to Pci Express card Aspm setting override
|
||||
UINT8 PcieDynamicGating; /// Need PMC enable it first from PMC 0x3_12 MCU 318.
|
||||
} PCH_PCI_EXPRESS_CONFIG;
|
||||
|
||||
|
||||
///
|
||||
/// ---------------------------- SATA Config -----------------------------
|
||||
///
|
||||
typedef enum {
|
||||
PchSataSpeedSupportGen1 = 1,
|
||||
PchSataSpeedSupportGen2
|
||||
} PCH_SATA_SPEED_SUPPORT;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Enable : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 HotPlug : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 MechSw : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 External : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 SpinUp : 1; /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device
|
||||
UINT8 Rsvdbits : 3; /// Reserved fields for future expansion w/o protocol change
|
||||
} PCH_SATA_PORT_SETTINGS;
|
||||
|
||||
typedef struct {
|
||||
PCH_SATA_PORT_SETTINGS PortSettings[PCH_AHCI_MAX_PORTS];
|
||||
UINT8 RaidAlternateId : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 Raid0 : 1; /// 0: Disable; 1: Enable RAID0
|
||||
UINT8 Raid1 : 1; /// 0: Disable; 1: Enable RAID1
|
||||
UINT8 Raid10 : 1; /// 0: Disable; 1: Enable RAID10
|
||||
UINT8 Raid5 : 1; /// 0: Disable; 1: Enable RAID5
|
||||
UINT8 Irrt : 1; /// 0: Disable; 1: Enable Intel Rapid Recovery Technology
|
||||
UINT8 OromUiBanner : 1; /// 0: Disable; 1: Enable OROM UI and BANNER
|
||||
UINT8 HddUnlock : 1; /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled
|
||||
|
||||
UINT8 LedLocate : 1; /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
|
||||
UINT8 IrrtOnly : 1; /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports
|
||||
UINT8 TestMode : 1; /// 0: Disable; 1: Allow entrance to the PCH SATA test modes
|
||||
UINT8 SalpSupport : 1; /// 0: Disable; 1: Enable Aggressive Link Power Management
|
||||
UINT8 LegacyMode : 1; /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode
|
||||
UINT8 SpeedSupport : 4; /// Indicates the maximum speed the SATA controller can support
|
||||
/// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2)
|
||||
|
||||
UINT8 Rsvdbits : 7; // Reserved fields for future expansion w/o protocol change
|
||||
} PCH_SATA_CONFIG;
|
||||
///
|
||||
/// --------------------------- AZALIA Config ------------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT32 VendorDeviceId;
|
||||
UINT16 SubSystemId;
|
||||
UINT8 RevisionId; /// 0xFF applies to all steppings
|
||||
UINT8 FrontPanelSupport;
|
||||
UINT16 NumberOfRearJacks;
|
||||
UINT16 NumberOfFrontJacks;
|
||||
} PCH_AZALIA_VERB_TABLE_HEADER;
|
||||
|
||||
typedef struct {
|
||||
PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader;
|
||||
UINT32 *VerbTableData;
|
||||
} PCH_AZALIA_VERB_TABLE;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Pme : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported
|
||||
UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached
|
||||
UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable
|
||||
UINT8 Rsvdbits : 3;
|
||||
UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform
|
||||
PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s)
|
||||
UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds
|
||||
} PCH_AZALIA_CONFIG;
|
||||
|
||||
///
|
||||
/// --------------------------- Smbus Config ------------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 NumRsvdSmbusAddresses;
|
||||
UINT8 *RsvdSmbusAddressTable;
|
||||
} PCH_SMBUS_CONFIG;
|
||||
|
||||
///
|
||||
/// --------------------------- Miscellaneous PM Config ------------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 MeWakeSts : 1;
|
||||
UINT8 MeHrstColdSts : 1;
|
||||
UINT8 MeHrstWarmSts : 1;
|
||||
UINT8 MeHostPowerDn : 1;
|
||||
UINT8 WolOvrWkSts : 1;
|
||||
UINT8 Rsvdbits : 3;
|
||||
} PCH_POWER_RESET_STATUS;
|
||||
|
||||
typedef struct {
|
||||
UINT8 PmeB0S5Dis : 1;
|
||||
UINT8 WolEnableOverride : 1;
|
||||
UINT8 Rsvdbits : 6;
|
||||
} PCH_WAKE_CONFIG;
|
||||
|
||||
typedef enum {
|
||||
PchSlpS360us,
|
||||
PchSlpS31ms,
|
||||
PchSlpS350ms,
|
||||
PchSlpS32s
|
||||
} PCH_SLP_S3_MIN_ASSERT;
|
||||
|
||||
typedef enum {
|
||||
PchSlpS4PchTime, /// The time defined in EDS Power Sequencing and Reset Signal Timings table
|
||||
PchSlpS41s,
|
||||
PchSlpS42s,
|
||||
PchSlpS43s,
|
||||
PchSlpS44s
|
||||
} PCH_SLP_S4_MIN_ASSERT;
|
||||
|
||||
typedef struct {
|
||||
///
|
||||
/// Specify which Power/Reset bits need to be cleared by
|
||||
/// the PCH Init Driver.
|
||||
/// Usually platform drivers take care of these bits, but if
|
||||
/// not, let PCH Init driver clear the bits.
|
||||
///
|
||||
PCH_POWER_RESET_STATUS PowerResetStatusClear;
|
||||
///
|
||||
/// Specify Wake Policy
|
||||
///
|
||||
PCH_WAKE_CONFIG WakeConfig;
|
||||
///
|
||||
/// SLP_XX Minimum Assertion Width Policy
|
||||
///
|
||||
PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert;
|
||||
PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert;
|
||||
UINT8 SlpStrchSusUp : 1; /// Enable/Disable SLP_X Stretching After SUS Well Power Up
|
||||
UINT8 SlpLanLowDc : 1;
|
||||
UINT8 Rsvdbits : 6;
|
||||
} PCH_MISC_PM_CONFIG;
|
||||
|
||||
///
|
||||
/// --------------------------- Subsystem Vendor ID / Subsystem ID Config -----
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 SubSystemVendorId;
|
||||
UINT16 SubSystemId;
|
||||
} PCH_DEFAULT_SVID_SID;
|
||||
|
||||
///
|
||||
/// --------------------------- Lock Down Config ------------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 GlobalSmi : 1;
|
||||
UINT8 BiosInterface : 1;
|
||||
UINT8 RtcLock : 1;
|
||||
UINT8 BiosLock : 1;
|
||||
UINT8 Rsvdbits : 4;
|
||||
UINT8 PchBiosLockSwSmiNumber;
|
||||
} PCH_LOCK_DOWN_CONFIG;
|
||||
//
|
||||
// --------------------------- Serial IRQ Config ------------------------------
|
||||
//
|
||||
typedef enum {
|
||||
PchQuietMode,
|
||||
PchContinuousMode
|
||||
} PCH_SIRQ_MODE;
|
||||
///
|
||||
/// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode
|
||||
///
|
||||
|
||||
typedef struct {
|
||||
BOOLEAN SirqEnable; /// Determines if enable Serial IRQ
|
||||
PCH_SIRQ_MODE SirqMode; /// Serial IRQ Mode Select
|
||||
} PCH_LPC_SIRQ_CONFIG;
|
||||
|
||||
///
|
||||
/// --------------------------- Power Optimizer Config ------------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 NumOfDevLtrOverride; /// Number of Pci Express card listed in LTR override table
|
||||
PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; /// Pointer to Pci Express devices LTR override table
|
||||
} PCH_PWR_OPT_CONFIG;
|
||||
|
||||
///
|
||||
/// --------------------- Low Power Input Output Config ------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled
|
||||
UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled
|
||||
UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled
|
||||
UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled
|
||||
UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled
|
||||
UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled
|
||||
UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled
|
||||
UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled
|
||||
UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled
|
||||
UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled
|
||||
UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled
|
||||
UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled
|
||||
UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled
|
||||
UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled
|
||||
UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled
|
||||
UINT8 Rsvdbits : 2;
|
||||
} PCH_LPSS_CONFIG;
|
||||
|
||||
///
|
||||
/// ----------------------------- SCC Config --------------------------------
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 eMMCEnabled : 1; /// Determines if SCC eMMC enabled
|
||||
UINT8 SdioEnabled : 1; /// Determines if SCC SDIO enabled
|
||||
UINT8 SdcardEnabled : 1; /// Determines if SCC SD Card enabled
|
||||
UINT8 HsiEnabled : 1; /// Determines if SCC HSI enabled
|
||||
UINT8 eMMC45Enabled : 1; /// Determines if SCC eMMC 4.5 enabled
|
||||
UINT8 eMMC45DDR50Enabled : 1; /// Determines if DDR50 enabled for eMMC 4.5
|
||||
UINT8 eMMC45HS200Enabled : 1; /// Determines if HS200nabled for eMMC 4.5
|
||||
UINT8 Rsvdbits : 1;
|
||||
UINT8 SdCardSDR25Enabled : 1; /// Determines if SDR25 for SD Card
|
||||
UINT8 SdCardDDR50Enabled : 1; /// Determines if DDR50 for SD Card
|
||||
UINT8 Rsvdbits1 : 6;
|
||||
UINT8 eMMC45RetuneTimerValue; /// Determines retune timer value.
|
||||
} PCH_SCC_CONFIG;
|
||||
|
||||
///
|
||||
/// ------------ General PCH Platform Policy protocol definition ------------
|
||||
///
|
||||
struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL {
|
||||
UINT8 Revision;
|
||||
UINT8 BusNumber; /// PCI Bus Number of the PCH device
|
||||
PCH_DEVICE_ENABLING *DeviceEnabling;
|
||||
PCH_USB_CONFIG *UsbConfig;
|
||||
PCH_PCI_EXPRESS_CONFIG *PciExpressConfig;
|
||||
|
||||
PCH_SATA_CONFIG *SataConfig;
|
||||
PCH_AZALIA_CONFIG *AzaliaConfig;
|
||||
PCH_SMBUS_CONFIG *SmbusConfig;
|
||||
PCH_MISC_PM_CONFIG *MiscPmConfig;
|
||||
PCH_DEFAULT_SVID_SID *DefaultSvidSid;
|
||||
PCH_LOCK_DOWN_CONFIG *LockDownConfig;
|
||||
PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
|
||||
PCH_PWR_OPT_CONFIG *PwrOptConfig;
|
||||
PCH_LPSS_CONFIG *LpssConfig;
|
||||
PCH_SCC_CONFIG *SccConfig;
|
||||
UINT8 IdleReserve;
|
||||
UINT8 EhciPllCfgEnable;
|
||||
UINT8 AcpiHWRed; //Hardware Reduced Mode
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,120 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchReset.h
|
||||
|
||||
@brief
|
||||
PCH Reset Protocol
|
||||
|
||||
**/
|
||||
#ifndef _PCH_RESET_H_
|
||||
#define _PCH_RESET_H_
|
||||
|
||||
|
||||
//
|
||||
#define PCH_RESET_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xdb63592c, 0xb8cc, 0x44c8, 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a \
|
||||
}
|
||||
#define PCH_RESET_CALLBACK_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x3a3300ab, 0xc929, 0x487d, 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 \
|
||||
}
|
||||
extern EFI_GUID gPchResetProtocolGuid;
|
||||
extern EFI_GUID gPchResetCallbackProtocolGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL;
|
||||
|
||||
typedef struct _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL;
|
||||
|
||||
///
|
||||
/// Related Definitions
|
||||
///
|
||||
///
|
||||
/// PCH Reset Types
|
||||
///
|
||||
typedef enum {
|
||||
ColdReset,
|
||||
WarmReset,
|
||||
ShutdownReset,
|
||||
PowerCycleReset,
|
||||
GlobalReset,
|
||||
GlobalResetWithEc
|
||||
} PCH_RESET_TYPE;
|
||||
|
||||
///
|
||||
/// Member functions
|
||||
///
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PCH_RESET) (
|
||||
IN PCH_RESET_PROTOCOL * This,
|
||||
IN PCH_RESET_TYPE PchResetType
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
Execute Pch Reset from the host controller.
|
||||
|
||||
@param[in] This Pointer to the PCH_RESET_PROTOCOL instance.
|
||||
@param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset,
|
||||
PowerCycleReset, GlobalReset, GlobalResetWithEc
|
||||
|
||||
@retval EFI_SUCCESS Successfully completed.
|
||||
@retval EFI_INVALID_PARAMETER If ResetType is invalid.
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *PCH_RESET_CALLBACK) (
|
||||
IN PCH_RESET_TYPE PchResetType
|
||||
)
|
||||
/**
|
||||
|
||||
@brief
|
||||
Execute call back function for Pch Reset.
|
||||
|
||||
@param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset.
|
||||
|
||||
@retval EFI_SUCCESS The callback function has been done successfully
|
||||
@retval EFI_NOT_FOUND Failed to find Pch Reset Callback protocol. Or, none of
|
||||
callback protocol is installed.
|
||||
@retval Others Do not do any reset from PCH
|
||||
|
||||
**/
|
||||
;
|
||||
|
||||
///
|
||||
/// Interface structure for the Pch Reset Protocol
|
||||
///
|
||||
struct _PCH_RESET_PROTOCOL {
|
||||
PCH_RESET Reset;
|
||||
};
|
||||
|
||||
///
|
||||
/// PCH_RESET_CALLBACK_PROTOCOL Structure Definition
|
||||
///
|
||||
struct _PCH_RESET_CALLBACK_PROTOCOL {
|
||||
PCH_RESET_CALLBACK ResetCallback;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,138 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
PchS3Support.h
|
||||
|
||||
@brief
|
||||
This file defines the PCH S3 support Protocol.
|
||||
|
||||
**/
|
||||
#ifndef _PCH_S3_SUPPORT_PROTOCOL_H_
|
||||
#define _PCH_S3_SUPPORT_PROTOCOL_H_
|
||||
|
||||
#ifndef ECP_FLAG
|
||||
#include <Pi/PiS3BootScript.h>
|
||||
#endif
|
||||
|
||||
#define EFI_PCH_S3_SUPPORT_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xe287d20b, 0xd897, 0x4e1e, 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 \
|
||||
}
|
||||
|
||||
#include <Protocol/PchPlatformPolicy.h>
|
||||
|
||||
///
|
||||
/// Extern the GUID for protocol users.
|
||||
///
|
||||
extern EFI_GUID gEfiPchS3SupportProtocolGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _EFI_PCH_S3_SUPPORT_PROTOCOL EFI_PCH_S3_SUPPORT_PROTOCOL;
|
||||
|
||||
typedef enum {
|
||||
PchS3ItemTypeSendCodecCommand,
|
||||
PchS3ItemTypePollStatus,
|
||||
PchS3ItemTypeInitPcieRootPortDownstream,
|
||||
PchS3ItemTypePcieSetPm,
|
||||
PchS3ItemTypePmTimerStall,
|
||||
PchS3ItemTypeMax
|
||||
} EFI_PCH_S3_DISPATCH_ITEM_TYPE;
|
||||
|
||||
///
|
||||
/// It's better not to use pointer here because the size of pointer in DXE is 8, but it's 4 in PEI
|
||||
/// plug 4 to ParameterSize in PEIM if you really need it
|
||||
///
|
||||
typedef struct {
|
||||
UINT32 HdaBar;
|
||||
UINT32 CodecCmdData;
|
||||
} EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND;
|
||||
|
||||
typedef struct {
|
||||
UINT64 MmioAddress;
|
||||
EFI_BOOT_SCRIPT_WIDTH Width;
|
||||
UINT64 Mask;
|
||||
UINT64 Value;
|
||||
UINT32 Timeout; // us
|
||||
} EFI_PCH_S3_PARAMETER_POLL_STATUS;
|
||||
|
||||
typedef struct {
|
||||
UINT8 RootPortBus;
|
||||
UINT8 RootPortDevice;
|
||||
UINT8 RootPortFunc;
|
||||
UINT8 TempBusNumberMin;
|
||||
UINT8 TempBusNumberMax;
|
||||
} EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM;
|
||||
|
||||
typedef struct {
|
||||
UINT8 RootPortBus;
|
||||
UINT8 RootPortDevice;
|
||||
UINT8 RootPortFunc;
|
||||
PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm;
|
||||
UINT8 NumOfDevAspmOverride;
|
||||
UINT32 DevAspmOverrideAddr;
|
||||
UINT8 TempBusNumberMin;
|
||||
UINT8 TempBusNumberMax;
|
||||
UINT8 NumOfDevLtrOverride;
|
||||
UINT32 DevLtrOverrideAddr;
|
||||
} EFI_PCH_S3_PARAMETER_PCIE_SET_PM;
|
||||
|
||||
typedef struct {
|
||||
UINT32 DelayTime; // us
|
||||
} EFI_PCH_S3_PARAMETER_PM_TIMER_STALL;
|
||||
|
||||
typedef struct {
|
||||
EFI_PCH_S3_DISPATCH_ITEM_TYPE Type;
|
||||
VOID *Parameter;
|
||||
} EFI_PCH_S3_DISPATCH_ITEM;
|
||||
|
||||
///
|
||||
/// Member functions
|
||||
///
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM) (
|
||||
IN EFI_PCH_S3_SUPPORT_PROTOCOL * This,
|
||||
IN EFI_PCH_S3_DISPATCH_ITEM * DispatchItem,
|
||||
OUT EFI_PHYSICAL_ADDRESS * S3DispatchEntryPoint
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
@brief
|
||||
Set an item to be dispatched at S3 resume time. At the same time, the entry point
|
||||
of the PCH S3 support image is returned to be used in subsequent boot script save
|
||||
call
|
||||
|
||||
@param[in] This Pointer to the protocol instance.
|
||||
@param[in] DispatchItem The item to be dispatched.
|
||||
@param[in] S3DispatchEntryPoint The entry point of the PCH S3 support image.
|
||||
|
||||
@retval EFI_STATUS Successfully completed.
|
||||
@retval EFI_OUT_OF_RESOURCES Out of resources.
|
||||
|
||||
**/
|
||||
|
||||
///
|
||||
/// Protocol definition
|
||||
///
|
||||
struct _EFI_PCH_S3_SUPPORT_PROTOCOL {
|
||||
EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,415 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
|
||||
/*++
|
||||
Module Name:
|
||||
|
||||
SdHostIo.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Interface definition for EFI_SD_HOST_IO_PROTOCOL
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _SD_HOST_IO_H
|
||||
#define _SD_HOST_IO_H
|
||||
|
||||
|
||||
// Global ID for the EFI_SD_HOST_IO_PROTOCOL
|
||||
// {B63F8EC7-A9C9-4472-A4C0-4D8BF365CC51}
|
||||
//
|
||||
#define EFI_SD_HOST_IO_PROTOCOL_GUID \
|
||||
{ 0xb63f8ec7, 0xa9c9, 0x4472, { 0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51 } }
|
||||
|
||||
typedef struct _EFI_SD_HOST_IO_PROTOCOL EFI_SD_HOST_IO_PROTOCOL;
|
||||
|
||||
//
|
||||
// TODO: Move to Pci22.h
|
||||
//
|
||||
#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
|
||||
#define PCI_IF_STANDARD_HOST_NO_DMA 0x00
|
||||
#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01
|
||||
|
||||
//
|
||||
// TODO: Retire
|
||||
//
|
||||
#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01
|
||||
|
||||
//
|
||||
// TODO: Do these belong in an Industry Standard include file?
|
||||
//
|
||||
// MMIO Registers definition for MMC/SDIO controller
|
||||
//
|
||||
#define MMIO_DMAADR 0x00
|
||||
#define MMIO_BLKSZ 0x04
|
||||
#define MMIO_BLKCNT 0x06
|
||||
#define MMIO_CMDARG 0x08
|
||||
#define MMIO_XFRMODE 0x0C
|
||||
#define MMIO_SDCMD 0x0E
|
||||
#define MMIO_RESP 0x10
|
||||
#define MMIO_BUFDATA 0x20
|
||||
#define MMIO_PSTATE 0x24
|
||||
#define MMIO_HOSTCTL 0x28
|
||||
#define MMIO_PWRCTL 0x29
|
||||
#define MMIO_BLKGAPCTL 0x2A
|
||||
#define MMIO_WAKECTL 0x2B
|
||||
#define MMIO_CLKCTL 0x2C
|
||||
#define MMIO_TOCTL 0x2E
|
||||
#define MMIO_SWRST 0x2F
|
||||
#define MMIO_NINTSTS 0x30
|
||||
#define MMIO_ERINTSTS 0x32
|
||||
#define MMIO_NINTEN 0x34
|
||||
#define MMIO_ERINTEN 0x36
|
||||
#define MMIO_NINTSIGEN 0x38
|
||||
#define MMIO_ERINTSIGEN 0x3A
|
||||
#define MMIO_AC12ERRSTS 0x3C
|
||||
#define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2
|
||||
#define MMIO_CAP 0x40
|
||||
#define MMIO_CAP2 0x44 //hphang <- New in VLV2
|
||||
#define MMIO_MCCAP 0x48
|
||||
#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2
|
||||
#define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2
|
||||
#define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2
|
||||
#define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2
|
||||
#define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2
|
||||
#define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2
|
||||
#define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2
|
||||
#define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2
|
||||
#define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2
|
||||
#define MMIO_SLTINTSTS 0xFC
|
||||
#define MMIO_CTRLRVER 0xFE
|
||||
|
||||
typedef enum {
|
||||
ResponseNo = 0,
|
||||
ResponseR1,
|
||||
ResponseR1b,
|
||||
ResponseR2,
|
||||
ResponseR3,
|
||||
ResponseR4,
|
||||
ResponseR5,
|
||||
ResponseR5b,
|
||||
ResponseR6,
|
||||
ResponseR7
|
||||
} RESPONSE_TYPE;
|
||||
|
||||
typedef enum {
|
||||
NoData = 0,
|
||||
InData,
|
||||
OutData
|
||||
} TRANSFER_TYPE;
|
||||
|
||||
typedef enum {
|
||||
Reset_Auto = 0,
|
||||
Reset_DAT,
|
||||
Reset_CMD,
|
||||
Reset_DAT_CMD,
|
||||
Reset_All,
|
||||
Reset_HW
|
||||
} RESET_TYPE;
|
||||
|
||||
|
||||
typedef enum {
|
||||
SDMA = 0,
|
||||
ADMA2,
|
||||
PIO
|
||||
} DMA_MOD;
|
||||
|
||||
typedef struct {
|
||||
UINT32 HighSpeedSupport: 1; //High speed supported
|
||||
UINT32 V18Support: 1; //1.8V supported
|
||||
UINT32 V30Support: 1; //3.0V supported
|
||||
UINT32 V33Support: 1; //3.3V supported
|
||||
UINT32 SDR50Support: 1;
|
||||
UINT32 SDR104Support: 1;
|
||||
UINT32 DDR50Support: 1;
|
||||
UINT32 Reserved0: 1;
|
||||
UINT32 BusWidth4: 1; // 4 bit width
|
||||
UINT32 BusWidth8: 1; // 8 bit width
|
||||
UINT32 Reserved1: 6;
|
||||
UINT32 SDMASupport: 1;
|
||||
UINT32 ADMA2Support: 1;
|
||||
UINT32 DmaMode: 2;
|
||||
UINT32 ReTuneTimer: 4;
|
||||
UINT32 ReTuneMode: 2;
|
||||
UINT32 Reserved2: 6;
|
||||
UINT32 BoundarySize;
|
||||
} HOST_CAPABILITY;
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
The main function used to send the command to the card inserted into the SD host
|
||||
slot.
|
||||
It will assemble the arguments to set the command register and wait for the command
|
||||
and transfer completed until timeout. Then it will read the response register to fill
|
||||
the ResponseData
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
CommandIndex - The command index to set the command index field of command register
|
||||
Argument - Command argument to set the argument field of command register
|
||||
DataType - TRANSFER_TYPE, indicates no data, data in or data out
|
||||
Buffer - Contains the data read from / write to the device
|
||||
BufferSize - The size of the buffer
|
||||
ResponseType - RESPONSE_TYPE
|
||||
TimeOut - Time out value in 1 ms unit
|
||||
ResponseData - Depending on the ResponseType, such as CSD or card status
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
EFI_OUT_OF_RESOURCES
|
||||
EFI_TIMEOUT
|
||||
EFI_DEVICE_ERROR
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN UINT16 CommandIndex,
|
||||
IN UINT32 Argument,
|
||||
IN TRANSFER_TYPE DataType,
|
||||
IN UINT8 *Buffer, OPTIONAL
|
||||
IN UINT32 BufferSize,
|
||||
IN RESPONSE_TYPE ResponseType,
|
||||
IN UINT32 TimeOut,
|
||||
OUT UINT32 *ResponseData OPTIONAL
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set max clock frequency of the host, the actual frequency
|
||||
may not be the same as MaxFrequency. It depends on
|
||||
the max frequency the host can support, divider, and host
|
||||
speed mode.
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
MaxFrequency - Max frequency in HZ
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN UINT32 MaxFrequency
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set bus width of the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
BusWidth - Bus width in 1, 4, 8 bits
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN UINT32 BusWidth
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set voltage which could supported by the host.
|
||||
Support 0(Power off the host), 1.8V, 3.0V, 3.3V
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
Voltage - Units in 0.1 V
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN UINT32 Voltage
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set Host High Speed
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
HighSpeed - True for High Speed Mode set, false for normal mode
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN UINT32 HighSpeed
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set High Speed Mode
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
SetHostDdrMode - True for DDR Mode set, false for normal mode
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_INVALID_PARAMETER
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN UINT32 DdrMode
|
||||
);
|
||||
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Reset the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
ResetAll - TRUE to reset all
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN RESET_TYPE ResetType
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Reset the host
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
Enable - TRUE to enable, FALSE to disable
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN BOOLEAN Enable
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Find whether these is a card inserted into the slot. If so
|
||||
init the host. If not, return EFI_NOT_FOUND.
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_NOT_FOUND
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This
|
||||
);
|
||||
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
Set the Block length
|
||||
|
||||
Arguments:
|
||||
This - Pointer to EFI_SD_HOST_IO_PROTOCOL
|
||||
BlockLength - card supportes block length
|
||||
|
||||
Returns:
|
||||
EFI_SUCCESS
|
||||
EFI_TIMEOUT
|
||||
|
||||
--*/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) (
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This,
|
||||
IN UINT32 BlockLength
|
||||
);
|
||||
|
||||
typedef EFI_STATUS
|
||||
(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE)(
|
||||
IN EFI_SD_HOST_IO_PROTOCOL *This
|
||||
);
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Interface structure for the EFI SD Host I/O Protocol
|
||||
//
|
||||
struct _EFI_SD_HOST_IO_PROTOCOL {
|
||||
UINT32 Revision;
|
||||
HOST_CAPABILITY HostCapability;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND SendCommand;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY SetClockFrequency;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH SetBusWidth;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE SetHostVoltage;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode;
|
||||
EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST ResetSdHost;
|
||||
EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;
|
||||
EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH SetBlockLength;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE SetupDevice;
|
||||
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE SetHostSpeedMode;
|
||||
};
|
||||
|
||||
extern EFI_GUID gEfiSdHostIoProtocolGuid;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
SmbiosSlotPopulation.h
|
||||
|
||||
Abstract:
|
||||
|
||||
EFI SMBIOS slot structure control code.
|
||||
|
||||
GUID:
|
||||
{EF7BF7D6-F8FF-4a76-8247-C0D0D1CC49C0}
|
||||
0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0
|
||||
|
||||
Revision History
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _EFI_SMBIOS_SLOT_POPULATION_H_
|
||||
#define _EFI_SMBIOS_SLOT_POPULATION_H_
|
||||
|
||||
//
|
||||
// Slot Population Protocol GUID
|
||||
//
|
||||
#define EFI_SMBIOS_SLOT_POPULATION_GUID \
|
||||
{ 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 }
|
||||
|
||||
typedef struct {
|
||||
UINT16 SmbiosSlotId; // SMBIOS Slot ID
|
||||
BOOLEAN InUse; // Does the slot have a card in it
|
||||
BOOLEAN Disabled; // Should the slot information be in SMBIOS
|
||||
} EFI_SMBIOS_SLOT_ENTRY;
|
||||
|
||||
typedef struct {
|
||||
UINT32 NumberOfEntries;
|
||||
EFI_SMBIOS_SLOT_ENTRY *SlotEntries;
|
||||
} EFI_SMBIOS_SLOT_POPULATION_INFO;
|
||||
|
||||
extern EFI_GUID gEfiSmbiosSlotPopulationGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,165 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
SmmIchnDispatchEx.h
|
||||
|
||||
@brief
|
||||
SmmIchnDispatch Extended Protocol
|
||||
|
||||
**/
|
||||
#ifndef _EFI_SMM_ICHN_DISPATCH_EX_H_
|
||||
#define _EFI_SMM_ICHN_DISPATCH_EX_H_
|
||||
|
||||
#ifdef ECP_FLAG
|
||||
#include <Protocol/SmmIchnDispatch/SmmIchnDispatch.h>
|
||||
#else
|
||||
#include <Protocol/SmmIchnDispatch.h>
|
||||
#endif
|
||||
|
||||
#define EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x3920405b, 0xc897, 0x44da, 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 \
|
||||
}
|
||||
extern EFI_GUID gEfiSmmIchnDispatchExProtocolGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL;
|
||||
|
||||
///
|
||||
/// Related Definitions
|
||||
///
|
||||
///
|
||||
/// Ichn Dispatch Extended Types
|
||||
///
|
||||
typedef enum {
|
||||
IchnExPciExpress = NUM_ICHN_TYPES + 1,
|
||||
IchnExMonitor,
|
||||
IchnExSpi,
|
||||
IchnExQRT,
|
||||
IchnExGpioUnlock,
|
||||
IchnExTmrOverflow,
|
||||
IchnExPcie0Hotplug,
|
||||
IchnExPcie1Hotplug,
|
||||
IchnExPcie2Hotplug,
|
||||
IchnExPcie3Hotplug,
|
||||
IchnExPcie0LinkActive,
|
||||
IchnExPcie1LinkActive,
|
||||
IchnExPcie2LinkActive,
|
||||
IchnExPcie3LinkActive,
|
||||
///
|
||||
/// INSERT NEW ITEMS JUST BEFORE THIS LINE
|
||||
///
|
||||
IchnExTypeMAX /// the maximum number of items in this enumeration
|
||||
} EFI_SMM_ICHN_EX_SMI_TYPE;
|
||||
|
||||
typedef struct {
|
||||
EFI_SMM_ICHN_EX_SMI_TYPE Type;
|
||||
} EFI_SMM_ICHN_DISPATCH_EX_CONTEXT;
|
||||
|
||||
///
|
||||
/// Member functions
|
||||
///
|
||||
typedef
|
||||
VOID
|
||||
(EFIAPI *EFI_SMM_ICHN_DISPATCH_EX) (
|
||||
IN EFI_HANDLE DispatchHandle,
|
||||
IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
@brief
|
||||
Dispatch function for a ICH n Extended specific SMI handler.
|
||||
|
||||
@param[in] DispatchHandle Handle of this dispatch function.
|
||||
@param[in] DispatchContext Pointer to the dispatch function's context.
|
||||
The DispatchContext fields are filled in
|
||||
by the dispatching driver prior to
|
||||
invoking this dispatch function.
|
||||
|
||||
@retval None
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SMM_ICHN_EX_REGISTER) (
|
||||
IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This,
|
||||
IN EFI_SMM_ICHN_DISPATCH_EX DispatchFunction,
|
||||
IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext,
|
||||
OUT EFI_HANDLE * DispatchHandle
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
@brief
|
||||
Register a child SMI source dispatch function with a parent SMM driver
|
||||
|
||||
@param[in] This Protocol instance pointer.
|
||||
@param[in] DispatchFunction Pointer to dispatch function to be invoked for
|
||||
this SMI source
|
||||
@param[in] DispatchContext Pointer to the dispatch function's context.
|
||||
The caller fills this context in before calling
|
||||
the register function to indicate to the register
|
||||
function the ICHN SMI source for which the dispatch
|
||||
function should be invoked.
|
||||
@param[in] DispatchHandle Handle of dispatch function, for when interfacing
|
||||
with the parent SMM driver.
|
||||
|
||||
@retval EFI_SUCCESS The dispatch function has been successfully
|
||||
registered and the SMI source has been enabled.
|
||||
@retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
|
||||
@retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this
|
||||
child.
|
||||
@retval EFI_INVALID_PARAMETER DispatchContext is invalid. The ICHN input value
|
||||
is not within valid range.
|
||||
|
||||
**/
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SMM_ICHN_EX_UNREGISTER) (
|
||||
IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This,
|
||||
IN EFI_HANDLE DispatchHandle
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
@brief
|
||||
Unregister a child SMI source dispatch function with a parent SMM driver
|
||||
|
||||
@param[in] This Protocol instance pointer.
|
||||
@param[in] DispatchHandle Handle of dispatch function to deregister.
|
||||
|
||||
@retval EFI_SUCCESS The dispatch function has been successfully
|
||||
unregistered and the SMI source has been disabled
|
||||
if there are no other registered child dispatch
|
||||
functions for this SMI source.
|
||||
@retval EFI_INVALID_PARAMETER Handle is invalid.
|
||||
@retval Others TBD
|
||||
|
||||
**/
|
||||
|
||||
///
|
||||
/// Interface structure for the SMM Ich n specific SMI Dispatch Protocol
|
||||
///
|
||||
typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL {
|
||||
EFI_SMM_ICHN_EX_REGISTER Register;
|
||||
EFI_SMM_ICHN_EX_UNREGISTER UnRegister;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,45 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
SmmSmbus.h
|
||||
|
||||
Abstract:
|
||||
|
||||
SmmSmbus Protocol
|
||||
|
||||
--*/
|
||||
#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__
|
||||
#define __EFI_SMM_SMBUS_PROTOCOL_H__
|
||||
|
||||
//
|
||||
// GUID for the SmmSmbus Protocol
|
||||
//
|
||||
// EDK and EDKII have different GUID formats
|
||||
//
|
||||
|
||||
#define EFI_SMM_SMBUS_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x72e40094, 0x2ee1, 0x497a, 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc \
|
||||
}
|
||||
|
||||
//
|
||||
// Resuse the DXE definition, and use another GUID.
|
||||
//
|
||||
typedef EFI_SMBUS_HC_PROTOCOL SMM_SMBUS_HC_PROTOCOL;
|
||||
|
||||
extern EFI_GUID gEfiSmmSmbusProtocolGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,266 @@
|
||||
/**
|
||||
**/
|
||||
/**
|
||||
|
||||
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
@file
|
||||
Spi.h
|
||||
|
||||
@brief
|
||||
This file defines the EFI SPI Protocol which implements the
|
||||
Intel(R) ICH SPI Host Controller Compatibility Interface.
|
||||
|
||||
**/
|
||||
#ifndef _EFI_SPI_H_
|
||||
#define _EFI_SPI_H_
|
||||
|
||||
|
||||
//
|
||||
#define EFI_SPI_PROTOCOL_GUID \
|
||||
{ \
|
||||
0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \
|
||||
}
|
||||
#define EFI_SMM_SPI_PROTOCOL_GUID \
|
||||
{ \
|
||||
0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \
|
||||
}
|
||||
extern EFI_GUID gEfiSpiProtocolGuid;
|
||||
extern EFI_GUID gEfiSmmSpiProtocolGuid;
|
||||
|
||||
///
|
||||
/// Forward reference for ANSI C compatibility
|
||||
///
|
||||
typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;
|
||||
|
||||
///
|
||||
/// SPI protocol data structures and definitions
|
||||
///
|
||||
///
|
||||
/// Number of Prefix Opcodes allowed on the SPI interface
|
||||
///
|
||||
#define SPI_NUM_PREFIX_OPCODE 2
|
||||
|
||||
///
|
||||
/// Number of Opcodes in the Opcode Menu
|
||||
///
|
||||
#define SPI_NUM_OPCODE 8
|
||||
|
||||
///
|
||||
/// Opcode Type
|
||||
/// EnumSpiOpcodeCommand: Command without address
|
||||
/// EnumSpiOpcodeRead: Read with address
|
||||
/// EnumSpiOpcodeWrite: Write with address
|
||||
///
|
||||
typedef enum {
|
||||
EnumSpiOpcodeReadNoAddr,
|
||||
EnumSpiOpcodeWriteNoAddr,
|
||||
EnumSpiOpcodeRead,
|
||||
EnumSpiOpcodeWrite,
|
||||
EnumSpiOpcodeMax
|
||||
} SPI_OPCODE_TYPE;
|
||||
|
||||
typedef enum {
|
||||
EnumSpiCycle20MHz,
|
||||
EnumSpiCycle33MHz,
|
||||
EnumSpiCycle66MHz, /// Not supported by VLV
|
||||
EnumSpiCycle50MHz,
|
||||
EnumSpiCycleMax
|
||||
} SPI_CYCLE_FREQUENCY;
|
||||
|
||||
typedef enum {
|
||||
EnumSpiRegionAll,
|
||||
EnumSpiRegionBios,
|
||||
EnumSpiRegionSeC,
|
||||
EnumSpiRegionDescriptor,
|
||||
EnumSpiRegionPlatformData,
|
||||
EnumSpiRegionMax
|
||||
} SPI_REGION_TYPE;
|
||||
|
||||
///
|
||||
/// Hardware Sequencing required operations (as listed in Valleyview EDS "Hardware
|
||||
/// Sequencing Commands and Opcode Requirements"
|
||||
///
|
||||
typedef enum {
|
||||
EnumSpiOperationWriteStatus,
|
||||
EnumSpiOperationProgramData_1_Byte,
|
||||
EnumSpiOperationProgramData_64_Byte,
|
||||
EnumSpiOperationReadData,
|
||||
EnumSpiOperationWriteDisable,
|
||||
EnumSpiOperationReadStatus,
|
||||
EnumSpiOperationWriteEnable,
|
||||
EnumSpiOperationFastRead,
|
||||
EnumSpiOperationEnableWriteStatus,
|
||||
EnumSpiOperationErase_256_Byte,
|
||||
EnumSpiOperationErase_4K_Byte,
|
||||
EnumSpiOperationErase_8K_Byte,
|
||||
EnumSpiOperationErase_64K_Byte,
|
||||
EnumSpiOperationFullChipErase,
|
||||
EnumSpiOperationJedecId,
|
||||
EnumSpiOperationDualOutputFastRead,
|
||||
EnumSpiOperationDiscoveryParameters,
|
||||
EnumSpiOperationOther,
|
||||
EnumSpiOperationMax
|
||||
} SPI_OPERATION;
|
||||
|
||||
///
|
||||
/// SPI Command Configuration
|
||||
/// Frequency The expected frequency to be used (value to be programmed to the SSFC
|
||||
/// Register)
|
||||
/// Operation Which Hardware Sequencing required operation this opcode respoinds to.
|
||||
/// The required operations are listed in EDS Table 5-55: "Hardware
|
||||
/// Sequencing Commands and Opcode Requirements"
|
||||
/// If the opcode does not corresponds to any operation listed, use
|
||||
/// EnumSpiOperationOther, and provides TYPE and Code for it in
|
||||
/// SpecialOpcodeEntry.
|
||||
///
|
||||
typedef struct _SPI_OPCODE_MENU_ENTRY {
|
||||
SPI_OPCODE_TYPE Type;
|
||||
UINT8 Code;
|
||||
SPI_CYCLE_FREQUENCY Frequency;
|
||||
SPI_OPERATION Operation;
|
||||
} SPI_OPCODE_MENU_ENTRY;
|
||||
|
||||
//
|
||||
// Initialization data table loaded to the SPI host controller
|
||||
// VendorId Vendor ID of the SPI device
|
||||
// DeviceId0 Device ID0 of the SPI device
|
||||
// DeviceId1 Device ID1 of the SPI device
|
||||
// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller
|
||||
// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu
|
||||
// BiosStartOffset The offset of the start of the BIOS image relative to the flash device.
|
||||
// Please note this is a Flash Linear Address, NOT a memory space address.
|
||||
// This value is platform specific and depends on the system flash map.
|
||||
// This value is only used on non Descriptor mode.
|
||||
// BiosSize The the BIOS Image size in flash. This value is platform specific
|
||||
// and depends on the system flash map. Please note BIOS Image size may
|
||||
// be smaller than BIOS Region size (in Descriptor Mode) or the flash size
|
||||
// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be
|
||||
// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash
|
||||
// (in Non Descriptor Mode)
|
||||
//
|
||||
typedef struct _SPI_INIT_TABLE {
|
||||
UINT8 VendorId;
|
||||
UINT8 DeviceId0;
|
||||
UINT8 DeviceId1;
|
||||
UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];
|
||||
SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];
|
||||
UINTN BiosStartOffset;
|
||||
UINTN BiosSize;
|
||||
} SPI_INIT_TABLE;
|
||||
|
||||
//
|
||||
// Protocol member functions
|
||||
//
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SPI_INIT) (
|
||||
IN EFI_SPI_PROTOCOL * This,
|
||||
IN SPI_INIT_TABLE * InitTable
|
||||
);
|
||||
|
||||
/**
|
||||
|
||||
@brief
|
||||
Initializes the host controller to execute SPI commands.
|
||||
|
||||
@param[in] This Pointer to the EFI_SPI_PROTOCOL instance.
|
||||
@param[in] InitData Pointer to caller-allocated buffer containing the SPI
|
||||
interface initialization table.
|
||||
|
||||
@retval EFI_SUCCESS Opcode initialization on the SPI host controller completed.
|
||||
@retval EFI_ACCESS_DENIED The SPI configuration interface is locked.
|
||||
@retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.
|
||||
@retval EFI_DEVICE_ERROR Device error, operation failed.
|
||||
|
||||
**/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SPI_LOCK) (
|
||||
IN EFI_SPI_PROTOCOL * This
|
||||
);
|
||||
/**
|
||||
|
||||
@brief
|
||||
Initializes the host controller to execute SPI commands.
|
||||
|
||||
@param[in] This Pointer to the EFI_SPI_PROTOCOL instance.
|
||||
@param[in] InitData Pointer to caller-allocated buffer containing the SPI
|
||||
interface initialization table.
|
||||
|
||||
@retval EFI_SUCCESS Opcode initialization on the SPI host controller completed.
|
||||
@retval EFI_ACCESS_DENIED The SPI configuration interface is locked.
|
||||
@retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.
|
||||
@retval EFI_DEVICE_ERROR Device error, operation failed.
|
||||
|
||||
**/
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_SPI_EXECUTE) (
|
||||
IN EFI_SPI_PROTOCOL * This,
|
||||
IN UINT8 OpcodeIndex,
|
||||
IN UINT8 PrefixOpcodeIndex,
|
||||
IN BOOLEAN DataCycle,
|
||||
IN BOOLEAN Atomic,
|
||||
IN BOOLEAN ShiftOut,
|
||||
IN UINTN Address,
|
||||
IN UINT32 DataByteCount,
|
||||
IN OUT UINT8 *Buffer,
|
||||
IN SPI_REGION_TYPE SpiRegionType
|
||||
);
|
||||
/**
|
||||
|
||||
@brief
|
||||
Execute SPI commands from the host controller.
|
||||
|
||||
@param[in] This Pointer to the EFI_SPI_PROTOCOL instance.
|
||||
@param[in] OpcodeIndex Index of the command in the OpCode Menu.
|
||||
@param[in] PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.
|
||||
@param[in] DataCycle TRUE if the SPI cycle contains data
|
||||
@param[in] Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.
|
||||
@param[in] ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.
|
||||
@param[in] Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform
|
||||
Region, this value specifies the offset from the Region Base; for BIOS Region,
|
||||
this value specifies the offset from the start of the BIOS Image. In Non
|
||||
Descriptor Mode, this value specifies the offset from the start of the BIOS Image.
|
||||
Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor
|
||||
Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is
|
||||
supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or
|
||||
the flash (in Non Descriptor Mode)
|
||||
@param[in] DataByteCount Number of bytes in the data portion of the SPI cycle.
|
||||
@param[in] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.
|
||||
@param[in] SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,
|
||||
EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in
|
||||
Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode
|
||||
and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative
|
||||
to base of the 1st flash device (i.e., it is a Flash Linear Address).
|
||||
|
||||
@retval EFI_SUCCESS Command succeed.
|
||||
@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
|
||||
@exception EFI_UNSUPPORTED Command not supported.
|
||||
@retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
|
||||
|
||||
**/
|
||||
|
||||
///
|
||||
/// Protocol definition
|
||||
///
|
||||
struct _EFI_SPI_PROTOCOL {
|
||||
EFI_SPI_INIT Init;
|
||||
EFI_SPI_LOCK Lock;
|
||||
EFI_SPI_EXECUTE Execute;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,94 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
TcoReset.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Protocol to communicate with ICH TCO.
|
||||
|
||||
GUID Info:
|
||||
{A6A79162-E325-4c30-BCC3-59373064EFB3}
|
||||
0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3);
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _TCO_RESET_H_
|
||||
#define _TCO_RESET_H_
|
||||
|
||||
|
||||
#define EFI_TCO_RESET_PROTOCOL_GUID \
|
||||
{0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3}
|
||||
|
||||
typedef struct _EFI_TCO_RESET_PROTOCOL EFI_TCO_RESET_PROTOCOL;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET) (
|
||||
IN UINT32 *RcrbGcsSaveValue
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Enables the TCO timer to reset the system in case of a system hang. This is
|
||||
used when writing the clock registers.
|
||||
|
||||
Arguments:
|
||||
|
||||
RcrbGcsSaveValue - This is the value of the RCRB GCS register before it is
|
||||
changed by this procedure. This will be used to restore
|
||||
the settings of this register in PpiDisableTcoReset.
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_STATUS
|
||||
|
||||
--*/
|
||||
;
|
||||
|
||||
typedef
|
||||
EFI_STATUS
|
||||
(EFIAPI *EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET) (
|
||||
OUT UINT32 RcrbGcsRestoreValue
|
||||
)
|
||||
/*++
|
||||
|
||||
Routine Description:
|
||||
|
||||
Disables the TCO timer. This is used after writing the clock registers.
|
||||
|
||||
Arguments:
|
||||
|
||||
RcrbGcsRestoreValue - Value saved in PpiEnableTcoReset so that it can
|
||||
restored.
|
||||
|
||||
Returns:
|
||||
|
||||
EFI_STATUS
|
||||
|
||||
--*/
|
||||
;
|
||||
|
||||
typedef struct _EFI_TCO_RESET_PROTOCOL {
|
||||
EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET EnableTcoReset;
|
||||
EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET DisableTcoReset;
|
||||
} EFI_TCO_RESET_PROTOCOL;
|
||||
|
||||
extern EFI_GUID gEfiTcoResetProtocolGuid;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,34 @@
|
||||
/*++
|
||||
Copyright (c) 1996 - 2014, Intel Corporation.
|
||||
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
|
||||
|
||||
Module Name:
|
||||
|
||||
|
||||
|
||||
Abstract:
|
||||
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _RSCI_H
|
||||
#define _RSCI_H
|
||||
|
||||
typedef enum {
|
||||
NOT_APPLICABLE_RESET = 0,
|
||||
WARM_RESET = 1,
|
||||
COLD_RESET = 2,
|
||||
GLOBAL_RESET = 7,
|
||||
}ANDROID_RESET_TYPE;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,67 @@
|
||||
/*++
|
||||
|
||||
Copyright (c) 2004, Intel Corporation
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
Module Name:
|
||||
|
||||
TianoApi.h
|
||||
|
||||
Abstract:
|
||||
|
||||
Tiano intrinsic definitions.
|
||||
|
||||
|
||||
--*/
|
||||
|
||||
#ifndef _TIANO_API_H_
|
||||
#define _TIANO_API_H_
|
||||
|
||||
//
|
||||
// Pointer to internal runtime function
|
||||
//
|
||||
#define EFI_INTERNAL_FUNCTION 0x00000002
|
||||
|
||||
//
|
||||
// Pointer to internal runtime pointer
|
||||
//
|
||||
#define EFI_INTERNAL_POINTER 0x00000004
|
||||
|
||||
//
|
||||
// Pointer to internal runtime pointer
|
||||
//
|
||||
#define EFI_IPF_GP_POINTER 0x00000008
|
||||
|
||||
#define EFI_TPL_DRIVER 6
|
||||
|
||||
//
|
||||
// EFI Event Types
|
||||
//
|
||||
#define EFI_EVENT_TIMER 0x80000000
|
||||
#define EFI_EVENT_RUNTIME 0x40000000
|
||||
#define EFI_EVENT_RUNTIME_CONTEXT 0x20000000
|
||||
|
||||
#define EFI_EVENT_NOTIFY_WAIT 0x00000100
|
||||
#define EFI_EVENT_NOTIFY_SIGNAL 0x00000200
|
||||
|
||||
#define EFI_EVENT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201
|
||||
#define EFI_EVENT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202
|
||||
|
||||
#define EFI_EVENT_EFI_SIGNAL_MASK 0x000000FF
|
||||
#define EFI_EVENT_EFI_SIGNAL_MAX 4
|
||||
|
||||
//
|
||||
// Task priority level
|
||||
//
|
||||
#define EFI_TPL_APPLICATION 4
|
||||
#define EFI_TPL_CALLBACK 8
|
||||
#define EFI_TPL_NOTIFY 16
|
||||
#define EFI_TPL_HIGH_LEVEL 31
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user